Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23156

1

T1

17

T2

23

T3

134

auto[ADC_CTRL_FILTER_COND_OUT]

3264

1

T3

42

T9

1

T11

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20896

1

T1

17

T3

142

T6

20

auto[1]

5524

1

T2

23

T3

34

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	760	1			T3	6		T9	1		T11	8
values[0]	31	1			T284	1		T189	8		T191	15
values[1]	717	1			T22	20		T25	7		T26	24
values[2]	2723	1			T2	23		T3	14		T4	3
values[3]	577	1			T1	17		T22	1		T41	1
values[4]	579	1			T25	1		T247	17		T54	9
values[5]	618	1			T7	21		T27	1		T55	17
values[6]	726	1			T122	7		T92	17		T123	10
values[7]	833	1			T11	5		T34	3		T128	13
values[8]	642	1			T3	28		T7	23		T9	1
values[9]	763	1			T25	21		T26	20		T35	10
minimum	17451	1			T3	128		T6	20		T9	202

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	615	1			T3	14		T9	1		T25	7
values[1]	2673	1			T2	23		T4	3		T5	5
values[2]	632	1			T1	17		T22	1		T41	1
values[3]	550	1			T7	21		T25	1		T247	17
values[4]	594	1			T27	1		T216	11		T92	3
values[5]	756	1			T122	7		T234	1		T92	17
values[6]	840	1			T9	1		T11	5		T34	3
values[7]	593	1			T3	28		T7	23		T22	16
values[8]	840	1			T26	20		T35	10		T153	1
values[9]	167	1			T283	1		T188	27		T279	32
minimum	18160	1			T3	134		T6	20		T9	203

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T25	2		T36	2		T92	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	1		T9	1		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T2	3		T4	3		T5	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T264	10		T251	17		T270	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	9		T22	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T234	1		T40	2		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	8		T54	5		T55	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T25	1		T247	8		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T92	1		T76	1		T274	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T27	1		T216	11		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T92	1		T76	1		T318	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T122	7		T234	1		T237	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	1		T34	2		T238	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T11	2		T128	13		T54	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	14		T34	3		T122	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	20		T22	9		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T35	7		T153	1		T83	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T26	12		T80	1		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T188	14		T279	16		T324	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T283	1		T336	4		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17835	1			T3	134		T6	20		T9	201
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T26	13		T36	2		T83	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T25	5		T36	1		T92	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	13		T42	6		T37	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T2	20		T244	10		T252	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T251	14		T270	9		T246	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	8		T123	7		T236	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T40	2		T289	11		T189	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	13		T54	4		T55	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T247	9		T84	2		T337	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T92	2		T76	12		T132	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T78	16		T123	5		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T92	16		T76	2		T318	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T237	9		T239	14		T258	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	1		T238	1		T239	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	3		T54	2		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	9		T34	1		T122	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T3	8		T22	7		T25	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T35	3		T83	12		T129	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T26	8		T84	1		T125	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T188	13		T279	16		T324	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T336	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	2		T11	2		T22	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T26	11		T36	1		T83	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	545	1			T3	6		T9	1		T11	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T125	12		T283	1		T126	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T284	1		T189	1		T191	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T338	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T22	10		T25	2		T55	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T26	13		T42	1		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1452	1			T2	3		T4	3		T5	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T9	1		T264	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	9		T22	1		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T234	1		T40	2		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T54	5		T236	4		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T25	1		T247	8		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	8		T55	8		T92	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T27	1		T216	11		T78	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T92	1		T318	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T122	7		T123	5		T237	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T34	2		T238	1		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	2		T128	13		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	14		T9	1		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	20		T22	9		T122	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T35	7		T153	1		T83	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T25	11		T26	12		T80	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17342	1			T3	128		T6	20		T9	200
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T271	8		T188	13		T279	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T125	9		T135	3		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T189	7		T191	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T22	10		T25	5		T55	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T26	11		T42	6		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	913	1			T2	20		T244	10		T252	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	13		T40	1		T251	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T1	8		T129	10		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	2		T339	8		T289	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T54	4		T236	3		T133	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T247	9		T84	2		T337	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	13		T55	9		T92	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T78	16		T157	11		T172	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T92	16		T318	2		T259	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T123	5		T237	9		T258	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	1		T238	1		T239	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	3		T54	2		T37	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	9		T34	1		T122	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	8		T22	7		T122	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T35	3		T83	12		T129	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T25	10		T26	8		T84	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T25	7		T36	3		T92	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	14		T9	1		T42	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T2	23		T4	3		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T264	1		T251	15		T270	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	9		T22	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T234	1		T40	4		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	14		T54	5		T55	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T25	1		T247	10		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T92	3		T76	13		T274	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T27	1		T216	1		T78	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T92	17		T76	3		T318	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T122	1		T234	1		T237	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	1		T34	2		T238	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	5		T128	1		T54	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	10		T34	3		T122	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	10		T22	8		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T35	9		T153	1		T83	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T26	9		T80	1		T84	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T188	14		T279	17		T324	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T283	1		T336	6		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17953	1			T3	134		T6	20		T9	203
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T26	12		T36	3		T83	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T38	5		T144	4		T14	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T37	9		T40	1		T143	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1128	1			T5	4		T12	8		T124	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T264	9		T251	16		T270	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	8		T123	7		T236	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T230	14		T142	13		T313	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	7		T54	4		T55	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T247	7		T84	10		T263	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T132	16		T273	12		T133	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T216	10		T123	4		T210	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T143	9		T259	8		T202	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T122	6		T237	9		T258	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T34	1		T154	11		T251	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T128	12		T54	13		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	13		T34	1		T122	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	18		T22	8		T25	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T35	1		T83	8		T144	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T26	11		T125	11		T126	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T188	13		T279	15		T205	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T22	9		T55	11		T140	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T26	12		T83	10		T154	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	565	1			T3	6		T9	1		T11	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T125	10		T283	1		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T284	1		T189	8		T191	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T338	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T22	11		T25	7		T55	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T26	12		T42	7		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T2	23		T4	3		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	14		T9	1		T264	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	9		T22	1		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T234	1		T40	4		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T54	5		T236	4		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T25	1		T247	10		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	14		T55	10		T92	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T27	1		T216	1		T78	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T92	17		T318	3		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T122	1		T123	6		T237	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T34	2		T238	2		T239	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T11	5		T128	1		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	10		T9	1		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	10		T22	8		T122	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T35	9		T153	1		T83	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T25	11		T26	9		T80	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17451	1			T3	128		T6	20		T9	202
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T271	7		T188	13		T279	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T125	11		T126	9		T135	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T191	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T338	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T22	9		T55	11		T38	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T26	12		T83	10		T37	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T5	4		T12	8		T124	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T264	9		T40	1		T251	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T1	8		T129	10		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T339	11		T230	14		T142	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T54	4		T236	3		T133	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T247	7		T84	10		T263	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T7	7		T55	7		T132	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T216	10		T255	7		T299	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T143	9		T259	8		T202	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T122	6		T123	4		T237	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	1		T154	11		T251	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T128	12		T54	13		T37	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	13		T34	1		T122	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	18		T22	8		T122	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T35	1		T83	8		T133	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T25	10		T26	11		T253	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4