Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23003

1

T2

23

T3

162

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3417

1

T1

17

T3

14

T11

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20869

1

T3

176

T6

20

T7

44

auto[1]

5551

1

T1

17

T2

23

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	383	1			T55	17		T78	17		T318	1
values[0]	25	1			T266	10		T142	14		T267	1
values[1]	519	1			T3	14		T27	1		T122	22
values[2]	638	1			T25	21		T13	3		T233	1
values[3]	676	1			T1	17		T26	24		T122	1
values[4]	548	1			T3	14		T22	1		T25	7
values[5]	754	1			T7	23		T11	5		T34	3
values[6]	745	1			T9	1		T26	20		T27	1
values[7]	605	1			T41	1		T34	4		T92	3
values[8]	741	1			T9	1		T22	36		T153	1
values[9]	2923	1			T2	23		T3	14		T4	3
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	564	1			T3	14		T25	21		T27	1
values[1]	600	1			T1	17		T233	1		T37	25
values[2]	619	1			T3	14		T25	7		T26	24
values[3]	691	1			T22	1		T122	7		T54	9
values[4]	740	1			T7	23		T11	5		T34	3
values[5]	663	1			T9	1		T26	20		T27	1
values[6]	2619	1			T2	23		T4	3		T5	5
values[7]	617	1			T9	1		T22	16		T153	1
values[8]	1090	1			T3	14		T7	21		T25	1
values[9]	152	1			T42	7		T78	17		T38	18
minimum	18065	1			T3	134		T6	20		T9	203

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	10		T13	2		T36	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T25	11		T27	1		T291	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T233	1		T127	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	9		T37	17		T237	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T247	8		T35	7		T123	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	1		T25	2		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T122	7		T92	1		T129	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T22	1		T54	5		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T7	14		T216	22		T84	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	2		T34	2		T122	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T9	1		T27	1		T259	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T26	12		T83	9		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T2	3		T4	3		T5	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T22	10		T272	1		T259	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	1		T84	11		T274	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T22	9		T153	1		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T3	10		T7	8		T128	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T25	1		T234	2		T55	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T42	1		T279	16		T297	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T78	1		T38	10		T280	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17825	1			T3	134		T6	20		T9	201
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T122	10		T129	1		T266	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T3	4		T13	1		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T25	10		T296	2		T276	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T270	9		T14	4		T271	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	8		T37	8		T237	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T247	9		T35	3		T123	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	13		T25	5		T26	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T92	16		T129	10		T202	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T54	4		T83	8		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	9		T84	5		T238	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	3		T34	1		T122	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T259	7		T135	3		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T26	8		T83	12		T239	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	841	1			T2	20		T34	1		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T22	10		T272	4		T259	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T84	2		T243	13		T157	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T22	7		T40	1		T255	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T3	4		T7	13		T55	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T55	9		T76	12		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T42	6		T279	16		T297	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T78	16		T38	8		T280	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	2		T11	2		T55	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T122	12		T129	1		T266	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T55	8		T213	1		T271	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T78	1		T318	1		T40	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T142	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T266	1		T267	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	10		T55	12		T36	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T27	1		T122	10		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	2		T233	1		T123	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T25	11		T37	17		T132	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T247	8		T35	7		T92	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	9		T26	13		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T122	7		T129	11		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T22	1		T25	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	14		T216	11		T274	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T11	2		T34	2		T54	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T9	1		T27	1		T216	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T26	12		T122	12		T92	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T41	1		T34	3		T92	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T273	13		T259	14		T210	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	1		T84	11		T274	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T22	19		T153	1		T76	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1513	1			T2	3		T3	10		T4	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T25	1		T234	2		T55	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T55	9		T213	7		T271	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T78	16		T40	1		T285	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T266	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T3	4		T55	9		T36	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T122	12		T129	1		T276	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	1		T123	5		T134	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T25	10		T37	8		T132	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T247	9		T35	3		T92	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	8		T26	11		T237	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T129	10		T157	4		T192	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	13		T25	5		T54	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T7	9		T238	1		T202	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	3		T34	1		T54	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T84	5		T259	7		T135	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T26	8		T122	14		T92	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T34	1		T92	2		T259	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T259	2		T235	1		T45	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T84	2		T243	13		T157	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T22	17		T76	12		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	920	1			T2	20		T3	4		T7	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T55	9		T38	8		T154	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	5		T13	3		T36	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T25	11		T27	1		T291	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T233	1		T127	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	9		T37	14		T237	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T247	10		T35	9		T123	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	14		T25	7		T26	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T122	1		T92	17		T129	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T22	1		T54	5		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	10		T216	2		T84	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	5		T34	2		T122	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	1		T27	1		T259	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T26	9		T83	13		T239	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1163	1			T2	23		T4	3		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T22	11		T272	5		T259	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	1		T84	3		T274	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T22	8		T153	1		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T3	5		T7	14		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T25	1		T234	2		T55	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T42	7		T279	17		T297	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T78	17		T38	13		T280	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17914	1			T3	134		T6	20		T9	203
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T122	13		T129	2		T266	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T3	9		T123	4		T134	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T25	10		T278	13		T296	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T270	10		T263	11		T14	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	8		T37	11		T237	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T247	7		T35	1		T123	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T26	12		T54	13		T154	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T122	6		T129	10		T144	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T54	4		T83	10		T133	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	13		T216	20		T264	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T34	1		T122	11		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T259	8		T135	9		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T26	11		T83	8		T273	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1123	1			T5	4		T12	8		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T22	9		T259	13		T210	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T84	10		T243	13		T192	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T22	8		T143	18		T255	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T3	9		T7	7		T128	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T55	7		T40	1		T154	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T279	15		T297	9		T340	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T38	5		T280	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T55	11		T313	10		T178	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T122	9		T203	1		T188	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T55	10		T213	8		T271	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T78	17		T318	1		T40	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T142	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T266	10		T267	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	5		T55	10		T36	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T27	1		T122	13		T129	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	3		T233	1		T123	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T25	11		T37	14		T132	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T247	10		T35	9		T92	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	9		T26	12		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T122	1		T129	11		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	14		T22	1		T25	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	10		T216	1		T274	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	5		T34	2		T54	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	1		T27	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T26	9		T122	15		T92	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T41	1		T34	3		T92	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T273	1		T259	3		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	1		T84	3		T274	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T22	19		T153	1		T76	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T2	23		T3	5		T4	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T25	1		T234	2		T55	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T55	7		T271	7		T140	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T40	1		T285	13		T341	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T142	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T3	9		T55	11		T313	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T122	9		T278	13		T276	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T123	4		T134	14		T270	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T25	10		T37	11		T132	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T247	7		T35	1		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	8		T26	12		T237	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T122	6		T129	10		T144	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T54	13		T133	9		T251	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	13		T216	10		T264	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T34	1		T54	4		T83	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T216	10		T259	8		T135	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T26	11		T122	11		T83	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	1		T236	15		T126	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T273	12		T259	13		T210	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T84	10		T243	13		T246	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T22	17		T143	18		T210	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1165	1			T3	9		T5	4		T7	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T55	7		T38	5		T154	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4