Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23243

1

T2

23

T3

148

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3177

1

T1

17

T3

28

T7

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21081

1

T1

17

T3

162

T6

20

auto[1]

5339

1

T2

23

T3

14

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	354	1			T25	28		T54	9		T55	17
values[0]	28	1			T150	8		T342	4		T302	6
values[1]	737	1			T13	3		T128	13		T54	16
values[2]	558	1			T3	14		T22	20		T34	3
values[3]	690	1			T26	20		T234	1		T233	1
values[4]	651	1			T22	1		T55	21		T216	11
values[5]	550	1			T3	14		T9	1		T22	16
values[6]	688	1			T1	17		T3	14		T25	1
values[7]	532	1			T11	5		T41	1		T241	1
values[8]	2736	1			T2	23		T4	3		T5	5
values[9]	1033	1			T7	21		T9	1		T27	1
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	593	1			T13	3		T84	2		T129	2
values[1]	624	1			T3	14		T22	20		T34	3
values[2]	763	1			T26	20		T216	11		T92	17
values[3]	610	1			T9	1		T22	17		T26	24
values[4]	666	1			T1	17		T3	28		T27	1
values[5]	480	1			T25	1		T122	22		T241	1
values[6]	2685	1			T2	23		T4	3		T5	5
values[7]	758	1			T7	23		T76	13		T236	7
values[8]	990	1			T7	21		T9	1		T25	7
values[9]	151	1			T25	21		T27	1		T54	9
minimum	18100	1			T3	134		T6	20		T9	203

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	2		T129	1		T125	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T84	1		T132	17		T273	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T34	2		T233	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	1		T22	10		T234	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T216	11		T144	12		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T26	12		T92	1		T37	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	1		T22	10		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T55	12		T36	2		T84	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	10		T27	1		T236	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	9		T3	10		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T122	10		T241	1		T123	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T25	1		T83	9		T154	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1528	1			T2	3		T4	3		T5	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	2		T123	5		T37	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T7	14		T39	2		T40	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T76	1		T236	4		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T9	1		T247	8		T55	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T7	8		T25	2		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T54	5		T278	14		T179	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T25	11		T27	1		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17824	1			T3	134		T6	20		T9	201
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T128	13		T80	1		T40	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	1		T129	1		T150	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T84	1		T132	11		T150	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T34	1		T78	16		T83	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T3	13		T22	10		T55	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T259	2		T192	14		T135	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T26	8		T92	16		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T22	7		T26	11		T237	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T55	9		T36	1		T84	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	4		T40	1		T253	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	8		T3	4		T42	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T122	12		T123	7		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T83	12		T154	8		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T2	20		T244	10		T252	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T11	3		T123	5		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	9		T40	2		T251	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T76	12		T236	3		T238	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T247	9		T55	9		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T7	13		T25	5		T92	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T54	4		T179	12		T292	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T25	10		T239	14		T339	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	2		T11	2		T54	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T40	1		T154	12		T202	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T54	5		T55	8		T318	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T25	13		T144	5		T126	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T342	1		T302	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T150	1		T305	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	2		T54	14		T216	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T128	13		T80	1		T84	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T34	2		T153	1		T78	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T3	1		T22	10		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T233	1		T151	1		T259	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T26	12		T234	1		T55	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T22	1		T216	11		T274	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T55	12		T36	2		T92	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	1		T22	9		T26	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	10		T122	7		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	10		T27	1		T122	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	9		T25	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T41	1		T241	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	2		T123	5		T37	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T2	3		T4	3		T5	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T76	1		T259	9		T246	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T9	1		T247	8		T36	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T7	8		T27	1		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T54	4		T55	9		T318	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T25	15		T277	9		T309	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T342	3		T302	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T150	7		T305	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	1		T54	2		T35	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T84	1		T132	11		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T34	1		T78	16		T83	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T3	13		T22	10		T134	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T259	2		T157	7		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T26	8		T55	9		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T237	9		T251	14		T192	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T55	9		T36	1		T92	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T22	7		T26	11		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T3	4		T84	2		T270	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	4		T122	12		T123	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	8		T42	6		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T40	2		T258	10		T14	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T11	3		T123	5		T37	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T2	20		T7	9		T244	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T76	12		T259	7		T246	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T247	9		T36	1		T76	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T7	13		T92	2		T84	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	3		T129	2		T125	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T84	2		T132	12		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T34	2		T233	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	14		T22	11		T234	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T216	1		T144	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	9		T92	17		T37	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	1		T22	9		T26	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T55	10		T36	3		T84	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	5		T27	1		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	9		T3	5		T42	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T122	13		T241	1		T123	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T25	1		T83	13		T154	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T2	23		T4	3		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	5		T123	6		T37	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	10		T39	2		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T76	13		T236	4		T238	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T247	10		T55	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T7	14		T25	7		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T54	5		T278	1		T179	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T25	11		T27	1		T239	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17924	1			T3	134		T6	20		T9	203
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T128	1		T80	1		T40	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T210	6		T243	13		T192	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T132	16		T273	12		T192	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T34	1		T83	10		T129	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T22	9		T55	7		T210	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T216	10		T144	11		T259	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T26	11		T37	2		T136	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T22	8		T26	12		T237	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T55	11		T84	10		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	9		T236	15		T253	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	8		T3	9		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T122	9		T123	7		T154	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T83	8		T154	6		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T5	4		T12	8		T124	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T123	4		T37	9		T259	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	13		T144	8		T126	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T236	3		T259	8		T246	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T247	7		T55	7		T133	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T7	7		T40	1		T126	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T54	4		T278	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T25	10		T144	4		T339	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T54	13		T216	10		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T128	12		T40	1		T154	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T54	5		T55	10		T318	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T25	18		T144	1		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T342	4		T302	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T150	8		T305	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	3		T54	3		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T128	1		T80	1		T84	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T34	2		T153	1		T78	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T3	14		T22	11		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T233	1		T151	1		T259	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T26	9		T234	1		T55	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T22	1		T216	1		T274	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T55	10		T36	3		T92	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T22	8		T26	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T3	5		T122	1		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	5		T27	1		T122	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	9		T25	1		T42	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T41	1		T241	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T11	5		T123	6		T37	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T2	23		T4	3		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T76	13		T259	8		T246	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	1		T247	10		T36	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T7	14		T27	1		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T54	4		T55	7		T245	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T25	10		T144	4		T126	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T54	13		T216	10		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T128	12		T132	16		T273	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T34	1		T83	10		T129	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T22	9		T210	5		T281	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T259	13		T258	3		T135	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T26	11		T55	7		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T216	10		T237	9		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T55	11		T135	9		T136	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T22	8		T26	12		T135	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	9		T122	6		T84	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	9		T122	9		T123	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	8		T34	1		T122	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T258	11		T281	14		T14	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T123	4		T37	9		T259	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T5	4		T7	13		T12	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T259	8		T246	11		T296	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T247	7		T133	8		T143	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T7	7		T236	3		T40	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4