Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23226

1

T2

23

T3

162

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3194

1

T1

17

T3

14

T7

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20960

1

T1

17

T3

162

T6

20

auto[1]

5460

1

T2

23

T3

14

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	249	1			T92	3		T318	1		T40	3
values[0]	35	1			T292	10		T343	12		T316	13
values[1]	713	1			T42	7		T122	1		T13	3
values[2]	2453	1			T2	23		T3	14		T4	3
values[3]	615	1			T1	17		T247	17		T216	11
values[4]	532	1			T22	20		T27	1		T34	3
values[5]	850	1			T7	23		T26	20		T234	1
values[6]	896	1			T3	14		T34	4		T54	9
values[7]	585	1			T25	7		T78	17		T125	21
values[8]	574	1			T7	21		T9	1		T22	17
values[9]	1055	1			T3	14		T9	1		T11	5
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	644	1			T3	14		T128	13		T36	3
values[1]	2450	1			T2	23		T4	3		T5	5
values[2]	685	1			T1	17		T234	1		T247	17
values[3]	616	1			T22	20		T27	1		T34	3
values[4]	793	1			T3	14		T7	23		T26	20
values[5]	868	1			T25	7		T34	4		T54	9
values[6]	470	1			T41	1		T153	1		T76	13
values[7]	636	1			T3	14		T7	21		T9	1
values[8]	1072	1			T9	1		T11	5		T26	24
values[9]	96	1			T40	3		T144	9		T259	16
minimum	18090	1			T3	134		T6	20		T9	203

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T128	13		T36	2		T132	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T38	10		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T2	3		T4	3		T5	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T129	11		T239	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T247	8		T92	1		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T1	9		T234	1		T216	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T27	1		T34	2		T274	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T22	10		T233	1		T35	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T3	10		T26	12		T55	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	14		T234	1		T238	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T25	2		T34	3		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T54	5		T130	1		T125	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T41	1		T78	1		T83	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T153	1		T76	1		T283	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	10		T22	10		T122	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	8		T9	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T26	13		T122	22		T55	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T9	1		T11	2		T55	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T40	2		T203	1		T289	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T144	9		T259	9		T328	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17790	1			T3	134		T6	20		T9	201
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T42	1		T122	1		T80	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T36	1		T132	11		T236	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	13		T38	8		T259	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	873	1			T2	20		T25	10		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T129	10		T239	14		T148	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T247	9		T92	16		T76	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T1	8		T84	4		T123	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T34	1		T318	2		T150	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T22	10		T35	3		T154	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	4		T26	8		T55	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	9		T238	1		T243	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T25	5		T34	1		T150	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T54	4		T125	9		T123	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T78	16		T83	8		T239	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T76	12		T154	12		T296	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T3	4		T22	7		T192	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	13		T54	2		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T26	11		T122	26		T55	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	3		T55	9		T40	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T40	1		T289	11		T254	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T259	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	2		T11	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T42	6		T192	4		T262	16

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T92	1		T318	1		T40	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T144	9		T127	1		T259	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T316	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T292	1		T343	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	2		T36	2		T132	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T42	1		T122	1		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T2	3		T4	3		T5	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T3	1		T129	11		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T247	8		T92	1		T84	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	9		T216	11		T123	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T27	1		T34	2		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T22	10		T234	1		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T26	12		T55	8		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	14		T234	1		T35	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T3	10		T34	3		T241	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T54	5		T130	1		T123	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T25	2		T78	1		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T125	12		T283	1		T264	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T22	10		T41	1		T122	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	8		T9	1		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T3	10		T26	13		T122	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T9	1		T11	2		T55	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T92	2		T40	1		T251	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T259	7		T270	9		T32	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T316	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T292	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	1		T36	1		T132	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T42	6		T38	8		T259	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	849	1			T2	20		T25	10		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T3	13		T129	10		T239	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T247	9		T92	16		T84	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T1	8		T123	5		T245	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T34	1		T76	2		T150	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T22	10		T84	4		T154	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T26	8		T55	9		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	9		T35	3		T238	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T3	4		T34	1		T83	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T54	4		T123	7		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T25	5		T78	16		T239	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T125	9		T154	12		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T22	7		T83	8		T192	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	13		T54	2		T76	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	4		T26	11		T122	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	3		T55	9		T237	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T128	1		T36	3		T132	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	14		T38	13		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T2	23		T4	3		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T129	11		T239	15		T148	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T247	10		T92	17		T76	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	9		T234	1		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T27	1		T34	2		T274	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T22	11		T233	1		T35	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	5		T26	9		T55	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	10		T234	1		T238	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T25	7		T34	3		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T54	5		T130	1		T125	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T41	1		T78	17		T83	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T153	1		T76	13		T283	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	5		T22	9		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	14		T9	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T26	12		T122	28		T55	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T9	1		T11	5		T55	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T40	3		T203	1		T289	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T144	1		T259	8		T328	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17920	1			T3	134		T6	20		T9	203
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T42	7		T122	1		T80	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T128	12		T132	16		T236	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T38	5		T259	13		T245	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1088	1			T5	4		T12	8		T25	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T129	10		T253	15		T271	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T247	7		T84	10		T154	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	8		T216	10		T123	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T34	1		T143	18		T135	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T22	9		T35	1		T154	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	9		T26	11		T55	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	13		T243	13		T317	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T34	1		T273	12		T210	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T54	4		T125	11		T123	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T83	10		T344	12		T345	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T264	9		T154	11		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	9		T22	8		T122	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	7		T54	13		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T26	12		T122	20		T55	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T55	11		T216	10		T236	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T346	5		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T144	8		T259	8		T347	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T271	7		T348	1		T349	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T192	9		T262	10		T350	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T92	3		T318	1		T40	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T144	1		T127	1		T259	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T316	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T292	10		T343	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	3		T36	3		T132	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T42	7		T122	1		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T2	23		T4	3		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T3	14		T129	11		T239	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T247	10		T92	17		T84	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	9		T216	1		T123	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T27	1		T34	2		T76	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T22	11		T234	1		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T26	9		T55	10		T36	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	10		T234	1		T35	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T3	5		T34	3		T241	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T54	5		T130	1		T123	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T25	7		T78	17		T239	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T125	10		T283	1		T264	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T22	9		T41	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	14		T9	1		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T3	5		T26	12		T122	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	1		T11	5		T55	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T40	1		T251	11		T351	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T144	8		T259	8		T270	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T343	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T132	16		T236	3		T210	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T38	5		T259	13		T192	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1108	1			T5	4		T12	8		T25	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T129	10		T253	15		T344	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T247	7		T84	10		T154	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	8		T216	10		T123	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T34	1		T143	18		T126	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T22	9		T154	6		T133	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T26	11		T55	7		T133	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	13		T35	1		T243	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T3	9		T34	1		T83	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T54	4		T123	7		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T344	12		T313	5		T338	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T125	11		T264	9		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T22	8		T122	6		T83	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	7		T54	13		T296	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T3	9		T26	12		T122	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T55	11		T216	10		T237	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4