Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20786

1

T3

162

T6

20

T9

205

auto[ADC_CTRL_FILTER_COND_OUT]

5634

1

T1

17

T2

23

T3

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21118

1

T1

17

T3

148

T6

20

auto[1]

5302

1

T2

23

T3

28

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	359	1			T1	17		T3	14		T128	13
values[0]	87	1			T141	1		T331	18		T159	8
values[1]	658	1			T22	1		T26	20		T27	1
values[2]	559	1			T7	23		T34	7		T122	7
values[3]	653	1			T3	14		T26	24		T153	1
values[4]	436	1			T9	1		T22	36		T247	17
values[5]	552	1			T13	3		T55	17		T83	21
values[6]	880	1			T7	21		T25	21		T122	1
values[7]	718	1			T41	1		T42	7		T122	26
values[8]	745	1			T3	14		T25	8		T92	17
values[9]	2910	1			T2	23		T4	3		T5	5
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	578	1			T26	20		T27	1		T234	1
values[1]	2653	1			T2	23		T4	3		T5	5
values[2]	567	1			T3	14		T9	1		T54	16
values[3]	476	1			T22	36		T13	3		T247	17
values[4]	613	1			T25	21		T122	1		T55	17
values[5]	777	1			T7	21		T55	21		T76	16
values[6]	823	1			T25	7		T41	1		T42	7
values[7]	669	1			T3	14		T25	1		T241	1
values[8]	1049	1			T1	17		T3	14		T9	1
values[9]	88	1			T264	10		T291	1		T156	1
minimum	18127	1			T3	134		T6	20		T9	203

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T26	12		T234	1		T216	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T27	1		T92	1		T40	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T26	13		T54	5		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1467	1			T2	3		T4	3		T5	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	1		T54	14		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T36	2		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T13	2		T247	8		T291	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T22	19		T216	11		T83	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T25	11		T55	8		T144	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T122	1		T123	5		T275	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T76	1		T130	1		T237	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	8		T55	12		T76	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T25	2		T41	1		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T122	12		T55	8		T92	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	10		T241	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T25	1		T78	1		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T3	10		T9	1		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T1	9		T27	1		T122	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T264	10		T156	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T291	1		T352	1		T300	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17842	1			T3	134		T6	20		T9	201
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T22	1		T83	11		T301	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T26	8		T129	10		T154	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T92	2		T40	3		T192	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T26	11		T54	4		T125	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	908	1			T2	20		T7	9		T34	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T54	2		T36	1		T259	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	13		T36	1		T134	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	1		T247	9		T272	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T22	17		T83	12		T236	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T25	10		T55	9		T192	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T123	5		T296	2		T31	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T76	2		T237	9		T213	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	13		T55	9		T76	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T25	5		T42	6		T84	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T122	14		T55	9		T92	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	4		T251	10		T157	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T78	16		T84	1		T123	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	4		T11	3		T35	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	8		T122	12		T37	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T139	7		T183	13		T287	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	2		T11	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T83	8		T136	11		T331	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	10		T238	1		T264	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T1	9		T128	13		T37	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T141	1		T333	18		T194	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T331	12		T159	8		T287	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T26	12		T216	11		T129	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T22	1		T27	1		T83	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T234	1		T54	5		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	14		T34	5		T122	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T26	13		T125	12		T318	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	1		T153	1		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T9	1		T247	8		T54	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T22	19		T216	11		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	2		T55	8		T272	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T83	9		T123	5		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T25	11		T237	10		T273	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T7	8		T122	1		T55	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T41	1		T42	1		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T122	12		T55	8		T92	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	10		T25	2		T241	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T25	1		T92	1		T78	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T9	1		T11	2		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1543	1			T2	3		T4	3		T5	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T3	4		T238	1		T133	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T1	8		T37	2		T270	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T333	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T331	6		T287	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T26	8		T129	10		T37	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T83	8		T40	3		T192	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T54	4		T239	14		T213	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	9		T34	2		T92	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T26	11		T125	9		T318	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	13		T134	9		T246	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T247	9		T54	2		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T22	17		T36	1		T236	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T13	1		T55	9		T272	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T83	12		T123	5		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T25	10		T237	9		T213	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	13		T55	9		T76	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T42	6		T76	2		T84	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T122	14		T55	9		T92	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	4		T25	5		T251	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T92	16		T78	16		T84	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	3		T35	3		T84	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	919	1			T2	20		T244	10		T122	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T26	9		T234	1		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T27	1		T92	3		T40	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T26	12		T54	5		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1238	1			T2	23		T4	3		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	1		T54	3		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	14		T36	3		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T13	3		T247	10		T291	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T22	19		T216	1		T83	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T25	11		T55	10		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T122	1		T123	6		T275	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T76	3		T130	1		T237	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T7	14		T55	10		T76	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T25	7		T41	1		T42	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T122	15		T55	10		T92	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	5		T241	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T25	1		T78	17		T84	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T3	5		T9	1		T11	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	9		T27	1		T122	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T264	1		T156	1		T139	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T291	1		T352	1		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17926	1			T3	134		T6	20		T9	203
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T22	1		T83	9		T301	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T26	11		T216	10		T129	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T258	3		T192	17		T276	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T26	12		T54	4		T125	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1137	1			T5	4		T7	13		T12	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T54	13		T259	9		T255	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T246	10		T227	7		T173	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T247	7		T230	14		T353	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T22	17		T216	10		T83	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T25	10		T55	7		T144	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T123	4		T281	11		T296	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T237	9		T14	3		T339	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	7		T55	11		T38	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T273	12		T136	4		T271	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T122	11		T55	7		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	9		T236	15		T144	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T123	7		T144	4		T210	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T3	9		T35	1		T84	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	8		T122	9		T128	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T264	9		T183	13		T287	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T300	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T37	9		T210	6		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T83	10		T136	4		T331	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	5		T238	2		T264	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T1	9		T128	1		T37	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T141	1		T333	20		T194	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T331	11		T159	1		T287	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T26	9		T216	1		T129	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T22	1		T27	1		T83	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T234	1		T54	5		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	10		T34	5		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T26	12		T125	10		T318	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	14		T153	1		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	1		T247	10		T54	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T22	19		T216	1		T36	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T13	3		T55	10		T272	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T83	13		T123	6		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T25	11		T237	10		T273	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T7	14		T122	1		T55	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T41	1		T42	7		T76	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T122	15		T55	10		T92	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	5		T25	7		T241	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T25	1		T92	17		T78	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	1		T11	5		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1251	1			T2	23		T4	3		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	9		T264	9		T133	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T1	8		T128	12		T37	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T333	12		T194	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T331	7		T159	7		T287	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T26	11		T216	10		T129	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T83	10		T258	3		T192	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T54	4		T306	3		T191	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	13		T34	2		T122	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T26	12		T125	11		T259	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T246	10		T227	7		T317	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T247	7		T54	13		T230	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T22	17		T216	10		T236	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T55	7		T144	8		T192	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T83	8		T123	4		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T25	10		T237	9		T273	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	7		T55	11		T38	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T136	4		T271	7		T204	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T122	11		T55	7		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T3	9		T144	11		T251	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T210	13		T258	11		T135	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T35	1		T84	10		T132	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1211	1			T5	4		T12	8		T122	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4