Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23236

1

T2

23

T3

162

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3184

1

T1

17

T3

14

T7

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20967

1

T1

17

T3

162

T6

20

auto[1]

5453

1

T2

23

T3

14

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	52	1			T80	1		T318	1		T251	22
values[0]	78	1			T132	28		T289	3		T354	14
values[1]	699	1			T3	14		T42	7		T122	1
values[2]	2452	1			T1	17		T2	23		T4	3
values[3]	562	1			T247	17		T216	11		T92	17
values[4]	554	1			T22	20		T27	1		T34	3
values[5]	804	1			T7	23		T26	20		T234	1
values[6]	864	1			T3	14		T25	7		T34	4
values[7]	664	1			T7	21		T78	17		T125	21
values[8]	488	1			T9	1		T22	17		T25	1
values[9]	1340	1			T3	14		T9	1		T11	5
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	822	1			T3	14		T42	7		T122	1
values[1]	2509	1			T2	23		T4	3		T5	5
values[2]	614	1			T1	17		T247	17		T92	17
values[3]	658	1			T22	20		T27	1		T34	3
values[4]	825	1			T3	14		T7	23		T26	20
values[5]	829	1			T25	7		T34	4		T54	9
values[6]	479	1			T76	13		T78	17		T83	19
values[7]	606	1			T3	14		T7	21		T9	1
values[8]	1032	1			T9	1		T11	5		T26	24
values[9]	154	1			T144	9		T259	16		T134	10
minimum	17892	1			T3	134		T6	20		T9	203

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	2		T128	13		T36	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	1		T42	1		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T2	3		T4	3		T5	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T216	11		T239	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T247	8		T92	1		T84	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	9		T129	11		T123	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T27	1		T34	2		T76	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T22	10		T234	1		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T3	10		T26	12		T55	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	14		T234	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T25	2		T34	3		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T54	5		T125	12		T123	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T78	1		T83	11		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T76	1		T283	1		T264	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	10		T22	10		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	8		T9	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T26	13		T122	22		T55	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T9	1		T11	2		T55	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T134	1		T293	2		T203	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T144	9		T259	9		T328	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17757	1			T3	134		T6	20		T9	201
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T355	10		T326	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	1		T36	1		T132	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	13		T42	6		T38	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	866	1			T2	20		T25	10		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T239	14		T148	15		T253	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T247	9		T92	16		T84	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T1	8		T129	10		T123	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T34	1		T76	2		T318	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T22	10		T35	3		T84	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	4		T26	8		T55	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	9		T238	1		T243	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T25	5		T34	1		T150	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T54	4		T125	9		T123	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T78	16		T83	8		T239	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T76	12		T154	12		T296	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T3	4		T22	7		T192	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	13		T54	2		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T26	11		T122	26		T55	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	3		T55	9		T134	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T134	9		T293	3		T289	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T259	7		T356	5		T357	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T355	14		T326	1		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T80	1		T318	1		T251	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T358	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T132	17		T289	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T354	1		T359	3		T292	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T36	2		T236	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	1		T42	1		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T2	3		T4	3		T5	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T1	9		T129	11		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T247	8		T92	1		T154	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T216	11		T123	5		T245	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T27	1		T34	2		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T22	10		T234	1		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T26	12		T55	8		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	14		T234	1		T35	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T3	10		T25	2		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T54	5		T130	1		T123	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T78	1		T239	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	8		T125	12		T283	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T22	10		T41	1		T122	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	1		T25	1		T54	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T3	10		T26	13		T122	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T9	1		T11	2		T55	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T251	10		T161	5		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T358	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T132	11		T289	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T354	13		T359	8		T292	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T36	1		T236	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	13		T42	6		T38	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	847	1			T2	20		T25	10		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T1	8		T129	10		T239	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T247	9		T92	16		T154	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T123	5		T245	3		T271	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T76	2		T84	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T22	10		T84	4		T154	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T26	8		T55	9		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	9		T35	3		T238	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	4		T25	5		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T54	4		T123	7		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T78	16		T239	10		T150	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	13		T125	9		T154	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T22	7		T83	8		T192	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T54	2		T76	12		T157	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T3	4		T26	11		T122	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	3		T55	9		T237	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	3		T128	1		T36	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	14		T42	7		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T2	23		T4	3		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T216	1		T239	15		T148	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T247	10		T92	17		T84	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	9		T129	11		T123	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T27	1		T34	2		T76	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T22	11		T234	1		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T3	5		T26	9		T55	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	10		T234	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T25	7		T34	3		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T54	5		T125	10		T123	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T78	17		T83	9		T239	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T76	13		T283	1		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T3	5		T22	9		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	14		T9	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T26	12		T122	28		T55	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	1		T11	5		T55	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T134	10		T293	5		T203	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T144	1		T259	8		T328	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17864	1			T3	134		T6	20		T9	203
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T355	15		T326	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T128	12		T132	16		T236	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T38	5		T259	13		T192	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1112	1			T5	4		T12	8		T25	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T216	10		T253	15		T271	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T247	7		T154	3		T126	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	8		T129	10		T123	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T34	1		T143	18		T135	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T22	9		T35	1		T154	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	9		T26	11		T55	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	13		T243	13		T317	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T34	1		T203	1		T139	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T54	4		T125	11		T123	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T83	10		T273	12		T344	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T264	9		T154	11		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	9		T22	8		T122	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	7		T54	13		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T26	12		T122	20		T55	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T55	11		T216	10		T236	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T20	5		T346	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T144	8		T259	8		T204	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T349	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T355	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T80	1		T318	1		T251	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T358	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T132	12		T289	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T354	14		T359	9		T292	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	3		T36	3		T236	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	14		T42	7		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1169	1			T2	23		T4	3		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T1	9		T129	11		T239	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T247	10		T92	17		T154	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T216	1		T123	6		T245	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T27	1		T34	2		T76	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T22	11		T234	1		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T26	9		T55	10		T36	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	10		T234	1		T35	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T3	5		T25	7		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T54	5		T130	1		T123	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T78	17		T239	11		T150	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	14		T125	10		T283	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T22	9		T41	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	1		T25	1		T54	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	401	1			T3	5		T26	12		T122	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T9	1		T11	5		T55	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T251	11		T161	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T132	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T359	2		T343	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T236	3		T210	19		T246	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T38	5		T259	13		T192	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1103	1			T5	4		T12	8		T25	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T1	8		T129	10		T253	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T247	7		T154	3		T126	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T216	10		T123	4		T245	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T34	1		T143	18		T126	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T22	9		T154	6		T133	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T26	11		T55	7		T133	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	13		T35	1		T243	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T3	9		T34	1		T83	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T54	4		T123	7		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T344	12		T188	2		T313	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	7		T125	11		T264	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T22	8		T122	6		T83	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T54	13		T296	1		T287	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T3	9		T26	12		T122	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T55	11		T216	10		T237	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4