Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22624

1

T1

17

T2

23

T3

162

auto[ADC_CTRL_FILTER_COND_OUT]

3796

1

T3

14

T9

1

T11

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20744

1

T1

17

T3

162

T6

20

auto[1]

5676

1

T2

23

T3

14

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	271	1			T41	1		T34	4		T122	22
values[0]	44	1			T143	10		T155	1		T213	13
values[1]	590	1			T11	5		T22	20		T234	1
values[2]	754	1			T3	14		T27	1		T128	13
values[3]	713	1			T84	5		T125	21		T132	28
values[4]	631	1			T3	14		T9	1		T233	1
values[5]	2669	1			T1	17		T2	23		T4	3
values[6]	585	1			T26	20		T42	7		T122	7
values[7]	734	1			T22	16		T25	7		T122	1
values[8]	674	1			T22	1		T34	3		T122	26
values[9]	892	1			T3	14		T7	23		T9	1
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	685	1			T11	5		T234	1		T92	3
values[1]	633	1			T3	14		T22	20		T27	1
values[2]	722	1			T9	1		T92	17		T125	21
values[3]	2721	1			T2	23		T3	14		T4	3
values[4]	576	1			T1	17		T7	21		T25	21
values[5]	650	1			T122	1		T13	3		T234	1
values[6]	664	1			T22	16		T25	7		T55	17
values[7]	654	1			T22	1		T34	3		T122	26
values[8]	955	1			T3	14		T7	23		T9	1
values[9]	106	1			T157	5		T301	1		T310	1
minimum	18054	1			T3	134		T6	20		T9	203

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T234	1		T92	1		T78	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	2		T130	1		T264	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T22	10		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T83	11		T84	2		T123	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	1		T132	17		T40	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T92	1		T125	12		T38	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1499	1			T2	3		T4	3		T5	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	10		T233	1		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	9		T7	8		T26	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T25	11		T26	13		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T234	1		T247	8		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T122	1		T13	2		T54	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T25	2		T291	1		T259	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T22	9		T55	8		T216	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T22	1		T34	2		T122	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T83	9		T210	14		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	10		T7	14		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T9	1		T25	1		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T310	1		T142	14		T297	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T157	1		T301	1		T255	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17794	1			T3	134		T6	20		T9	201
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T76	1		T37	5		T144	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T92	2		T78	16		T237	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	3		T135	12		T136	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	13		T22	10		T150	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T83	8		T84	5		T123	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T132	11		T40	1		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T92	16		T125	9		T38	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	910	1			T2	20		T244	10		T252	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	4		T129	10		T133	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T1	8		T7	13		T26	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T25	10		T26	11		T42	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T247	9		T268	13		T141	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	1		T54	2		T35	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T25	5		T259	7		T235	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T22	7		T55	9		T251	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T34	1		T122	14		T36	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T83	12		T157	7		T45	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	4		T7	9		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T122	12		T55	9		T84	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T297	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T157	4		T255	12		T311	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	2		T11	2		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T76	12		T37	2		T227	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T34	3		T54	5		T360	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T41	1		T122	10		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T143	10		T213	1		T312	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T155	1		T314	1		T217	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T22	10		T234	1		T92	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	2		T76	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	1		T27	1		T128	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T83	11		T84	1		T123	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T132	17		T126	2		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T84	1		T125	12		T38	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	1		T283	1		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	10		T233	1		T92	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1467	1			T1	9		T2	3		T4	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T25	11		T26	13		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T26	12		T234	1		T247	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T42	1		T122	7		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T25	2		T291	1		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T22	9		T122	1		T55	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T22	1		T34	2		T122	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T216	11		T83	9		T210	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	10		T7	14		T36	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T9	1		T25	1		T55	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T34	1		T54	4		T360	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T122	12		T129	1		T243	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T213	12		T315	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T217	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T22	10		T92	2		T78	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	3		T76	12		T37	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	13		T237	9		T239	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T83	8		T84	1		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T132	11		T134	9		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T84	4		T125	9		T38	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T40	1		T150	7		T272	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	4		T92	16		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	884	1			T1	8		T2	20		T7	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T25	10		T26	11		T92	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T26	8		T247	9		T37	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T42	6		T13	1		T54	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T25	5		T235	1		T276	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T22	7		T55	9		T251	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T34	1		T122	14		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T83	12		T157	7		T45	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	4		T7	9		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T55	9		T84	2		T239	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T234	1		T92	3		T78	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	5		T130	1		T264	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	14		T22	11		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T83	9		T84	7		T123	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	1		T132	12		T40	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T92	17		T125	10		T38	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T2	23		T4	3		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	5		T233	1		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T1	9		T7	14		T26	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T25	11		T26	12		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T234	1		T247	10		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T122	1		T13	3		T54	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T25	7		T291	1		T259	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T22	8		T55	10		T216	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T22	1		T34	2		T122	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T83	13		T210	1		T157	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	5		T7	10		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T9	1		T25	1		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T310	1		T142	1		T297	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T157	5		T301	1		T255	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17901	1			T3	134		T6	20		T9	203
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T76	13		T37	5		T144	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T237	9		T154	6		T14	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T264	9		T133	9		T143	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T22	9		T128	12		T144	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T83	10		T123	7		T236	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T132	16		T40	1		T126	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T125	11		T38	5		T126	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T5	4		T12	8		T124	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	9		T129	10		T133	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	8		T7	7		T26	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	10		T26	12		T122	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T247	7		T210	6		T268	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T54	13		T35	1		T236	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T259	8		T281	11		T276	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T22	8		T55	7		T216	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T34	1		T122	11		T258	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T83	8		T210	13		T45	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	9		T7	13		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T122	9		T55	7		T84	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T142	13		T297	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T255	14		T311	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T143	9		T192	17		T19	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T37	2		T144	11		T227	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T34	3		T54	5		T360	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T41	1		T122	13		T129	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T143	1		T213	13		T312	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T155	1		T314	1		T217	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T22	11		T234	1		T92	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	5		T76	13		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	14		T27	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T83	9		T84	2		T123	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T132	12		T126	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T84	5		T125	10		T38	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T9	1		T283	1		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	5		T233	1		T92	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T1	9		T2	23		T4	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T25	11		T26	12		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T26	9		T234	1		T247	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T42	7		T122	1		T13	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T25	7		T291	1		T235	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T22	8		T122	1		T55	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T22	1		T34	2		T122	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T216	1		T83	13		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	5		T7	10		T36	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T9	1		T25	1		T55	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T34	1		T54	4		T360	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T122	9		T243	13		T309	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T143	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T217	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T22	9		T154	6		T192	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T37	2		T133	9		T143	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T128	12		T237	9		T144	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T83	10		T123	7		T236	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T132	16		T126	1		T136	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T125	11		T38	5		T154	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T40	1		T258	11		T246	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	9		T129	10		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1147	1			T1	8		T5	4		T7	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T25	10		T26	12		T133	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T26	11		T247	7		T37	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T122	6		T54	13		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T281	11		T276	7		T268	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T22	8		T55	7		T216	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T34	1		T122	11		T259	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T216	10		T83	8		T210	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	9		T7	13		T123	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T55	7		T84	10		T251	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4