Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	5		T13	3		T55	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T25	11		T27	1		T122	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T233	1		T127	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	9		T37	14		T237	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T35	9		T123	8		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	14		T25	7		T26	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T122	1		T92	17		T129	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T22	1		T54	5		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	10		T216	2		T84	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	5		T34	2		T122	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	1		T27	1		T84	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T26	9		T83	13		T239	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1153	1			T2	23		T4	3		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	11		T34	3		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	1		T234	1		T84	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T22	8		T76	13		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T3	5		T128	1		T55	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T25	1		T234	1		T55	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T7	14		T42	7		T133	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T38	13		T268	14		T269	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17864	1			T3	134		T6	20		T9	203
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	9		T55	11		T123	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T25	10		T122	9		T278	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T270	10		T263	11		T14	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	8		T37	11		T237	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T35	1		T123	7		T143	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T26	12		T247	7		T54	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T122	6		T129	10		T144	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T54	4		T83	10		T133	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	13		T216	20		T264	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T34	1		T122	11		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T259	17		T135	9		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T26	11		T83	8		T273	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1118	1			T5	4		T12	8		T124	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T22	9		T34	1		T259	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T84	10		T243	13		T136	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T22	8		T154	11		T133	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	9		T128	12		T55	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T55	7		T40	1		T144	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T7	7		T133	8		T279	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T38	5		T268	9		T280	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T265	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T142	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T266	10		T267	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	5		T55	10		T36	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T27	1		T122	13		T129	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	3		T233	1		T123	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T25	11		T122	1		T37	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T35	9		T92	17		T123	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	9		T3	14		T26	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T122	1		T129	11		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T22	1		T25	7		T54	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	10		T9	1		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	5		T54	5		T36	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T216	1		T84	7		T135	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T34	2		T122	15		T92	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T27	1		T41	1		T92	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T26	9		T34	3		T273	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T84	3		T274	1		T275	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T22	19		T153	1		T76	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1428	1			T2	23		T3	5		T4	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T25	1		T234	1		T55	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T265	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T142	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T3	9		T55	11		T271	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T122	9		T278	13		T276	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T123	4		T134	14		T270	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T25	10		T37	11		T132	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T35	1		T123	7		T143	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	8		T26	12		T247	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T122	6		T129	10		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T54	13		T251	16		T258	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	13		T216	10		T264	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T54	4		T83	10		T133	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T216	10		T135	9		T281	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T34	1		T122	11		T83	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T236	15		T126	9		T259	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T26	11		T34	1		T273	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T84	10		T243	13		T246	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	17		T143	18		T210	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T3	9		T5	4		T7	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T55	7		T38	5		T40	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4