Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23175

1

T1

17

T2

23

T3

162

auto[ADC_CTRL_FILTER_COND_OUT]

3245

1

T3

14

T22

36

T26

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20936

1

T1

17

T3

134

T6

20

auto[1]

5484

1

T2

23

T3

42

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T282	8		-	-		-	-
values[0]	159	1			T34	4		T122	26		T123	10
values[1]	753	1			T3	28		T7	21		T26	24
values[2]	688	1			T27	1		T122	22		T247	17
values[3]	739	1			T25	1		T41	1		T42	7
values[4]	2499	1			T2	23		T4	3		T5	5
values[5]	490	1			T1	17		T122	1		T234	1
values[6]	669	1			T3	14		T11	5		T22	20
values[7]	784	1			T25	7		T34	3		T54	16
values[8]	537	1			T7	23		T13	3		T55	21
values[9]	1231	1			T9	1		T22	17		T25	21
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1093	1			T3	28		T7	21		T26	24
values[1]	671	1			T25	1		T27	1		T41	1
values[2]	671	1			T55	17		T92	17		T80	1
values[3]	2497	1			T1	17		T2	23		T4	3
values[4]	614	1			T11	5		T122	7		T234	1
values[5]	671	1			T3	14		T22	20		T25	7
values[6]	739	1			T34	3		T13	3		T54	16
values[7]	500	1			T7	23		T26	20		T55	21
values[8]	919	1			T9	1		T22	17		T25	21
values[9]	182	1			T55	17		T274	1		T283	1
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T3	20		T7	8		T27	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T26	13		T34	3		T122	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T25	1		T27	1		T54	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T41	1		T42	1		T247	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T92	1		T83	11		T84	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T55	8		T80	1		T125	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1452	1			T1	9		T2	3		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T122	1		T163	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	2		T216	11		T236	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T122	7		T234	1		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T25	2		T150	1		T284	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T3	1		T22	10		T216	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T34	2		T13	2		T37	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T54	14		T92	1		T237	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	14		T26	12		T55	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T80	1		T283	1		T154	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T9	1		T22	1		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T22	9		T233	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T143	10		T137	1		T230	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T55	8		T274	1		T283	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T3	8		T7	13		T122	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T26	11		T34	1		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T54	4		T253	16		T135	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T42	6		T247	9		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T92	16		T83	8		T84	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T55	9		T125	9		T157	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	864	1			T1	8		T2	20		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T192	14		T285	2		T286	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	3		T236	3		T238	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T40	1		T154	8		T148	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T25	5		T150	10		T251	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	13		T22	10		T78	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T34	1		T13	1		T37	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T54	2		T92	2		T237	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T7	9		T26	8		T55	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T154	12		T213	7		T258	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T25	10		T35	3		T38	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T22	7		T37	6		T157	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T137	3		T287	2		T288	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T55	9		T164	14		T289	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T282	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T122	12		T123	5		T189	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T34	3		T135	17		T290	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	20		T7	8		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T26	13		T234	1		T126	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T27	1		T54	5		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T122	10		T247	8		T36	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T25	1		T92	1		T83	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T41	1		T42	1		T55	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1439	1			T2	3		T4	3		T5	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T122	7		T80	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	9		T84	1		T236	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T122	1		T234	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	2		T216	11		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	1		T22	10		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T25	2		T34	2		T291	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T54	14		T216	11		T92	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	14		T13	2		T55	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T80	1		T283	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T9	1		T22	1		T25	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T22	9		T233	1		T55	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T282	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T122	14		T123	5		T189	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T34	1		T135	12		T292	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	8		T7	13		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T26	11		T246	4		T245	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T54	4		T36	1		T135	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T122	12		T247	9		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T92	16		T83	8		T84	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T42	6		T55	9		T125	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	883	1			T2	20		T244	10		T252	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T192	14		T285	2		T188	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T1	8		T84	1		T236	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T40	1		T137	10		T286	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	3		T239	14		T293	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	13		T22	10		T78	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T25	5		T34	1		T150	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T54	2		T92	2		T83	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T7	9		T13	1		T55	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T213	7		T157	4		T258	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T25	10		T26	8		T35	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T22	7		T55	9		T37	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T3	10		T7	14		T27	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T26	12		T34	3		T122	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T25	1		T27	1		T54	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	1		T42	7		T247	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T92	17		T83	9		T84	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T55	10		T80	1		T125	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T1	9		T2	23		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T122	1		T163	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	5		T216	1		T236	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T122	1		T234	1		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T25	7		T150	11		T284	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	14		T22	11		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T34	2		T13	3		T37	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T54	3		T92	3		T237	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	10		T26	9		T55	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T80	1		T283	1		T154	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T9	1		T22	1		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T22	8		T233	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T143	1		T137	4		T230	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T55	10		T274	1		T283	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T3	18		T7	7		T122	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T26	12		T34	1		T122	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T54	4		T126	1		T253	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T247	7		T251	11		T259	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T83	10		T123	7		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T55	7		T125	11		T255	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1127	1			T1	8		T5	4		T12	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T192	11		T294	11		T285	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T216	10		T236	3		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T122	6		T40	1		T154	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T251	16		T138	1		T295	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T22	9		T216	10		T83	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T34	1		T37	2		T210	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T54	13		T237	9		T271	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	13		T26	11		T55	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T154	11		T258	11		T296	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T25	10		T35	1		T38	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T22	8		T37	9		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T143	9		T287	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T55	7		T273	12		T144	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T282	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T122	15		T123	6		T189	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T34	3		T135	13		T290	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	10		T7	14		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T26	12		T234	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T27	1		T54	5		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T122	13		T247	10		T36	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T25	1		T92	17		T83	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T41	1		T42	7		T55	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T2	23		T4	3		T5	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T122	1		T80	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	9		T84	2		T236	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T122	1		T234	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	5		T216	1		T239	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	14		T22	11		T78	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T25	7		T34	2		T291	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T54	3		T216	1		T92	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	10		T13	3		T55	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T80	1		T283	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T9	1		T22	1		T25	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T22	8		T233	1		T55	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T122	11		T123	4		T297	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T34	1		T135	16		T290	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	18		T7	7		T154	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T26	12		T126	9		T246	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T54	4		T135	9		T278	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T122	9		T247	7		T84	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T83	10		T123	7		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T55	7		T125	11		T259	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T5	4		T12	8		T124	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T122	6		T192	11		T255	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	8		T236	3		T45	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T40	1		T210	5		T298	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T216	10		T138	1		T295	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T22	9		T237	9		T236	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T34	1		T251	16		T259	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T54	13		T216	10		T83	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	13		T55	11		T37	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T258	11		T296	1		T299	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T25	10		T26	11		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T22	8		T55	7		T37	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4