Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23332

1

T2

23

T3

148

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3088

1

T1

17

T3

28

T7

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21053

1

T1

17

T3

162

T6

20

auto[1]

5367

1

T2

23

T3

14

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	61	1			T7	21		T19	11		T300	11
values[0]	110	1			T54	16		T150	8		T243	27
values[1]	670	1			T13	3		T128	13		T216	11
values[2]	587	1			T3	14		T22	20		T34	3
values[3]	590	1			T26	20		T234	1		T233	1
values[4]	690	1			T22	1		T26	24		T55	21
values[5]	561	1			T3	14		T9	1		T22	16
values[6]	706	1			T1	17		T3	14		T25	1
values[7]	536	1			T11	5		T241	1		T130	1
values[8]	2736	1			T2	23		T4	3		T5	5
values[9]	1310	1			T9	1		T25	28		T27	1
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	835	1			T13	3		T128	13		T54	16
values[1]	614	1			T3	14		T22	20		T34	3
values[2]	780	1			T26	20		T216	11		T92	17
values[3]	590	1			T9	1		T22	16		T26	24
values[4]	648	1			T1	17		T3	28		T22	1
values[5]	561	1			T11	5		T25	1		T122	22
values[6]	2541	1			T2	23		T4	3		T5	5
values[7]	810	1			T7	23		T92	3		T76	13
values[8]	978	1			T7	21		T9	1		T25	7
values[9]	196	1			T25	21		T54	9		T239	15
minimum	17867	1			T3	134		T6	20		T9	203

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	2		T54	14		T216	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T128	13		T80	1		T84	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T34	2		T233	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	1		T22	10		T234	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T216	11		T237	10		T144	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T26	12		T92	1		T37	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	1		T22	9		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T36	2		T84	11		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	10		T22	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	9		T3	10		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T122	10		T241	1		T123	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	2		T25	1		T83	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T2	3		T4	3		T5	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T123	5		T37	12		T291	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	14		T39	2		T144	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T92	1		T76	1		T236	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T9	1		T122	1		T247	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T7	8		T25	2		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T54	5		T301	1		T227	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T25	11		T239	1		T283	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17755	1			T3	134		T6	20		T9	201
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	1		T54	2		T35	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T84	1		T132	11		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	1		T78	16		T83	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T3	13		T22	10		T55	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T237	9		T259	2		T157	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T26	8		T92	16		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T22	7		T26	11		T55	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T36	1		T84	2		T239	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	4		T40	1		T253	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	8		T3	4		T42	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T122	12		T123	7		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	3		T83	12		T154	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	877	1			T2	20		T244	10		T252	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T123	5		T37	6		T259	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	9		T251	10		T213	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T92	2		T76	12		T236	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T247	9		T55	9		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T7	13		T25	5		T84	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T54	4		T227	5		T179	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T25	10		T239	14		T277	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	2		T11	2		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T260	18		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T7	8		T19	6		T300	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T54	14		T243	14		T302	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T150	1		T303	1		T304	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	2		T216	11		T35	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T128	13		T80	1		T84	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T34	2		T153	1		T78	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	1		T22	10		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T233	1		T237	10		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T26	12		T234	1		T55	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T22	1		T26	13		T55	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T36	2		T92	1		T239	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	1		T22	9		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	10		T122	7		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	10		T27	1		T122	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	9		T25	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T241	1		T130	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	2		T123	5		T37	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1513	1			T2	3		T4	3		T5	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T76	1		T127	1		T259	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T9	1		T122	1		T247	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	410	1			T25	13		T27	1		T92	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T7	13		T19	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T54	2		T243	13		T302	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T150	7		T304	9		T305	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	1		T35	3		T129	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T84	1		T132	11		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T34	1		T78	16		T83	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T3	13		T22	10		T134	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T237	9		T259	2		T157	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T26	8		T55	9		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T26	11		T55	9		T251	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T36	1		T92	16		T239	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T22	7		T40	1		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T3	4		T84	2		T270	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	4		T122	12		T123	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	8		T42	6		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T40	2		T258	10		T14	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T11	3		T123	5		T37	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T2	20		T7	9		T244	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T76	12		T259	7		T246	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T247	9		T54	4		T55	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T25	15		T92	2		T84	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T13	3		T54	3		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T128	1		T80	1		T84	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T34	2		T233	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	14		T22	11		T234	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T216	1		T237	10		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T26	9		T92	17		T37	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	1		T22	8		T26	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T36	3		T84	3		T239	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	5		T22	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	9		T3	5		T42	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T122	13		T241	1		T123	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	5		T25	1		T83	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T2	23		T4	3		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T123	6		T37	9		T291	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	10		T39	2		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T92	3		T76	13		T236	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	1		T122	1		T247	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T7	14		T25	7		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T54	5		T301	1		T227	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T25	11		T239	15		T283	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17867	1			T3	134		T6	20		T9	203
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T54	13		T216	10		T35	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T128	12		T132	16		T273	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	1		T83	10		T129	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T22	9		T55	7		T210	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T216	10		T237	9		T144	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T26	11		T37	2		T136	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T22	8		T26	12		T55	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T84	10		T45	3		T271	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	9		T236	15		T253	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	8		T3	9		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T122	9		T123	7		T154	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T83	8		T154	6		T306	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1159	1			T5	4		T12	8		T124	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T123	4		T37	9		T259	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	13		T144	8		T126	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T236	3		T259	8		T246	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T247	7		T55	7		T133	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	7		T40	1		T126	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T54	4		T227	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T25	10		T144	4		T277	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T260	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T7	14		T19	8		T300	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T54	3		T243	14		T302	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T150	8		T303	1		T304	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	3		T216	1		T35	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T128	1		T80	1		T84	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T34	2		T153	1		T78	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	14		T22	11		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T233	1		T237	10		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T26	9		T234	1		T55	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T22	1		T26	12		T55	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T36	3		T92	17		T239	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	1		T22	8		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	5		T122	1		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	5		T27	1		T122	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	9		T25	1		T42	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T241	1		T130	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	5		T123	6		T37	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T2	23		T4	3		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T76	13		T127	1		T259	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T9	1		T122	1		T247	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	440	1			T25	18		T27	1		T92	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T260	17		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T7	7		T19	3		T300	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T54	13		T243	13		T307	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T304	7		T308	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T216	10		T35	1		T154	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T128	12		T132	16		T273	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T34	1		T83	10		T129	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T22	9		T210	5		T281	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T237	9		T259	13		T258	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T26	11		T55	7		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T26	12		T55	11		T216	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T45	3		T285	8		T183	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T22	8		T154	3		T135	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	9		T122	6		T84	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	9		T122	9		T123	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	8		T34	1		T122	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T258	11		T281	14		T14	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T123	4		T37	9		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T5	4		T7	13		T12	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T259	8		T246	11		T296	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T247	7		T54	4		T55	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T25	10		T236	3		T40	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4