Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23168

1

T1

17

T2

23

T3

162

auto[ADC_CTRL_FILTER_COND_OUT]

3252

1

T3

14

T22

36

T26

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20925

1

T1

17

T3

134

T6

20

auto[1]

5495

1

T2

23

T3

42

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	165	1			T22	16		T233	1		T153	1
values[0]	52	1			T34	4		T135	29		T290	9
values[1]	865	1			T3	28		T7	21		T26	24
values[2]	653	1			T27	1		T122	22		T247	17
values[3]	757	1			T25	1		T41	1		T42	7
values[4]	2531	1			T2	23		T4	3		T5	5
values[5]	456	1			T1	17		T122	1		T234	1
values[6]	676	1			T3	14		T11	5		T22	20
values[7]	842	1			T25	7		T34	3		T13	3
values[8]	446	1			T7	23		T55	21		T92	3
values[9]	1114	1			T9	1		T22	1		T25	21
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	902	1			T3	28		T26	24		T27	1
values[1]	602	1			T25	1		T27	1		T41	1
values[2]	713	1			T55	17		T92	17		T83	19
values[3]	2560	1			T1	17		T2	23		T4	3
values[4]	535	1			T234	1		T216	11		T236	7
values[5]	720	1			T3	14		T11	5		T22	20
values[6]	689	1			T34	3		T13	3		T54	16
values[7]	525	1			T7	23		T26	20		T55	21
values[8]	988	1			T9	1		T22	17		T25	21
values[9]	93	1			T55	17		T283	1		T273	13
minimum	18093	1			T3	134		T6	20		T7	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	20		T27	1		T122	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T26	13		T122	10		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T25	1		T27	1		T54	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T41	1		T42	1		T247	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T92	1		T83	11		T84	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T55	8		T125	12		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1478	1			T1	9		T2	3		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T122	8		T80	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T216	11		T236	4		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T234	1		T39	2		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	2		T25	2		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T3	1		T22	10		T216	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T34	2		T13	2		T37	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T54	14		T92	1		T318	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	14		T26	12		T55	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T80	1		T283	1		T154	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T9	1		T22	1		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T22	9		T233	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T275	1		T143	10		T319	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T55	8		T283	1		T273	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17817	1			T3	134		T6	20		T7	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T34	3		T135	17		T310	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	8		T122	14		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T26	11		T122	12		T132	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T54	4		T253	16		T135	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T42	6		T247	9		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T92	16		T83	8		T84	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T55	9		T125	9		T157	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	871	1			T1	8		T2	20		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T192	14		T285	2		T188	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T236	3		T239	14		T272	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T40	1		T154	8		T148	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	3		T25	5		T150	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	13		T22	10		T78	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T34	1		T13	1		T37	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T54	2		T92	2		T318	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T7	9		T26	8		T55	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T154	12		T213	7		T258	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T25	10		T35	3		T38	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T22	7		T37	6		T157	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T55	9		T289	11		T320	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	13		T9	2		T11	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T34	1		T135	12		T227	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T143	29		T158	10		T282	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T22	9		T233	1		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T34	3		T135	17		T290	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T3	20		T7	8		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T26	13		T234	1		T126	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T27	1		T54	5		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T122	10		T247	8		T36	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T25	1		T92	1		T83	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T41	1		T42	1		T55	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1448	1			T2	3		T4	3		T5	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T122	7		T80	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	9		T84	1		T236	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T122	1		T234	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	2		T216	11		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	1		T22	10		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T25	2		T34	2		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T54	14		T216	11		T92	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	14		T55	12		T92	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T80	1		T283	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T9	1		T22	1		T25	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T55	8		T274	1		T37	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T158	5		T282	7		T321	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T22	7		T15	4		T139	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T34	1		T135	12		T305	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	8		T7	13		T122	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T26	11		T246	4		T245	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T54	4		T36	1		T135	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T122	12		T247	9		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T92	16		T83	8		T84	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T42	6		T55	9		T125	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	873	1			T2	20		T244	10		T252	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T192	14		T285	2		T188	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	8		T84	1		T236	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T40	1		T137	10		T286	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	3		T239	14		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	13		T22	10		T78	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T25	5		T34	1		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T54	2		T92	2		T83	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T7	9		T55	9		T92	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T213	7		T258	10		T296	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T25	10		T26	8		T35	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T55	9		T37	6		T154	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T3	10		T27	1		T122	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T26	12		T122	13		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T25	1		T27	1		T54	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T41	1		T42	7		T247	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T92	17		T83	9		T84	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T55	10		T125	10		T157	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T1	9		T2	23		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T122	2		T80	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T216	1		T236	4		T239	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T234	1		T39	2		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	5		T25	7		T150	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	14		T22	11		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	2		T13	3		T37	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T54	3		T92	3		T318	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	10		T26	9		T55	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T80	1		T283	1		T154	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T9	1		T22	1		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T22	8		T233	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T275	1		T143	1		T319	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T55	10		T283	1		T273	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17933	1			T3	134		T6	20		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T34	3		T135	13		T310	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	18		T122	11		T123	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T26	12		T122	9		T132	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T54	4		T126	1		T253	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T247	7		T84	10		T251	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T83	10		T123	7		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T55	7		T125	11		T255	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1150	1			T1	8		T5	4		T12	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T122	6		T192	11		T294	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T216	10		T236	3		T285	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T40	1		T154	6		T210	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T251	16		T138	1		T295	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T22	9		T216	10		T83	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	1		T37	2		T259	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T54	13		T271	9		T277	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	13		T26	11		T55	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T154	11		T258	11		T296	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T25	10		T35	1		T38	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T22	8		T37	9		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T143	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T55	7		T273	12		T144	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T7	7		T136	8		T286	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T34	1		T135	16		T227	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T143	2		T158	6		T282	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T22	8		T233	1		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T34	3		T135	13		T290	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T3	10		T7	14		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T26	12		T234	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T27	1		T54	5		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T122	13		T247	10		T36	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T25	1		T92	17		T83	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T41	1		T42	7		T55	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T2	23		T4	3		T5	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T122	1		T80	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	9		T84	2		T236	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T122	1		T234	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	5		T216	1		T239	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	14		T22	11		T78	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T25	7		T34	2		T13	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T54	3		T216	1		T92	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T7	10		T55	10		T92	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T80	1		T283	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T9	1		T22	1		T25	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T55	10		T274	1		T37	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T143	27		T158	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T22	8		T15	2		T204	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T34	1		T135	16		T290	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	18		T7	7		T122	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T26	12		T126	9		T246	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T54	4		T135	9		T278	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T122	9		T247	7		T84	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T83	10		T123	7		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T55	7		T125	11		T259	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1128	1			T5	4		T12	8		T124	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T122	6		T192	11		T255	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	8		T236	3		T45	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T40	1		T210	5		T298	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T216	10		T138	1		T295	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T22	9		T237	9		T236	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T34	1		T37	2		T251	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T54	13		T216	10		T83	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	13		T55	11		T264	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T258	11		T296	1		T299	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T25	10		T26	11		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T55	7		T37	9		T273	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4