Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23184

1

T1

17

T2

23

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3236

1

T3

28

T9

1

T22

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20810

1

T1

17

T3

142

T6

20

auto[1]

5610

1

T2

23

T3

34

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	472	1			T3	6		T9	1		T11	8
values[0]	50	1			T42	7		T55	21		T284	1
values[1]	709	1			T22	20		T25	7		T26	24
values[2]	2653	1			T2	23		T3	14		T4	3
values[3]	632	1			T1	17		T22	1		T41	1
values[4]	558	1			T25	1		T247	17		T54	9
values[5]	665	1			T7	21		T27	1		T55	17
values[6]	771	1			T122	7		T92	17		T78	17
values[7]	680	1			T11	5		T34	3		T128	13
values[8]	764	1			T3	28		T7	23		T9	1
values[9]	1015	1			T25	21		T26	20		T35	10
minimum	17451	1			T3	128		T6	20		T9	202

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	874	1			T3	14		T9	1		T22	20
values[1]	2718	1			T2	23		T4	3		T5	5
values[2]	654	1			T1	17		T22	1		T25	1
values[3]	540	1			T7	21		T54	9		T55	17
values[4]	574	1			T27	1		T216	11		T92	3
values[5]	672	1			T122	7		T234	1		T92	17
values[6]	885	1			T9	1		T11	5		T34	3
values[7]	644	1			T3	28		T7	23		T22	16
values[8]	731	1			T35	10		T80	1		T84	2
values[9]	232	1			T26	20		T283	1		T271	16
minimum	17896	1			T3	134		T6	20		T9	203

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	1		T22	10		T25	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T9	1		T26	13		T36	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T2	3		T4	3		T5	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T233	1		T251	17		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	9		T22	1		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T25	1		T41	1		T247	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	8		T54	5		T132	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T55	8		T241	1		T84	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T27	1		T92	1		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T216	11		T125	1		T274	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T92	1		T76	1		T237	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T122	7		T234	1		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T9	1		T11	2		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T13	2		T128	13		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	14		T34	3		T122	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	20		T22	9		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T35	7		T80	1		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T84	1		T130	1		T125	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T271	8		T188	14		T279	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T26	12		T283	1		T230	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T3	134		T6	20		T9	201
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T313	6		T322	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	13		T22	10		T25	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T26	11		T36	1		T92	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T2	20		T244	10		T252	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T251	14		T213	7		T270	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	8		T123	7		T236	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T247	9		T40	2		T259	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T7	13		T54	4		T132	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T55	9		T84	2		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T92	2		T76	12		T78	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T245	3		T323	2		T160	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T92	16		T76	2		T237	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T239	14		T318	2		T258	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	3		T34	1		T54	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	1		T150	7		T251	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	9		T34	1		T122	26
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	8		T22	7		T25	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T35	3		T129	1		T148	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T84	1		T125	9		T253	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T271	8		T188	13		T279	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T26	8		T324	14		T325	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	2		T11	2		T42	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T313	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	454	1			T3	6		T9	1		T11	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T42	1		T55	12		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T284	1		T326	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T22	10		T25	2		T36	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T26	13		T36	2		T92	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T2	3		T3	1		T4	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	1		T233	1		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	9		T22	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T41	1		T40	2		T259	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T54	5		T123	8		T236	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T25	1		T247	8		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	8		T27	1		T92	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T55	8		T216	11		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T92	1		T78	1		T123	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T122	7		T283	1		T318	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	2		T34	2		T54	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T128	13		T234	1		T239	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	14		T9	1		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	20		T22	9		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T35	7		T153	1		T80	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T25	11		T26	12		T84	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17342	1			T3	128		T6	20		T9	200
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T188	13		T165	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T42	6		T55	9		T137	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T326	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T22	10		T25	5		T36	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T26	11		T36	1		T92	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T2	20		T3	13		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	1		T251	14		T213	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	8		T129	10		T150	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T40	2		T259	2		T293	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T54	4		T123	7		T236	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T247	9		T84	2		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	13		T92	2		T76	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T55	9		T245	3		T299	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T92	16		T78	16		T123	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T318	2		T150	7		T258	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	3		T34	1		T54	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T239	14		T251	10		T327	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	9		T34	1		T122	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	8		T22	7		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T35	3		T83	12		T84	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T25	10		T26	8		T84	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	14		T22	11		T25	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	1		T26	12		T36	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T2	23		T4	3		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T233	1		T251	15		T213	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	9		T22	1		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T25	1		T41	1		T247	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	14		T54	5		T132	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T55	10		T241	1		T84	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T27	1		T92	3		T76	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T216	1		T125	1		T274	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T92	17		T76	3		T237	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T122	1		T234	1		T239	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	1		T11	5		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	3		T128	1		T150	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	10		T34	3		T122	28
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	10		T22	8		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T35	9		T80	1		T129	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T84	2		T130	1		T125	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T271	9		T188	14		T279	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T26	9		T283	1		T230	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17875	1			T3	134		T6	20		T9	203
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T313	13		T322	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T22	9		T55	11		T38	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T26	12		T83	10		T37	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1120	1			T5	4		T12	8		T124	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T251	16		T270	10		T142	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	8		T123	7		T236	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T247	7		T259	9		T328	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	7		T54	4		T132	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T55	7		T84	10		T210	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T123	4		T133	9		T210	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T216	10		T273	12		T245	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T237	9		T143	9		T259	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T122	6		T258	11		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T34	1		T54	13		T37	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T128	12		T144	11		T251	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	13		T34	1		T122	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	18		T22	8		T25	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T35	1		T236	15		T144	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T125	11		T126	9		T253	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T271	7		T188	13		T279	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T26	11		T248	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T329	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T313	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	434	1			T3	6		T9	1		T11	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T42	7		T55	10		T137	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T284	1		T326	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T22	11		T25	7		T36	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T26	12		T36	3		T92	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T2	23		T3	14		T4	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	1		T233	1		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	9		T22	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T41	1		T40	4		T259	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T54	5		T123	8		T236	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T25	1		T247	10		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	14		T27	1		T92	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T55	10		T216	1		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T92	17		T78	17		T123	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T122	1		T283	1		T318	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	5		T34	2		T54	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T128	1		T234	1		T239	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	10		T9	1		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	10		T22	8		T13	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T35	9		T153	1		T80	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T25	11		T26	9		T84	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17451	1			T3	128		T6	20		T9	202
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T188	13		T159	6		T165	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T55	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T22	9		T38	5		T144	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T26	12		T83	10		T37	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T5	4		T12	8		T124	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	1		T251	16		T270	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	8		T129	10		T133	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T259	9		T328	9		T142	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T54	4		T123	7		T236	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T247	7		T84	10		T210	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	7		T132	16		T133	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T55	7		T216	10		T273	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T123	4		T37	2		T237	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T122	6		T258	11		T192	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T34	1		T54	13		T154	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T128	12		T251	11		T294	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	13		T34	1		T122	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	18		T22	8		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T35	1		T83	8		T133	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T25	10		T26	11		T125	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4