Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23080

1

T1

17

T2

23

T3

162

auto[ADC_CTRL_FILTER_COND_OUT]

3340

1

T3

14

T25

1

T34

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21025

1

T1

17

T3

162

T6

20

auto[1]

5395

1

T2

23

T3

14

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	230	1			T22	16		T259	16		T235	2
values[0]	20	1			T9	1		T143	19		-	-
values[1]	682	1			T22	21		T35	10		T92	3
values[2]	556	1			T11	5		T34	4		T55	21
values[3]	678	1			T42	7		T122	48		T76	13
values[4]	680	1			T3	42		T233	1		T83	40
values[5]	2696	1			T2	23		T4	3		T5	5
values[6]	620	1			T7	44		T26	20		T122	1
values[7]	663	1			T9	1		T27	1		T234	1
values[8]	728	1			T1	17		T25	28		T26	24
values[9]	1004	1			T34	3		T234	1		T54	25
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	622	1			T22	21		T92	3		T123	10
values[1]	544	1			T11	5		T42	7		T34	4
values[2]	704	1			T122	48		T123	15		T237	19
values[3]	2789	1			T2	23		T3	42		T4	3
values[4]	554	1			T7	21		T25	1		T27	1
values[5]	665	1			T7	23		T26	20		T92	3
values[6]	649	1			T9	1		T25	21		T27	1
values[7]	790	1			T1	17		T25	7		T26	24
values[8]	858	1			T22	16		T34	3		T54	25
values[9]	149	1			T39	2		T235	2		T192	32
minimum	18096	1			T3	134		T6	20		T9	204

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T22	11		T92	1		T210	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T123	5		T236	4		T40	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	2		T42	1		T55	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T34	3		T163	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T122	22		T123	8		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T237	10		T251	29		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T2	3		T3	11		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	10		T13	2		T36	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	8		T27	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T25	1		T122	7		T128	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	14		T26	12		T92	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T84	1		T129	11		T239	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T25	11		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T40	2		T154	12		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T1	9		T25	2		T26	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T216	11		T274	1		T264	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T22	9		T34	2		T54	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T54	14		T92	1		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T235	1		T136	5		T335	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T39	2		T192	18		T159	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17793	1			T3	134		T6	20		T9	202
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T283	1		T143	19		T279	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T22	10		T92	2		T243	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T123	5		T236	3		T40	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	3		T42	6		T55	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T34	1		T14	4		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T122	26		T123	7		T238	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T237	9		T251	24		T173	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	894	1			T2	20		T3	17		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	4		T13	1		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T7	13		T133	4		T157	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T154	8		T150	10		T259	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	9		T26	8		T92	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T84	1		T129	10		T239	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T25	10		T76	2		T129	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	1		T154	12		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	8		T25	5		T26	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T270	9		T137	10		T293	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T22	7		T34	1		T54	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T54	2		T92	16		T78	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T235	1		T136	10		T335	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T192	14		T248	11		T249	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	2		T11	2		T35	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T279	12		T311	17		T17	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T22	9		T259	9		T235	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T192	18		T245	5		T230	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T9	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T143	19		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T22	11		T35	7		T92	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T123	5		T236	4		T283	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	2		T55	12		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T34	3		T40	4		T154	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T42	1		T122	22		T76	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T237	10		T163	1		T251	29
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	11		T233	1		T83	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	10		T83	11		T132	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1479	1			T2	3		T4	3		T5	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T25	1		T122	7		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	22		T26	12		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T84	1		T239	2		T240	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T27	1		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T129	11		T40	2		T154	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T1	9		T25	13		T26	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T216	11		T274	1		T264	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T34	2		T234	1		T54	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T54	14		T92	1		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T22	7		T259	7		T235	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T192	14		T245	2		T230	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T22	10		T35	3		T92	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T123	5		T236	3		T266	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	3		T55	9		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T34	1		T40	3		T154	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T42	6		T122	26		T76	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T237	9		T251	24		T14	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	17		T83	12		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	4		T83	8		T132	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	869	1			T2	20		T244	10		T252	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	1		T36	1		T154	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	22		T26	8		T92	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T84	1		T239	24		T268	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T76	2		T129	1		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T129	10		T40	1		T154	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	8		T25	15		T26	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T136	11		T137	10		T293	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T34	1		T54	4		T125	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T54	2		T92	16		T78	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T22	12		T92	3		T210	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T123	6		T236	4		T40	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	5		T42	7		T55	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T34	3		T163	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T122	28		T123	8		T238	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T237	10		T251	26		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T2	23		T3	19		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	5		T13	3		T36	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T7	14		T27	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T25	1		T122	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	10		T26	9		T92	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T84	2		T129	11		T239	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T9	1		T25	11		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T40	2		T154	13		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	9		T25	7		T26	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T216	1		T274	1		T264	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T22	8		T34	2		T54	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T54	3		T92	17		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T235	2		T136	11		T335	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T39	2		T192	15		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17942	1			T3	134		T6	20		T9	204
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T283	1		T143	1		T279	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T22	9		T210	13		T243	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T123	4		T236	3		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T55	11		T144	8		T45	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T34	1		T14	3		T16	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T122	20		T123	7		T134	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T237	9		T251	27		T173	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T3	9		T5	4		T12	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	9		T83	10		T132	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T7	7		T133	8		T246	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T122	6		T128	12		T236	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	13		T26	11		T143	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T129	10		T268	9		T142	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T25	10		T216	10		T37	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T40	1		T154	11		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	8		T26	12		T247	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T216	10		T264	9		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T22	8		T34	1		T54	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T54	13		T135	8		T245	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T136	4		T335	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T192	17		T159	16		T260	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T35	1		T84	10		T38	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T143	18		T279	12		T311	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T22	8		T259	8		T235	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T192	15		T245	3		T230	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T9	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T143	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T22	12		T35	9		T92	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T123	6		T236	4		T283	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	5		T55	10		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T34	3		T40	6		T154	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T42	7		T122	28		T76	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T237	10		T163	1		T251	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	19		T233	1		T83	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	5		T83	9		T132	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T2	23		T4	3		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T25	1		T122	1		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	24		T26	9		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T84	2		T239	26		T240	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	1		T27	1		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T129	11		T40	2		T154	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	9		T25	18		T26	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T216	1		T274	1		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T34	2		T234	1		T54	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T54	3		T92	17		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T22	8		T259	8		T250	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T192	17		T245	4		T230	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T143	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T22	9		T35	1		T84	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T123	4		T236	3		T143	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T55	11		T144	8		T243	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T34	1		T40	1		T154	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T122	20		T123	7		T192	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T237	9		T251	27		T14	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	9		T83	8		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	9		T83	10		T132	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T5	4		T12	8		T124	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T122	6		T128	12		T236	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	20		T26	11		T133	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T268	9		T142	13		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T37	9		T253	15		T263	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T129	10		T40	1		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	8		T25	10		T26	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T216	10		T264	9		T126	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T34	1		T54	4		T125	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T54	13		T133	9		T270	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4