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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.22


Total test records in report: 919
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T800 /workspace/coverage/default/49.adc_ctrl_smoke.169450208 Jun 28 07:14:17 PM PDT 24 Jun 28 07:14:36 PM PDT 24 6026865983 ps
T801 /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.376667848 Jun 28 07:01:25 PM PDT 24 Jun 28 07:04:38 PM PDT 24 321967188102 ps
T802 /workspace/coverage/default/36.adc_ctrl_fsm_reset.1444686572 Jun 28 07:10:33 PM PDT 24 Jun 28 07:15:49 PM PDT 24 77105530129 ps
T803 /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1844573484 Jun 28 07:13:28 PM PDT 24 Jun 28 07:25:38 PM PDT 24 325187882532 ps
T59 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.422487752 Jun 28 06:58:30 PM PDT 24 Jun 28 06:58:33 PM PDT 24 446253388 ps
T804 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.4269643499 Jun 28 06:59:01 PM PDT 24 Jun 28 06:59:05 PM PDT 24 481045732 ps
T60 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3212576429 Jun 28 06:57:46 PM PDT 24 Jun 28 06:57:51 PM PDT 24 471651242 ps
T85 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3974964073 Jun 28 06:58:18 PM PDT 24 Jun 28 06:58:24 PM PDT 24 553668849 ps
T56 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.569533284 Jun 28 06:58:17 PM PDT 24 Jun 28 06:58:33 PM PDT 24 4397964247 ps
T65 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.156936310 Jun 28 06:58:16 PM PDT 24 Jun 28 06:58:21 PM PDT 24 427466117 ps
T50 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2110212112 Jun 28 06:58:59 PM PDT 24 Jun 28 06:59:08 PM PDT 24 4691384915 ps
T66 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1056486871 Jun 28 06:58:50 PM PDT 24 Jun 28 06:58:55 PM PDT 24 463217341 ps
T53 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1240938548 Jun 28 06:58:17 PM PDT 24 Jun 28 06:58:28 PM PDT 24 2619438533 ps
T805 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.548927949 Jun 28 06:59:20 PM PDT 24 Jun 28 06:59:23 PM PDT 24 408735147 ps
T806 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1022944757 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:51 PM PDT 24 397225417 ps
T118 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.885071423 Jun 28 06:58:02 PM PDT 24 Jun 28 06:58:06 PM PDT 24 678723786 ps
T57 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3539378829 Jun 28 06:59:10 PM PDT 24 Jun 28 06:59:33 PM PDT 24 8413291688 ps
T86 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2940698898 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:50 PM PDT 24 523322093 ps
T119 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2590830677 Jun 28 06:57:31 PM PDT 24 Jun 28 06:57:34 PM PDT 24 1277706019 ps
T58 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1608334737 Jun 28 06:57:50 PM PDT 24 Jun 28 06:58:03 PM PDT 24 4771850591 ps
T87 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2116832769 Jun 28 06:59:01 PM PDT 24 Jun 28 06:59:06 PM PDT 24 447410201 ps
T88 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2605984183 Jun 28 06:57:26 PM PDT 24 Jun 28 06:57:29 PM PDT 24 751674324 ps
T61 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3872802980 Jun 28 06:59:00 PM PDT 24 Jun 28 06:59:25 PM PDT 24 8538631238 ps
T51 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.719865217 Jun 28 06:57:54 PM PDT 24 Jun 28 06:58:07 PM PDT 24 2537294184 ps
T807 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4195049588 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:52 PM PDT 24 286810371 ps
T52 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.846482506 Jun 28 06:58:14 PM PDT 24 Jun 28 06:58:45 PM PDT 24 52272471270 ps
T97 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3222162503 Jun 28 06:57:26 PM PDT 24 Jun 28 06:57:30 PM PDT 24 648928068 ps
T808 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1307464669 Jun 28 06:59:31 PM PDT 24 Jun 28 06:59:33 PM PDT 24 525659173 ps
T67 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1030156890 Jun 28 06:58:59 PM PDT 24 Jun 28 06:59:06 PM PDT 24 347088349 ps
T809 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.932783550 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:55 PM PDT 24 4464291996 ps
T71 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2825526596 Jun 28 06:58:17 PM PDT 24 Jun 28 06:58:26 PM PDT 24 8136927455 ps
T810 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2167165895 Jun 28 06:59:11 PM PDT 24 Jun 28 06:59:16 PM PDT 24 460973188 ps
T120 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.400805710 Jun 28 06:59:14 PM PDT 24 Jun 28 06:59:19 PM PDT 24 511320046 ps
T811 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4017960216 Jun 28 06:58:59 PM PDT 24 Jun 28 06:59:04 PM PDT 24 542984048 ps
T812 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2795168023 Jun 28 06:58:19 PM PDT 24 Jun 28 06:58:23 PM PDT 24 532248915 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.161065638 Jun 28 06:57:29 PM PDT 24 Jun 28 06:57:36 PM PDT 24 1750537504 ps
T121 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3598332184 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:52 PM PDT 24 526238631 ps
T813 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2770290780 Jun 28 06:59:34 PM PDT 24 Jun 28 06:59:37 PM PDT 24 504615612 ps
T98 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2922781493 Jun 28 06:58:18 PM PDT 24 Jun 28 06:58:23 PM PDT 24 471996856 ps
T814 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1515977832 Jun 28 06:59:14 PM PDT 24 Jun 28 06:59:19 PM PDT 24 403747494 ps
T112 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3260480483 Jun 28 06:57:54 PM PDT 24 Jun 28 06:57:58 PM PDT 24 4962068614 ps
T815 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1337770402 Jun 28 06:57:26 PM PDT 24 Jun 28 06:57:31 PM PDT 24 4393603195 ps
T72 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3236513578 Jun 28 06:59:11 PM PDT 24 Jun 28 06:59:22 PM PDT 24 7867364168 ps
T113 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4027247365 Jun 28 06:59:00 PM PDT 24 Jun 28 06:59:05 PM PDT 24 498771026 ps
T816 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1228089069 Jun 28 06:59:01 PM PDT 24 Jun 28 06:59:08 PM PDT 24 466047372 ps
T99 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2263850301 Jun 28 06:58:15 PM PDT 24 Jun 28 06:58:18 PM PDT 24 524190265 ps
T817 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3558889431 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:53 PM PDT 24 568615394 ps
T818 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1011379632 Jun 28 06:58:59 PM PDT 24 Jun 28 06:59:03 PM PDT 24 595783556 ps
T361 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3340237246 Jun 28 06:58:59 PM PDT 24 Jun 28 06:59:09 PM PDT 24 8237444686 ps
T363 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.49573900 Jun 28 06:59:14 PM PDT 24 Jun 28 06:59:24 PM PDT 24 8466969351 ps
T819 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.756731004 Jun 28 06:58:59 PM PDT 24 Jun 28 06:59:03 PM PDT 24 355455823 ps
T820 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.10502999 Jun 28 06:58:31 PM PDT 24 Jun 28 06:58:37 PM PDT 24 4464179334 ps
T821 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4219780430 Jun 28 06:58:16 PM PDT 24 Jun 28 06:58:19 PM PDT 24 466497690 ps
T114 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.196934167 Jun 28 06:58:20 PM PDT 24 Jun 28 06:58:24 PM PDT 24 558188521 ps
T822 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.103551490 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:52 PM PDT 24 684841611 ps
T823 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2444350203 Jun 28 06:57:26 PM PDT 24 Jun 28 06:57:29 PM PDT 24 405390958 ps
T100 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2402785243 Jun 28 06:57:29 PM PDT 24 Jun 28 06:57:34 PM PDT 24 977214256 ps
T824 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1768227925 Jun 28 06:59:01 PM PDT 24 Jun 28 06:59:06 PM PDT 24 539350030 ps
T825 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1115884745 Jun 28 06:58:15 PM PDT 24 Jun 28 06:58:18 PM PDT 24 485077999 ps
T115 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2490282131 Jun 28 06:58:59 PM PDT 24 Jun 28 06:59:04 PM PDT 24 353167901 ps
T826 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1667826040 Jun 28 06:59:14 PM PDT 24 Jun 28 06:59:20 PM PDT 24 516090833 ps
T116 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3841283475 Jun 28 06:58:16 PM PDT 24 Jun 28 06:58:29 PM PDT 24 2800206297 ps
T827 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2349476738 Jun 28 06:59:19 PM PDT 24 Jun 28 06:59:22 PM PDT 24 518121250 ps
T828 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3227413997 Jun 28 06:59:14 PM PDT 24 Jun 28 06:59:20 PM PDT 24 464705503 ps
T829 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.187686920 Jun 28 06:59:01 PM PDT 24 Jun 28 06:59:06 PM PDT 24 586875161 ps
T101 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4214343888 Jun 28 06:57:27 PM PDT 24 Jun 28 06:57:35 PM PDT 24 1381494721 ps
T73 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1625683369 Jun 28 06:58:59 PM PDT 24 Jun 28 06:59:13 PM PDT 24 8542929296 ps
T117 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.417263861 Jun 28 06:58:03 PM PDT 24 Jun 28 06:58:10 PM PDT 24 2440710827 ps
T830 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2333599842 Jun 28 06:58:17 PM PDT 24 Jun 28 06:58:25 PM PDT 24 4703899155 ps
T364 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.4291657806 Jun 28 06:58:15 PM PDT 24 Jun 28 06:58:28 PM PDT 24 4155800158 ps
T831 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.926151923 Jun 28 06:58:31 PM PDT 24 Jun 28 06:58:34 PM PDT 24 519021077 ps
T832 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.726202630 Jun 28 06:59:10 PM PDT 24 Jun 28 06:59:14 PM PDT 24 326906717 ps
T833 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3565323140 Jun 28 06:58:17 PM PDT 24 Jun 28 06:58:23 PM PDT 24 439086968 ps
T834 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3229769895 Jun 28 06:59:22 PM PDT 24 Jun 28 06:59:25 PM PDT 24 558839641 ps
T835 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2285645547 Jun 28 06:58:47 PM PDT 24 Jun 28 06:58:53 PM PDT 24 4716806829 ps
T836 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1607969159 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:52 PM PDT 24 462393512 ps
T837 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2980326006 Jun 28 06:59:10 PM PDT 24 Jun 28 06:59:14 PM PDT 24 396565402 ps
T838 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1887163872 Jun 28 06:59:33 PM PDT 24 Jun 28 06:59:36 PM PDT 24 343023794 ps
T839 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.766454345 Jun 28 06:59:22 PM PDT 24 Jun 28 06:59:24 PM PDT 24 416919709 ps
T840 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2542347879 Jun 28 06:58:15 PM PDT 24 Jun 28 06:58:20 PM PDT 24 484367314 ps
T841 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1998111647 Jun 28 06:59:09 PM PDT 24 Jun 28 06:59:12 PM PDT 24 291412274 ps
T842 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1572159874 Jun 28 06:57:50 PM PDT 24 Jun 28 06:57:53 PM PDT 24 516512491 ps
T102 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3149888274 Jun 28 06:57:30 PM PDT 24 Jun 28 06:57:34 PM PDT 24 452232677 ps
T843 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.915332918 Jun 28 06:57:46 PM PDT 24 Jun 28 06:57:49 PM PDT 24 617654324 ps
T844 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4210912213 Jun 28 06:58:59 PM PDT 24 Jun 28 06:59:06 PM PDT 24 597758015 ps
T845 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3707325439 Jun 28 06:59:20 PM PDT 24 Jun 28 06:59:23 PM PDT 24 514944236 ps
T846 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3790618402 Jun 28 06:58:18 PM PDT 24 Jun 28 06:58:23 PM PDT 24 349120505 ps
T847 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.589036629 Jun 28 06:59:10 PM PDT 24 Jun 28 06:59:23 PM PDT 24 4171575114 ps
T848 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.643552937 Jun 28 06:59:21 PM PDT 24 Jun 28 06:59:24 PM PDT 24 428962978 ps
T849 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4065389043 Jun 28 06:58:29 PM PDT 24 Jun 28 06:58:31 PM PDT 24 422532295 ps
T103 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3633546552 Jun 28 06:58:04 PM PDT 24 Jun 28 06:59:33 PM PDT 24 48325451054 ps
T850 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4051731608 Jun 28 06:59:21 PM PDT 24 Jun 28 06:59:24 PM PDT 24 475804406 ps
T851 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2848183189 Jun 28 06:59:10 PM PDT 24 Jun 28 06:59:15 PM PDT 24 616001515 ps
T852 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2437354679 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:52 PM PDT 24 294996298 ps
T853 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.971712699 Jun 28 06:57:27 PM PDT 24 Jun 28 06:57:32 PM PDT 24 510644137 ps
T854 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3387887766 Jun 28 06:59:21 PM PDT 24 Jun 28 06:59:24 PM PDT 24 327535902 ps
T362 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2975033933 Jun 28 06:58:47 PM PDT 24 Jun 28 06:59:11 PM PDT 24 8457598185 ps
T855 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2694033281 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:51 PM PDT 24 641621429 ps
T856 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3099816973 Jun 28 06:58:58 PM PDT 24 Jun 28 06:59:01 PM PDT 24 471338992 ps
T857 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1966268028 Jun 28 06:57:29 PM PDT 24 Jun 28 06:57:49 PM PDT 24 26661577717 ps
T858 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2107990110 Jun 28 06:59:21 PM PDT 24 Jun 28 06:59:24 PM PDT 24 519544988 ps
T859 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.464894406 Jun 28 06:59:10 PM PDT 24 Jun 28 06:59:13 PM PDT 24 535726542 ps
T104 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2456649260 Jun 28 06:58:30 PM PDT 24 Jun 28 06:58:33 PM PDT 24 519658497 ps
T860 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4191971179 Jun 28 06:58:04 PM PDT 24 Jun 28 06:58:08 PM PDT 24 466877171 ps
T861 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3514404635 Jun 28 06:59:22 PM PDT 24 Jun 28 06:59:25 PM PDT 24 428735303 ps
T862 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1255791161 Jun 28 06:57:16 PM PDT 24 Jun 28 06:57:20 PM PDT 24 585896748 ps
T863 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3855062677 Jun 28 06:58:03 PM PDT 24 Jun 28 06:58:05 PM PDT 24 390501982 ps
T105 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.909416262 Jun 28 06:59:10 PM PDT 24 Jun 28 06:59:15 PM PDT 24 527105723 ps
T864 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2669117669 Jun 28 06:59:14 PM PDT 24 Jun 28 06:59:19 PM PDT 24 644738387 ps
T865 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3820713033 Jun 28 06:59:13 PM PDT 24 Jun 28 06:59:19 PM PDT 24 485365008 ps
T866 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.368120231 Jun 28 06:58:50 PM PDT 24 Jun 28 06:58:58 PM PDT 24 2297605593 ps
T106 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2799215633 Jun 28 06:57:31 PM PDT 24 Jun 28 06:57:34 PM PDT 24 563414564 ps
T867 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3126816461 Jun 28 06:59:19 PM PDT 24 Jun 28 06:59:22 PM PDT 24 544662409 ps
T868 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1333575524 Jun 28 06:59:13 PM PDT 24 Jun 28 06:59:18 PM PDT 24 389941513 ps
T869 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2387190683 Jun 28 06:57:51 PM PDT 24 Jun 28 06:57:55 PM PDT 24 1438576309 ps
T870 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1118754309 Jun 28 06:58:47 PM PDT 24 Jun 28 06:58:50 PM PDT 24 391597219 ps
T871 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.877695565 Jun 28 06:58:32 PM PDT 24 Jun 28 06:58:34 PM PDT 24 472222199 ps
T872 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3302001120 Jun 28 06:57:30 PM PDT 24 Jun 28 06:57:33 PM PDT 24 410272267 ps
T873 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1660799071 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:58 PM PDT 24 8527332114 ps
T874 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2394527822 Jun 28 06:58:20 PM PDT 24 Jun 28 06:58:24 PM PDT 24 423955074 ps
T875 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2769367475 Jun 28 06:58:32 PM PDT 24 Jun 28 06:58:51 PM PDT 24 4472242834 ps
T107 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4194527650 Jun 28 06:58:03 PM PDT 24 Jun 28 06:58:07 PM PDT 24 905715149 ps
T876 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.568295792 Jun 28 06:58:02 PM PDT 24 Jun 28 06:58:06 PM PDT 24 321062579 ps
T877 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2775087680 Jun 28 06:57:26 PM PDT 24 Jun 28 06:57:32 PM PDT 24 4779133430 ps
T108 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2275273653 Jun 28 06:57:50 PM PDT 24 Jun 28 06:57:53 PM PDT 24 577211268 ps
T878 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1352056886 Jun 28 06:59:12 PM PDT 24 Jun 28 06:59:19 PM PDT 24 834048522 ps
T879 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1257642024 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:54 PM PDT 24 4775616025 ps
T880 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4114347709 Jun 28 06:59:11 PM PDT 24 Jun 28 06:59:15 PM PDT 24 399115216 ps
T881 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.792880169 Jun 28 06:58:05 PM PDT 24 Jun 28 06:58:08 PM PDT 24 462799328 ps
T882 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4054045262 Jun 28 06:59:23 PM PDT 24 Jun 28 06:59:26 PM PDT 24 517865231 ps
T883 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2704743516 Jun 28 06:59:01 PM PDT 24 Jun 28 06:59:07 PM PDT 24 537480301 ps
T884 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1485468213 Jun 28 06:57:52 PM PDT 24 Jun 28 06:57:55 PM PDT 24 432163379 ps
T885 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2049775118 Jun 28 06:58:49 PM PDT 24 Jun 28 06:58:53 PM PDT 24 424856871 ps
T886 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.623965106 Jun 28 06:58:29 PM PDT 24 Jun 28 06:58:42 PM PDT 24 5305375131 ps
T887 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.542977816 Jun 28 06:59:00 PM PDT 24 Jun 28 06:59:15 PM PDT 24 8083928705 ps
T888 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1466715636 Jun 28 06:59:21 PM PDT 24 Jun 28 06:59:24 PM PDT 24 533208865 ps
T889 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2149383967 Jun 28 06:59:01 PM PDT 24 Jun 28 06:59:14 PM PDT 24 4403871224 ps
T890 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2602530244 Jun 28 06:59:34 PM PDT 24 Jun 28 06:59:37 PM PDT 24 480221126 ps
T891 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2920839933 Jun 28 06:59:10 PM PDT 24 Jun 28 06:59:13 PM PDT 24 473460851 ps
T892 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4047383496 Jun 28 06:58:48 PM PDT 24 Jun 28 06:58:53 PM PDT 24 385905721 ps
T893 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3552081899 Jun 28 06:59:23 PM PDT 24 Jun 28 06:59:26 PM PDT 24 542145274 ps
T894 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3350359580 Jun 28 06:58:19 PM PDT 24 Jun 28 06:58:24 PM PDT 24 414382988 ps
T895 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1425693903 Jun 28 06:58:03 PM PDT 24 Jun 28 06:58:06 PM PDT 24 381484318 ps
T896 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1997916365 Jun 28 06:58:16 PM PDT 24 Jun 28 06:58:19 PM PDT 24 496661043 ps
T897 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1421028879 Jun 28 06:57:48 PM PDT 24 Jun 28 06:57:55 PM PDT 24 8684765267 ps
T898 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.229305235 Jun 28 06:57:51 PM PDT 24 Jun 28 06:57:54 PM PDT 24 1316626936 ps
T899 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3202945157 Jun 28 06:58:59 PM PDT 24 Jun 28 06:59:04 PM PDT 24 470656887 ps
T900 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1190950616 Jun 28 06:57:47 PM PDT 24 Jun 28 06:57:51 PM PDT 24 943407227 ps
T901 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2461566713 Jun 28 06:58:14 PM PDT 24 Jun 28 06:58:17 PM PDT 24 448952216 ps
T902 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2255102227 Jun 28 06:59:12 PM PDT 24 Jun 28 06:59:18 PM PDT 24 4242845546 ps
T903 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1571914986 Jun 28 06:58:59 PM PDT 24 Jun 28 06:59:18 PM PDT 24 4243182945 ps
T904 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1840109639 Jun 28 06:59:01 PM PDT 24 Jun 28 06:59:07 PM PDT 24 2512386373 ps
T905 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4080022493 Jun 28 06:58:49 PM PDT 24 Jun 28 06:58:53 PM PDT 24 764765246 ps
T906 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.590105664 Jun 28 06:58:15 PM PDT 24 Jun 28 06:58:19 PM PDT 24 2435161537 ps
T907 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3412307736 Jun 28 06:57:51 PM PDT 24 Jun 28 06:57:54 PM PDT 24 463601974 ps
T908 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3957120488 Jun 28 06:59:22 PM PDT 24 Jun 28 06:59:24 PM PDT 24 496901783 ps
T909 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2662304523 Jun 28 06:59:13 PM PDT 24 Jun 28 06:59:19 PM PDT 24 508978248 ps
T910 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1921479220 Jun 28 06:59:21 PM PDT 24 Jun 28 06:59:24 PM PDT 24 436695310 ps
T109 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4175767450 Jun 28 06:58:04 PM PDT 24 Jun 28 06:58:08 PM PDT 24 665691071 ps
T911 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.359450711 Jun 28 06:58:14 PM PDT 24 Jun 28 06:58:31 PM PDT 24 4824650857 ps
T912 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2128454736 Jun 28 06:58:04 PM PDT 24 Jun 28 06:58:09 PM PDT 24 9045626886 ps
T913 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2520037954 Jun 28 06:59:20 PM PDT 24 Jun 28 06:59:23 PM PDT 24 292694947 ps
T914 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.361641991 Jun 28 06:59:14 PM PDT 24 Jun 28 06:59:19 PM PDT 24 301768736 ps
T915 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1600739762 Jun 28 06:57:48 PM PDT 24 Jun 28 06:57:53 PM PDT 24 2274126736 ps
T916 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1557628967 Jun 28 06:59:00 PM PDT 24 Jun 28 06:59:05 PM PDT 24 508630352 ps
T917 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4187789166 Jun 28 06:59:20 PM PDT 24 Jun 28 06:59:22 PM PDT 24 428297391 ps
T918 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2314990414 Jun 28 06:59:10 PM PDT 24 Jun 28 06:59:15 PM PDT 24 4858117649 ps
T919 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1353774289 Jun 28 06:58:31 PM PDT 24 Jun 28 06:58:34 PM PDT 24 562435781 ps
T110 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.502343757 Jun 28 06:58:18 PM PDT 24 Jun 28 06:58:24 PM PDT 24 512896702 ps

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1307498637
Short name T3
Test name
Test status
Simulation time 614156515944 ps
CPU time 1653.69 seconds
Started Jun 28 07:00:05 PM PDT 24
Finished Jun 28 07:27:43 PM PDT 24
Peak memory 202248 kb
Host smart-926a7a03-6dd3-47a6-a77d-5fbb0ed87a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307498637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1307498637
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3778959371
Short name T11
Test name
Test status
Simulation time 61244163890 ps
CPU time 95.06 seconds
Started Jun 28 07:12:04 PM PDT 24
Finished Jun 28 07:13:43 PM PDT 24
Peak memory 210580 kb
Host smart-3e53850d-80c8-40cc-8e25-f9e0c5124dac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778959371 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3778959371
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.4007096215
Short name T40
Test name
Test status
Simulation time 281412579112 ps
CPU time 245.61 seconds
Started Jun 28 07:13:28 PM PDT 24
Finished Jun 28 07:17:41 PM PDT 24
Peak memory 212964 kb
Host smart-a9a87637-2d1e-41cf-9719-8097ab47b7cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007096215 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.4007096215
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3907495210
Short name T26
Test name
Test status
Simulation time 339863818619 ps
CPU time 394.89 seconds
Started Jun 28 07:09:54 PM PDT 24
Finished Jun 28 07:16:35 PM PDT 24
Peak memory 201880 kb
Host smart-a5d630c3-18a9-4202-8d08-ed2fea6a9abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907495210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3907495210
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1987061612
Short name T55
Test name
Test status
Simulation time 511526440380 ps
CPU time 350.77 seconds
Started Jun 28 07:13:55 PM PDT 24
Finished Jun 28 07:19:46 PM PDT 24
Peak memory 201864 kb
Host smart-8eadaa7c-d40f-4083-b379-80db316d1461
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987061612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1987061612
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3973295087
Short name T224
Test name
Test status
Simulation time 123629549490 ps
CPU time 446.34 seconds
Started Jun 28 07:00:05 PM PDT 24
Finished Jun 28 07:07:34 PM PDT 24
Peak memory 202256 kb
Host smart-81b62d86-b69c-42a5-bdb1-a8e047f8f0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973295087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3973295087
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3631574775
Short name T259
Test name
Test status
Simulation time 489302036888 ps
CPU time 699.58 seconds
Started Jun 28 07:01:16 PM PDT 24
Finished Jun 28 07:12:59 PM PDT 24
Peak memory 201900 kb
Host smart-8e21d420-8241-4348-ba3f-d723d5d3d967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631574775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3631574775
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.657774647
Short name T25
Test name
Test status
Simulation time 590358584317 ps
CPU time 112.27 seconds
Started Jun 28 07:09:27 PM PDT 24
Finished Jun 28 07:11:25 PM PDT 24
Peak memory 210204 kb
Host smart-e3da684c-221f-4c3b-b8b4-db746beaf1f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657774647 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.657774647
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3826560418
Short name T122
Test name
Test status
Simulation time 694259203831 ps
CPU time 394.97 seconds
Started Jun 28 07:05:41 PM PDT 24
Finished Jun 28 07:12:17 PM PDT 24
Peak memory 201896 kb
Host smart-f509392f-3f5c-46fd-8445-4154e547a053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826560418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3826560418
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1976009086
Short name T54
Test name
Test status
Simulation time 371110074541 ps
CPU time 773.46 seconds
Started Jun 28 07:12:05 PM PDT 24
Finished Jun 28 07:25:03 PM PDT 24
Peak memory 201812 kb
Host smart-b54aab8f-c347-43bf-9c96-4479b190ccb6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976009086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1976009086
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.422487752
Short name T59
Test name
Test status
Simulation time 446253388 ps
CPU time 1.57 seconds
Started Jun 28 06:58:30 PM PDT 24
Finished Jun 28 06:58:33 PM PDT 24
Peak memory 201728 kb
Host smart-8a36218b-d160-42ac-a2fa-8337db66f507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422487752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.422487752
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3465051835
Short name T84
Test name
Test status
Simulation time 513145518351 ps
CPU time 440.97 seconds
Started Jun 28 07:05:28 PM PDT 24
Finished Jun 28 07:12:51 PM PDT 24
Peak memory 201892 kb
Host smart-cf42f0fb-7423-4dbd-b9a3-e18236f82231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465051835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3465051835
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.4175152562
Short name T62
Test name
Test status
Simulation time 4462647288 ps
CPU time 2.31 seconds
Started Jun 28 06:59:43 PM PDT 24
Finished Jun 28 06:59:48 PM PDT 24
Peak memory 217092 kb
Host smart-e5a0f97b-389f-44e3-bcfb-c22321590216
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175152562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.4175152562
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.4187689407
Short name T143
Test name
Test status
Simulation time 562812746198 ps
CPU time 358.27 seconds
Started Jun 28 07:01:15 PM PDT 24
Finished Jun 28 07:07:18 PM PDT 24
Peak memory 201872 kb
Host smart-f78d65ef-b25e-4fef-a225-a1ecee539424
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187689407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.4187689407
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.339027264
Short name T133
Test name
Test status
Simulation time 516285103696 ps
CPU time 253.78 seconds
Started Jun 28 07:00:25 PM PDT 24
Finished Jun 28 07:04:41 PM PDT 24
Peak memory 201848 kb
Host smart-6468cb2c-5e5c-4dcf-9cac-384abe444740
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339027264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.339027264
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.1869546164
Short name T192
Test name
Test status
Simulation time 514225696559 ps
CPU time 312.85 seconds
Started Jun 28 07:06:15 PM PDT 24
Finished Jun 28 07:11:29 PM PDT 24
Peak memory 201880 kb
Host smart-4b3b4ad4-ee22-4863-a43a-93567cfb0d17
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869546164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.1869546164
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2657675372
Short name T2
Test name
Test status
Simulation time 492034567136 ps
CPU time 303.11 seconds
Started Jun 28 07:05:27 PM PDT 24
Finished Jun 28 07:10:31 PM PDT 24
Peak memory 201980 kb
Host smart-56d5a293-66b7-420d-bca1-8de01d9c66e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657675372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2657675372
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.449177288
Short name T279
Test name
Test status
Simulation time 526320242882 ps
CPU time 1205.35 seconds
Started Jun 28 07:14:01 PM PDT 24
Finished Jun 28 07:34:11 PM PDT 24
Peak memory 201896 kb
Host smart-549a2241-8668-4faa-a048-fd4361dd9d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449177288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.449177288
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4214343888
Short name T101
Test name
Test status
Simulation time 1381494721 ps
CPU time 6.02 seconds
Started Jun 28 06:57:27 PM PDT 24
Finished Jun 28 06:57:35 PM PDT 24
Peak memory 201692 kb
Host smart-4ca2c010-a344-4623-8147-6fc1e448a0fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214343888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.4214343888
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.876543745
Short name T213
Test name
Test status
Simulation time 326670669479 ps
CPU time 198.58 seconds
Started Jun 28 07:10:55 PM PDT 24
Finished Jun 28 07:14:20 PM PDT 24
Peak memory 201864 kb
Host smart-a2855885-db90-4de1-ba34-7ed66a8ca8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876543745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.876543745
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3037178950
Short name T16
Test name
Test status
Simulation time 251204801206 ps
CPU time 158.92 seconds
Started Jun 28 07:03:35 PM PDT 24
Finished Jun 28 07:06:14 PM PDT 24
Peak memory 210268 kb
Host smart-3530d77d-1f76-41d1-861b-17daaab8f527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037178950 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3037178950
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1780543811
Short name T287
Test name
Test status
Simulation time 491183820248 ps
CPU time 1042.25 seconds
Started Jun 28 07:13:29 PM PDT 24
Finished Jun 28 07:30:58 PM PDT 24
Peak memory 201872 kb
Host smart-674671dc-6aa0-473e-b58a-21e9c2bbb776
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780543811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1780543811
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3536276352
Short name T344
Test name
Test status
Simulation time 338523070345 ps
CPU time 405.38 seconds
Started Jun 28 07:01:59 PM PDT 24
Finished Jun 28 07:08:47 PM PDT 24
Peak memory 201876 kb
Host smart-b953fd4b-8271-4086-b1d3-c04055025d5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536276352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3536276352
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1926628970
Short name T34
Test name
Test status
Simulation time 280872609828 ps
CPU time 209.37 seconds
Started Jun 28 07:09:08 PM PDT 24
Finished Jun 28 07:12:42 PM PDT 24
Peak memory 211536 kb
Host smart-d6a848fc-fe3d-471e-a46d-5ecb911082e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926628970 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1926628970
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3239575172
Short name T132
Test name
Test status
Simulation time 1046109163192 ps
CPU time 2332.6 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:39:04 PM PDT 24
Peak memory 218536 kb
Host smart-3e1dc4af-eca9-4d21-89a8-eadf10b8a620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239575172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3239575172
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3836605829
Short name T313
Test name
Test status
Simulation time 572549252566 ps
CPU time 716.81 seconds
Started Jun 28 07:04:25 PM PDT 24
Finished Jun 28 07:16:23 PM PDT 24
Peak memory 201908 kb
Host smart-ad3ed3a5-2ea6-4fd1-8e31-a00d8a07587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836605829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3836605829
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2882786926
Short name T210
Test name
Test status
Simulation time 606220583747 ps
CPU time 1417.75 seconds
Started Jun 28 07:02:11 PM PDT 24
Finished Jun 28 07:25:50 PM PDT 24
Peak memory 201928 kb
Host smart-de81b313-b0fe-4be2-b2c3-cd15174a17b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882786926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2882786926
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3976248020
Short name T168
Test name
Test status
Simulation time 495164759756 ps
CPU time 207.18 seconds
Started Jun 28 07:06:02 PM PDT 24
Finished Jun 28 07:09:31 PM PDT 24
Peak memory 201952 kb
Host smart-ef04ebf7-d771-4244-97f0-012edf2d6712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976248020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3976248020
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1328010921
Short name T408
Test name
Test status
Simulation time 517090540 ps
CPU time 1.18 seconds
Started Jun 28 06:59:43 PM PDT 24
Finished Jun 28 06:59:47 PM PDT 24
Peak memory 201620 kb
Host smart-abba7eba-892c-4804-860a-c73d80b00a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328010921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1328010921
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2442158536
Short name T125
Test name
Test status
Simulation time 421956558225 ps
CPU time 719.64 seconds
Started Jun 28 07:13:26 PM PDT 24
Finished Jun 28 07:25:33 PM PDT 24
Peak memory 202156 kb
Host smart-c3bb4a23-450a-4d60-8df2-56ef76c7e483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442158536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2442158536
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.825202849
Short name T142
Test name
Test status
Simulation time 360168327287 ps
CPU time 772.94 seconds
Started Jun 28 07:13:55 PM PDT 24
Finished Jun 28 07:26:49 PM PDT 24
Peak memory 201980 kb
Host smart-ffd031df-4054-4d14-a78d-2df7aac509b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825202849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.825202849
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3872802980
Short name T61
Test name
Test status
Simulation time 8538631238 ps
CPU time 21.4 seconds
Started Jun 28 06:59:00 PM PDT 24
Finished Jun 28 06:59:25 PM PDT 24
Peak memory 201880 kb
Host smart-ef56df01-2df6-4d8b-8c0f-42417bbc06bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872802980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3872802980
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.214032648
Short name T203
Test name
Test status
Simulation time 61215771582 ps
CPU time 107.5 seconds
Started Jun 28 07:02:05 PM PDT 24
Finished Jun 28 07:03:54 PM PDT 24
Peak memory 211036 kb
Host smart-c011d866-c848-48e8-90f4-792d2efcb2e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214032648 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.214032648
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1380370995
Short name T309
Test name
Test status
Simulation time 493752434550 ps
CPU time 1016.51 seconds
Started Jun 28 06:59:55 PM PDT 24
Finished Jun 28 07:16:54 PM PDT 24
Peak memory 201868 kb
Host smart-d176b2f0-9739-4383-9a92-848f6c9e330d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380370995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1380370995
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.723374172
Short name T155
Test name
Test status
Simulation time 486912309934 ps
CPU time 336.78 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:05:47 PM PDT 24
Peak memory 201888 kb
Host smart-ac619b7e-ace0-4518-8370-a88941e5ab93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723374172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.723374172
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.161065638
Short name T111
Test name
Test status
Simulation time 1750537504 ps
CPU time 4.5 seconds
Started Jun 28 06:57:29 PM PDT 24
Finished Jun 28 06:57:36 PM PDT 24
Peak memory 201512 kb
Host smart-ed1eaf28-5e46-4d75-bd52-506120c4e745
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161065638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.161065638
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.741365125
Short name T22
Test name
Test status
Simulation time 515265610732 ps
CPU time 289.67 seconds
Started Jun 28 07:09:27 PM PDT 24
Finished Jun 28 07:14:22 PM PDT 24
Peak memory 201884 kb
Host smart-5b576478-68be-4870-ab09-baa9e59cd782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741365125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.741365125
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3520417656
Short name T255
Test name
Test status
Simulation time 339770241896 ps
CPU time 677.05 seconds
Started Jun 28 07:14:39 PM PDT 24
Finished Jun 28 07:26:22 PM PDT 24
Peak memory 201892 kb
Host smart-eaa5df10-a44a-44e7-ad5c-b72a05f22ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520417656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3520417656
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3230452082
Short name T251
Test name
Test status
Simulation time 329201738735 ps
CPU time 427.19 seconds
Started Jun 28 07:08:29 PM PDT 24
Finished Jun 28 07:15:39 PM PDT 24
Peak memory 201804 kb
Host smart-702fae0f-7b6d-45f7-a3c6-85356a9e0313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230452082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3230452082
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.965433024
Short name T296
Test name
Test status
Simulation time 70553199964 ps
CPU time 87.47 seconds
Started Jun 28 07:11:12 PM PDT 24
Finished Jun 28 07:12:43 PM PDT 24
Peak memory 217784 kb
Host smart-28fad488-9d4c-4199-bd67-3129b8e7697a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965433024 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.965433024
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3980851917
Short name T38
Test name
Test status
Simulation time 110107000970 ps
CPU time 68.77 seconds
Started Jun 28 06:59:45 PM PDT 24
Finished Jun 28 07:00:57 PM PDT 24
Peak memory 210188 kb
Host smart-b9720e12-ea15-433f-a86d-c4c72f7b4746
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980851917 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3980851917
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3521010534
Short name T305
Test name
Test status
Simulation time 491189544756 ps
CPU time 273.11 seconds
Started Jun 28 07:03:23 PM PDT 24
Finished Jun 28 07:07:58 PM PDT 24
Peak memory 201872 kb
Host smart-0c3e36ca-3b5a-4c25-8bc8-c74dfeb34638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521010534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3521010534
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2066517289
Short name T292
Test name
Test status
Simulation time 486532582508 ps
CPU time 537.01 seconds
Started Jun 28 07:06:27 PM PDT 24
Finished Jun 28 07:15:25 PM PDT 24
Peak memory 201884 kb
Host smart-f698baf0-c84a-4f2c-9d38-363855b602d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066517289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2066517289
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.552522876
Short name T136
Test name
Test status
Simulation time 407494459512 ps
CPU time 915.09 seconds
Started Jun 28 07:08:29 PM PDT 24
Finished Jun 28 07:23:47 PM PDT 24
Peak memory 201872 kb
Host smart-5815c713-3823-49d8-8c48-3e311ee66fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552522876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.552522876
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2089201963
Short name T91
Test name
Test status
Simulation time 374956866649 ps
CPU time 202.43 seconds
Started Jun 28 06:59:33 PM PDT 24
Finished Jun 28 07:02:58 PM PDT 24
Peak memory 201876 kb
Host smart-5b23040f-df94-4427-83e2-2d42d5ad639b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089201963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2089201963
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2342724322
Short name T266
Test name
Test status
Simulation time 204270476508 ps
CPU time 488.9 seconds
Started Jun 28 07:01:59 PM PDT 24
Finished Jun 28 07:10:11 PM PDT 24
Peak memory 201876 kb
Host smart-33e36817-db7f-43bf-9ac3-4e3c0a7f5897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342724322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2342724322
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1317128356
Short name T333
Test name
Test status
Simulation time 166662727017 ps
CPU time 101.23 seconds
Started Jun 28 07:04:34 PM PDT 24
Finished Jun 28 07:06:16 PM PDT 24
Peak memory 210204 kb
Host smart-908a7c2a-580f-4da0-b262-61880c98287f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317128356 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1317128356
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2714364142
Short name T189
Test name
Test status
Simulation time 497303503319 ps
CPU time 1203.28 seconds
Started Jun 28 07:12:05 PM PDT 24
Finished Jun 28 07:32:13 PM PDT 24
Peak memory 201880 kb
Host smart-1046accd-d24f-4769-8cf8-b91db7c9061f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714364142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2714364142
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1230869776
Short name T326
Test name
Test status
Simulation time 184655544950 ps
CPU time 125.17 seconds
Started Jun 28 07:01:47 PM PDT 24
Finished Jun 28 07:03:53 PM PDT 24
Peak memory 210172 kb
Host smart-48495e79-24b8-40b9-a20d-83d0597edfe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230869776 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1230869776
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.513557849
Short name T144
Test name
Test status
Simulation time 544716698819 ps
CPU time 1220.54 seconds
Started Jun 28 07:05:54 PM PDT 24
Finished Jun 28 07:26:15 PM PDT 24
Peak memory 201948 kb
Host smart-c297b0fe-a5e1-46ba-8c71-35517e26ecb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513557849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.513557849
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3326263014
Short name T260
Test name
Test status
Simulation time 381534576804 ps
CPU time 143.4 seconds
Started Jun 28 07:13:28 PM PDT 24
Finished Jun 28 07:15:59 PM PDT 24
Peak memory 201880 kb
Host smart-9059c0fd-7440-4ce5-8f9c-28d4e7722f46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326263014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3326263014
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2385563852
Short name T265
Test name
Test status
Simulation time 166272575653 ps
CPU time 110.78 seconds
Started Jun 28 06:59:43 PM PDT 24
Finished Jun 28 07:01:36 PM PDT 24
Peak memory 201904 kb
Host smart-19db2983-d576-4eb0-9009-6ab11ed8c6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385563852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2385563852
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.642809407
Short name T282
Test name
Test status
Simulation time 164162219905 ps
CPU time 371.04 seconds
Started Jun 28 07:01:48 PM PDT 24
Finished Jun 28 07:08:00 PM PDT 24
Peak memory 201928 kb
Host smart-e56e39ee-5c9c-4557-a66a-26da847efa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642809407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.642809407
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2867190244
Short name T230
Test name
Test status
Simulation time 665164967298 ps
CPU time 1910.18 seconds
Started Jun 28 06:59:56 PM PDT 24
Finished Jun 28 07:31:48 PM PDT 24
Peak memory 202184 kb
Host smart-9343f58a-aeb3-406c-b7df-b4721ce1584d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867190244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2867190244
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2002715111
Short name T220
Test name
Test status
Simulation time 115746872439 ps
CPU time 464.34 seconds
Started Jun 28 07:08:27 PM PDT 24
Finished Jun 28 07:16:15 PM PDT 24
Peak memory 202252 kb
Host smart-248a003d-86ea-4beb-bd49-1249ca2e0c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002715111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2002715111
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1037486043
Short name T300
Test name
Test status
Simulation time 543669517075 ps
CPU time 333.22 seconds
Started Jun 28 07:01:08 PM PDT 24
Finished Jun 28 07:06:42 PM PDT 24
Peak memory 201856 kb
Host smart-9eee94d5-5a0a-45f8-b353-cfbe2056eea0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037486043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1037486043
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.253240418
Short name T271
Test name
Test status
Simulation time 341710967364 ps
CPU time 139.16 seconds
Started Jun 28 07:02:21 PM PDT 24
Finished Jun 28 07:04:42 PM PDT 24
Peak memory 201876 kb
Host smart-1a8344f2-e4d7-445f-b7f9-00a0e57e31ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253240418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.253240418
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3364405589
Short name T23
Test name
Test status
Simulation time 140325892832 ps
CPU time 486.93 seconds
Started Jun 28 07:13:57 PM PDT 24
Finished Jun 28 07:22:07 PM PDT 24
Peak memory 202244 kb
Host smart-38e1b323-bda8-4076-8e96-6b173a23b315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364405589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3364405589
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3340237246
Short name T361
Test name
Test status
Simulation time 8237444686 ps
CPU time 6.76 seconds
Started Jun 28 06:58:59 PM PDT 24
Finished Jun 28 06:59:09 PM PDT 24
Peak memory 201856 kb
Host smart-e2f185b2-8f23-4073-a33c-321c8879306e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340237246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3340237246
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2205194862
Short name T342
Test name
Test status
Simulation time 219592979434 ps
CPU time 376.51 seconds
Started Jun 28 06:59:33 PM PDT 24
Finished Jun 28 07:05:52 PM PDT 24
Peak memory 201856 kb
Host smart-e930a740-bd07-47ca-9285-cf36cef5e845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205194862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2205194862
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.4024584729
Short name T358
Test name
Test status
Simulation time 167903753032 ps
CPU time 388.61 seconds
Started Jun 28 07:02:46 PM PDT 24
Finished Jun 28 07:09:17 PM PDT 24
Peak memory 201868 kb
Host smart-db954eec-3253-40bc-896a-39ea5b44726a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024584729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.4024584729
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.482779988
Short name T316
Test name
Test status
Simulation time 325061297616 ps
CPU time 199.8 seconds
Started Jun 28 07:04:14 PM PDT 24
Finished Jun 28 07:07:36 PM PDT 24
Peak memory 201856 kb
Host smart-0af033c3-0953-458a-a04b-d61bf4927439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482779988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.482779988
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3018442391
Short name T338
Test name
Test status
Simulation time 337459365396 ps
CPU time 102.8 seconds
Started Jun 28 07:09:10 PM PDT 24
Finished Jun 28 07:10:57 PM PDT 24
Peak memory 201888 kb
Host smart-25dec88f-9407-4d97-a84c-5a20cf00523e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018442391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3018442391
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3546927721
Short name T336
Test name
Test status
Simulation time 22995523782 ps
CPU time 48.99 seconds
Started Jun 28 07:00:04 PM PDT 24
Finished Jun 28 07:00:56 PM PDT 24
Peak memory 202004 kb
Host smart-c426096c-1605-42cb-a552-d1100c493ddf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546927721 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3546927721
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2333256112
Short name T631
Test name
Test status
Simulation time 570725869432 ps
CPU time 866.48 seconds
Started Jun 28 06:59:33 PM PDT 24
Finished Jun 28 07:14:02 PM PDT 24
Peak memory 201872 kb
Host smart-a2012fa2-d52d-4971-a0d4-aabc4ace1ad2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333256112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2333256112
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.308535384
Short name T331
Test name
Test status
Simulation time 552511113851 ps
CPU time 495.48 seconds
Started Jun 28 06:59:34 PM PDT 24
Finished Jun 28 07:07:52 PM PDT 24
Peak memory 210500 kb
Host smart-6c56cc60-459c-4e02-9fda-29c43e5a1f2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308535384 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.308535384
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1853239612
Short name T330
Test name
Test status
Simulation time 165611972444 ps
CPU time 25.06 seconds
Started Jun 28 07:04:56 PM PDT 24
Finished Jun 28 07:05:22 PM PDT 24
Peak memory 201872 kb
Host smart-dd31b7c0-c583-41b9-9f93-269c3d73453e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853239612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1853239612
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3732747525
Short name T20
Test name
Test status
Simulation time 330318773169 ps
CPU time 190.49 seconds
Started Jun 28 07:06:29 PM PDT 24
Finished Jun 28 07:09:40 PM PDT 24
Peak memory 210264 kb
Host smart-0f3e79c8-b0f8-48ae-9aba-9e07499dbefa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732747525 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3732747525
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1320331387
Short name T9
Test name
Test status
Simulation time 452827491742 ps
CPU time 647.3 seconds
Started Jun 28 07:08:28 PM PDT 24
Finished Jun 28 07:19:19 PM PDT 24
Peak memory 202164 kb
Host smart-0cf34055-2542-4ce3-9700-4efc13fe1df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320331387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1320331387
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.843963626
Short name T222
Test name
Test status
Simulation time 102443168053 ps
CPU time 343.94 seconds
Started Jun 28 07:09:27 PM PDT 24
Finished Jun 28 07:15:17 PM PDT 24
Peak memory 202324 kb
Host smart-38b578b2-1ec3-407f-8bdb-d75e9e4ecf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843963626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.843963626
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3838934413
Short name T217
Test name
Test status
Simulation time 127255219514 ps
CPU time 189.7 seconds
Started Jun 28 07:10:52 PM PDT 24
Finished Jun 28 07:14:10 PM PDT 24
Peak memory 218656 kb
Host smart-1a887a6a-613c-472e-9184-f1142b314294
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838934413 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3838934413
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.48554166
Short name T188
Test name
Test status
Simulation time 382190495371 ps
CPU time 221.24 seconds
Started Jun 28 07:12:04 PM PDT 24
Finished Jun 28 07:15:49 PM PDT 24
Peak memory 201968 kb
Host smart-ef8644e9-539f-4413-8ddf-74fdeb4a3a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48554166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.48554166
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.4187961210
Short name T228
Test name
Test status
Simulation time 98458465032 ps
CPU time 566.19 seconds
Started Jun 28 07:00:04 PM PDT 24
Finished Jun 28 07:09:33 PM PDT 24
Peak memory 202200 kb
Host smart-1c67a82e-eafc-42e1-9b77-6e510fa9081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187961210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4187961210
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1299134777
Short name T343
Test name
Test status
Simulation time 199332279384 ps
CPU time 36.98 seconds
Started Jun 28 07:00:15 PM PDT 24
Finished Jun 28 07:00:58 PM PDT 24
Peak memory 201944 kb
Host smart-50e9ebcc-f941-4865-947e-89dec41dc214
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299134777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1299134777
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.971712699
Short name T853
Test name
Test status
Simulation time 510644137 ps
CPU time 2.69 seconds
Started Jun 28 06:57:27 PM PDT 24
Finished Jun 28 06:57:32 PM PDT 24
Peak memory 211032 kb
Host smart-f430e505-da70-4168-b96f-76270c2303ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971712699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.971712699
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1660799071
Short name T873
Test name
Test status
Simulation time 8527332114 ps
CPU time 7.21 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:58 PM PDT 24
Peak memory 201832 kb
Host smart-c81e8d4f-dbc3-4657-9652-62a61400f8bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660799071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1660799071
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3609143378
Short name T304
Test name
Test status
Simulation time 597926025734 ps
CPU time 340.32 seconds
Started Jun 28 06:59:32 PM PDT 24
Finished Jun 28 07:05:13 PM PDT 24
Peak memory 201964 kb
Host smart-e02a0cae-bf7c-48d5-a0f3-9c53d4a59eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609143378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3609143378
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2916213735
Short name T315
Test name
Test status
Simulation time 497221245140 ps
CPU time 419.68 seconds
Started Jun 28 06:59:44 PM PDT 24
Finished Jun 28 07:06:46 PM PDT 24
Peak memory 201924 kb
Host smart-a559543d-3e16-489b-9d2e-5f32e369f18e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916213735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2916213735
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1462692407
Short name T349
Test name
Test status
Simulation time 516896158074 ps
CPU time 1230.82 seconds
Started Jun 28 06:59:43 PM PDT 24
Finished Jun 28 07:20:16 PM PDT 24
Peak memory 201948 kb
Host smart-69ffc502-1f00-478e-a1bc-06f5873ffa91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462692407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1462692407
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2506423175
Short name T355
Test name
Test status
Simulation time 337564484763 ps
CPU time 413.1 seconds
Started Jun 28 07:04:09 PM PDT 24
Finished Jun 28 07:11:04 PM PDT 24
Peak memory 201956 kb
Host smart-e433f6c2-5ddb-4259-bc1a-e25eed7cf344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506423175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2506423175
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3908631078
Short name T191
Test name
Test status
Simulation time 171703139550 ps
CPU time 98.69 seconds
Started Jun 28 06:59:54 PM PDT 24
Finished Jun 28 07:01:35 PM PDT 24
Peak memory 201976 kb
Host smart-75d408e5-ba46-4f17-9ff4-76e46380dc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908631078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3908631078
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.4083992675
Short name T332
Test name
Test status
Simulation time 330477935536 ps
CPU time 209.73 seconds
Started Jun 28 07:06:27 PM PDT 24
Finished Jun 28 07:09:58 PM PDT 24
Peak memory 201864 kb
Host smart-25e91a15-79e7-456e-ac32-35b3aa749fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083992675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.4083992675
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4223750279
Short name T45
Test name
Test status
Simulation time 153799412353 ps
CPU time 110.53 seconds
Started Jun 28 07:08:26 PM PDT 24
Finished Jun 28 07:10:20 PM PDT 24
Peak memory 210516 kb
Host smart-82b74c19-dcf2-476e-baf0-58c909c84fbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223750279 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4223750279
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1975707630
Short name T225
Test name
Test status
Simulation time 85593088970 ps
CPU time 358.73 seconds
Started Jun 28 07:08:28 PM PDT 24
Finished Jun 28 07:14:30 PM PDT 24
Peak memory 202276 kb
Host smart-6e9a9e8e-a2b4-4446-8044-5299f49103d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975707630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1975707630
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3236599537
Short name T227
Test name
Test status
Simulation time 250427099106 ps
CPU time 389.25 seconds
Started Jun 28 07:08:54 PM PDT 24
Finished Jun 28 07:15:24 PM PDT 24
Peak memory 210456 kb
Host smart-de54287f-b5e1-4a85-8d0d-c3634997738a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236599537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3236599537
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3580544775
Short name T179
Test name
Test status
Simulation time 330728780265 ps
CPU time 189.23 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:03:19 PM PDT 24
Peak memory 201876 kb
Host smart-95432b2f-49c5-4ee7-8c7c-d6e7aba8ecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580544775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3580544775
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3614991058
Short name T19
Test name
Test status
Simulation time 182081784839 ps
CPU time 431.69 seconds
Started Jun 28 07:14:02 PM PDT 24
Finished Jun 28 07:21:19 PM PDT 24
Peak memory 210540 kb
Host smart-2659b799-5104-4394-aa69-d1926d4e056b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614991058 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3614991058
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2178313577
Short name T329
Test name
Test status
Simulation time 565061384789 ps
CPU time 656.64 seconds
Started Jun 28 07:14:03 PM PDT 24
Finished Jun 28 07:25:06 PM PDT 24
Peak memory 201960 kb
Host smart-ca56c3ec-70bf-45b7-a10d-d511d9d4d0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178313577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2178313577
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.4094691368
Short name T346
Test name
Test status
Simulation time 565180458968 ps
CPU time 647.67 seconds
Started Jun 28 07:00:15 PM PDT 24
Finished Jun 28 07:11:09 PM PDT 24
Peak memory 201884 kb
Host smart-a028fb37-e400-4354-8b8a-d58d8100bdff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094691368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.4094691368
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.671870958
Short name T297
Test name
Test status
Simulation time 501851462799 ps
CPU time 588.04 seconds
Started Jun 28 07:00:50 PM PDT 24
Finished Jun 28 07:10:41 PM PDT 24
Peak memory 201960 kb
Host smart-fae16dd1-88c1-4231-9aa2-4b8ec5eaf878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671870958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.671870958
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2402785243
Short name T100
Test name
Test status
Simulation time 977214256 ps
CPU time 3.08 seconds
Started Jun 28 06:57:29 PM PDT 24
Finished Jun 28 06:57:34 PM PDT 24
Peak memory 201728 kb
Host smart-ed0907a4-13f5-463e-8a98-165d5bc56632
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402785243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2402785243
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1966268028
Short name T857
Test name
Test status
Simulation time 26661577717 ps
CPU time 17.81 seconds
Started Jun 28 06:57:29 PM PDT 24
Finished Jun 28 06:57:49 PM PDT 24
Peak memory 201820 kb
Host smart-d7f2b20b-ffbc-446a-bc69-a1e367c3854e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966268028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1966268028
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3222162503
Short name T97
Test name
Test status
Simulation time 648928068 ps
CPU time 2.22 seconds
Started Jun 28 06:57:26 PM PDT 24
Finished Jun 28 06:57:30 PM PDT 24
Peak memory 201512 kb
Host smart-1e1fabe4-2593-4f95-9cc4-6e40ddc95b76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222162503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3222162503
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2605984183
Short name T88
Test name
Test status
Simulation time 751674324 ps
CPU time 1.24 seconds
Started Jun 28 06:57:26 PM PDT 24
Finished Jun 28 06:57:29 PM PDT 24
Peak memory 201576 kb
Host smart-82661212-5a06-49e5-96ac-e605d40e8f25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605984183 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2605984183
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2799215633
Short name T106
Test name
Test status
Simulation time 563414564 ps
CPU time 1.03 seconds
Started Jun 28 06:57:31 PM PDT 24
Finished Jun 28 06:57:34 PM PDT 24
Peak memory 201516 kb
Host smart-d3697d47-1477-4366-8211-8d5e1aeda7f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799215633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2799215633
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2444350203
Short name T823
Test name
Test status
Simulation time 405390958 ps
CPU time 0.87 seconds
Started Jun 28 06:57:26 PM PDT 24
Finished Jun 28 06:57:29 PM PDT 24
Peak memory 201388 kb
Host smart-7bf0893b-0306-4079-a61f-79151197f0d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444350203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2444350203
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1255791161
Short name T862
Test name
Test status
Simulation time 585896748 ps
CPU time 1.61 seconds
Started Jun 28 06:57:16 PM PDT 24
Finished Jun 28 06:57:20 PM PDT 24
Peak memory 201788 kb
Host smart-14d27055-5776-42d1-aa6b-31488b7b9169
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255791161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1255791161
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1337770402
Short name T815
Test name
Test status
Simulation time 4393603195 ps
CPU time 4.42 seconds
Started Jun 28 06:57:26 PM PDT 24
Finished Jun 28 06:57:31 PM PDT 24
Peak memory 201820 kb
Host smart-962df946-2446-4ef7-86f9-7c0120900738
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337770402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1337770402
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1190950616
Short name T900
Test name
Test status
Simulation time 943407227 ps
CPU time 2.04 seconds
Started Jun 28 06:57:47 PM PDT 24
Finished Jun 28 06:57:51 PM PDT 24
Peak memory 201708 kb
Host smart-4572a50d-9da5-4c59-b0c6-24e0eee1e029
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190950616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1190950616
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2590830677
Short name T119
Test name
Test status
Simulation time 1277706019 ps
CPU time 1.08 seconds
Started Jun 28 06:57:31 PM PDT 24
Finished Jun 28 06:57:34 PM PDT 24
Peak memory 201516 kb
Host smart-259684f2-0888-49b6-95c3-9d382857ac40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590830677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2590830677
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.915332918
Short name T843
Test name
Test status
Simulation time 617654324 ps
CPU time 1.25 seconds
Started Jun 28 06:57:46 PM PDT 24
Finished Jun 28 06:57:49 PM PDT 24
Peak memory 201576 kb
Host smart-d2fa22d8-059d-4e83-9631-ac1ddc1d2408
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915332918 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.915332918
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3149888274
Short name T102
Test name
Test status
Simulation time 452232677 ps
CPU time 1.88 seconds
Started Jun 28 06:57:30 PM PDT 24
Finished Jun 28 06:57:34 PM PDT 24
Peak memory 201516 kb
Host smart-f9d2f1c1-4b8c-4371-baf6-0bf58abede12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149888274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3149888274
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3302001120
Short name T872
Test name
Test status
Simulation time 410272267 ps
CPU time 1.02 seconds
Started Jun 28 06:57:30 PM PDT 24
Finished Jun 28 06:57:33 PM PDT 24
Peak memory 201444 kb
Host smart-5270bf6b-26a9-4e15-aec8-0ecc47e20dbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302001120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3302001120
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1600739762
Short name T915
Test name
Test status
Simulation time 2274126736 ps
CPU time 2.84 seconds
Started Jun 28 06:57:48 PM PDT 24
Finished Jun 28 06:57:53 PM PDT 24
Peak memory 201616 kb
Host smart-fb68c50d-b081-408b-a181-0e19a626e3e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600739762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1600739762
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2775087680
Short name T877
Test name
Test status
Simulation time 4779133430 ps
CPU time 4.5 seconds
Started Jun 28 06:57:26 PM PDT 24
Finished Jun 28 06:57:32 PM PDT 24
Peak memory 201848 kb
Host smart-8154afd0-65fe-4604-b6e1-7048bcf1bdce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775087680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2775087680
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2049775118
Short name T885
Test name
Test status
Simulation time 424856871 ps
CPU time 1.88 seconds
Started Jun 28 06:58:49 PM PDT 24
Finished Jun 28 06:58:53 PM PDT 24
Peak memory 201572 kb
Host smart-7ee6193f-7854-4c04-a1a0-da49faf4b61d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049775118 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2049775118
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1607969159
Short name T836
Test name
Test status
Simulation time 462393512 ps
CPU time 1.11 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:52 PM PDT 24
Peak memory 201508 kb
Host smart-1bb25627-2cc6-4290-925b-4b134d27c8d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607969159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1607969159
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4195049588
Short name T807
Test name
Test status
Simulation time 286810371 ps
CPU time 1.31 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:52 PM PDT 24
Peak memory 201440 kb
Host smart-c02292ff-808e-42ec-a1c6-7e2a76574a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195049588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4195049588
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2285645547
Short name T835
Test name
Test status
Simulation time 4716806829 ps
CPU time 4.92 seconds
Started Jun 28 06:58:47 PM PDT 24
Finished Jun 28 06:58:53 PM PDT 24
Peak memory 201888 kb
Host smart-b9b3a71c-3f56-43f5-b60d-3b0378b4948e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285645547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2285645547
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2694033281
Short name T855
Test name
Test status
Simulation time 641621429 ps
CPU time 1.89 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:51 PM PDT 24
Peak memory 201764 kb
Host smart-6628587e-cfed-4846-8fe9-85afb5e1bc8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694033281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2694033281
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.932783550
Short name T809
Test name
Test status
Simulation time 4464291996 ps
CPU time 3.88 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:55 PM PDT 24
Peak memory 201816 kb
Host smart-892b2118-8c12-4d4c-af63-e175518f1ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932783550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.932783550
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4080022493
Short name T905
Test name
Test status
Simulation time 764765246 ps
CPU time 1.39 seconds
Started Jun 28 06:58:49 PM PDT 24
Finished Jun 28 06:58:53 PM PDT 24
Peak memory 201556 kb
Host smart-aa9288f4-105f-4d84-b966-f495a916a542
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080022493 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.4080022493
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3598332184
Short name T121
Test name
Test status
Simulation time 526238631 ps
CPU time 2.02 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:52 PM PDT 24
Peak memory 201512 kb
Host smart-cda9fff6-e0c4-4489-9b8e-846799dc8cb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598332184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3598332184
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2437354679
Short name T852
Test name
Test status
Simulation time 294996298 ps
CPU time 1.31 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:52 PM PDT 24
Peak memory 201452 kb
Host smart-c72eb2f8-3525-4d3b-b2af-27890735ff56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437354679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2437354679
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.368120231
Short name T866
Test name
Test status
Simulation time 2297605593 ps
CPU time 5.9 seconds
Started Jun 28 06:58:50 PM PDT 24
Finished Jun 28 06:58:58 PM PDT 24
Peak memory 201572 kb
Host smart-8f03342c-9bfd-4ddf-b7a8-eef62ccbf367
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368120231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.368120231
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1056486871
Short name T66
Test name
Test status
Simulation time 463217341 ps
CPU time 2.31 seconds
Started Jun 28 06:58:50 PM PDT 24
Finished Jun 28 06:58:55 PM PDT 24
Peak memory 201716 kb
Host smart-2a301076-04ae-4fd4-8564-d89eb65be3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056486871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1056486871
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2940698898
Short name T86
Test name
Test status
Simulation time 523322093 ps
CPU time 1.37 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:50 PM PDT 24
Peak memory 201540 kb
Host smart-213da841-3314-42c4-bce5-af7e9329e16c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940698898 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2940698898
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1118754309
Short name T870
Test name
Test status
Simulation time 391597219 ps
CPU time 1.66 seconds
Started Jun 28 06:58:47 PM PDT 24
Finished Jun 28 06:58:50 PM PDT 24
Peak memory 201532 kb
Host smart-e3a0987e-f6a5-48df-a5ee-a764d0aff129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118754309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1118754309
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1022944757
Short name T806
Test name
Test status
Simulation time 397225417 ps
CPU time 0.89 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:51 PM PDT 24
Peak memory 201432 kb
Host smart-ba778f96-3511-4a22-8619-103c7803b6e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022944757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1022944757
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1257642024
Short name T879
Test name
Test status
Simulation time 4775616025 ps
CPU time 3.23 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:54 PM PDT 24
Peak memory 201856 kb
Host smart-c1be5d7a-e5e4-4f7a-9119-a211582bee56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257642024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1257642024
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4047383496
Short name T892
Test name
Test status
Simulation time 385905721 ps
CPU time 2.28 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:53 PM PDT 24
Peak memory 201816 kb
Host smart-adc96cd8-10e0-4e17-98b0-db2219e3d6e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047383496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4047383496
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2975033933
Short name T362
Test name
Test status
Simulation time 8457598185 ps
CPU time 21.77 seconds
Started Jun 28 06:58:47 PM PDT 24
Finished Jun 28 06:59:11 PM PDT 24
Peak memory 201872 kb
Host smart-dcc2df1d-faa3-4d1c-a6f4-fb878ab0b7a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975033933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2975033933
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4017960216
Short name T811
Test name
Test status
Simulation time 542984048 ps
CPU time 2.07 seconds
Started Jun 28 06:58:59 PM PDT 24
Finished Jun 28 06:59:04 PM PDT 24
Peak memory 201576 kb
Host smart-aebc652a-9589-441a-95b4-c1055f45f7e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017960216 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.4017960216
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1557628967
Short name T916
Test name
Test status
Simulation time 508630352 ps
CPU time 1.41 seconds
Started Jun 28 06:59:00 PM PDT 24
Finished Jun 28 06:59:05 PM PDT 24
Peak memory 201516 kb
Host smart-60ba9549-3c87-4512-b6a1-788f93933e88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557628967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1557628967
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3099816973
Short name T856
Test name
Test status
Simulation time 471338992 ps
CPU time 0.96 seconds
Started Jun 28 06:58:58 PM PDT 24
Finished Jun 28 06:59:01 PM PDT 24
Peak memory 201404 kb
Host smart-41e31e10-c083-4d8d-9ee6-51e07fc1e464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099816973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3099816973
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1571914986
Short name T903
Test name
Test status
Simulation time 4243182945 ps
CPU time 15.56 seconds
Started Jun 28 06:58:59 PM PDT 24
Finished Jun 28 06:59:18 PM PDT 24
Peak memory 201896 kb
Host smart-0bfbe286-809d-4488-b776-86fca5b72371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571914986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1571914986
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3558889431
Short name T817
Test name
Test status
Simulation time 568615394 ps
CPU time 3.28 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:53 PM PDT 24
Peak memory 217688 kb
Host smart-244bf372-fd5c-4e21-b683-0e8ef41094cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558889431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3558889431
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1625683369
Short name T73
Test name
Test status
Simulation time 8542929296 ps
CPU time 11.53 seconds
Started Jun 28 06:58:59 PM PDT 24
Finished Jun 28 06:59:13 PM PDT 24
Peak memory 201812 kb
Host smart-2393e16e-3e19-4794-9339-f9b51ee38d71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625683369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1625683369
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.187686920
Short name T829
Test name
Test status
Simulation time 586875161 ps
CPU time 2.18 seconds
Started Jun 28 06:59:01 PM PDT 24
Finished Jun 28 06:59:06 PM PDT 24
Peak memory 201508 kb
Host smart-e3c0f711-e475-41a5-9f81-51c0e2ecd36f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187686920 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.187686920
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.756731004
Short name T819
Test name
Test status
Simulation time 355455823 ps
CPU time 1.21 seconds
Started Jun 28 06:58:59 PM PDT 24
Finished Jun 28 06:59:03 PM PDT 24
Peak memory 201516 kb
Host smart-b00603bf-7cca-46a8-81fb-0a9b7e0393fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756731004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.756731004
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1011379632
Short name T818
Test name
Test status
Simulation time 595783556 ps
CPU time 0.75 seconds
Started Jun 28 06:58:59 PM PDT 24
Finished Jun 28 06:59:03 PM PDT 24
Peak memory 201444 kb
Host smart-d42ee22e-3983-4daf-ad37-d165f0e465f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011379632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1011379632
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2110212112
Short name T50
Test name
Test status
Simulation time 4691384915 ps
CPU time 5.17 seconds
Started Jun 28 06:58:59 PM PDT 24
Finished Jun 28 06:59:08 PM PDT 24
Peak memory 201836 kb
Host smart-a23dc6fd-d5b1-4270-b691-b194c781fa6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110212112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2110212112
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4210912213
Short name T844
Test name
Test status
Simulation time 597758015 ps
CPU time 2.9 seconds
Started Jun 28 06:58:59 PM PDT 24
Finished Jun 28 06:59:06 PM PDT 24
Peak memory 217572 kb
Host smart-d927e929-f9f5-4098-b671-d556f06a8362
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210912213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4210912213
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2116832769
Short name T87
Test name
Test status
Simulation time 447410201 ps
CPU time 1.51 seconds
Started Jun 28 06:59:01 PM PDT 24
Finished Jun 28 06:59:06 PM PDT 24
Peak memory 201576 kb
Host smart-388e8b5c-2188-478d-8c90-dd5e1580c23b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116832769 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2116832769
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2490282131
Short name T115
Test name
Test status
Simulation time 353167901 ps
CPU time 1.71 seconds
Started Jun 28 06:58:59 PM PDT 24
Finished Jun 28 06:59:04 PM PDT 24
Peak memory 201508 kb
Host smart-2ec6cb04-ba80-4e1a-8a9e-6f79263e5a45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490282131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2490282131
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3202945157
Short name T899
Test name
Test status
Simulation time 470656887 ps
CPU time 1.22 seconds
Started Jun 28 06:58:59 PM PDT 24
Finished Jun 28 06:59:04 PM PDT 24
Peak memory 201436 kb
Host smart-3bb34699-a0c9-44cb-bb93-6c070436507a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202945157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3202945157
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2149383967
Short name T889
Test name
Test status
Simulation time 4403871224 ps
CPU time 10.29 seconds
Started Jun 28 06:59:01 PM PDT 24
Finished Jun 28 06:59:14 PM PDT 24
Peak memory 201888 kb
Host smart-0ffd36c5-0d9c-4856-b4b0-6b87a1878ae6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149383967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2149383967
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1030156890
Short name T67
Test name
Test status
Simulation time 347088349 ps
CPU time 2.98 seconds
Started Jun 28 06:58:59 PM PDT 24
Finished Jun 28 06:59:06 PM PDT 24
Peak memory 201708 kb
Host smart-e171f381-a863-432a-94fe-5445520186bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030156890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1030156890
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.542977816
Short name T887
Test name
Test status
Simulation time 8083928705 ps
CPU time 11.46 seconds
Started Jun 28 06:59:00 PM PDT 24
Finished Jun 28 06:59:15 PM PDT 24
Peak memory 201832 kb
Host smart-e85fe6a0-5a83-4f51-9231-fc1105e5e218
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542977816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.542977816
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1768227925
Short name T824
Test name
Test status
Simulation time 539350030 ps
CPU time 1.09 seconds
Started Jun 28 06:59:01 PM PDT 24
Finished Jun 28 06:59:06 PM PDT 24
Peak memory 201576 kb
Host smart-5d1c8c86-d524-4f1e-b406-7379eb732db4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768227925 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1768227925
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4027247365
Short name T113
Test name
Test status
Simulation time 498771026 ps
CPU time 0.84 seconds
Started Jun 28 06:59:00 PM PDT 24
Finished Jun 28 06:59:05 PM PDT 24
Peak memory 201492 kb
Host smart-566187ea-dffc-48af-89ac-903f9d762357
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027247365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.4027247365
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.4269643499
Short name T804
Test name
Test status
Simulation time 481045732 ps
CPU time 1.17 seconds
Started Jun 28 06:59:01 PM PDT 24
Finished Jun 28 06:59:05 PM PDT 24
Peak memory 201420 kb
Host smart-aa2777cf-73e2-4d76-8b06-b212e1277f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269643499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.4269643499
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1840109639
Short name T904
Test name
Test status
Simulation time 2512386373 ps
CPU time 2.51 seconds
Started Jun 28 06:59:01 PM PDT 24
Finished Jun 28 06:59:07 PM PDT 24
Peak memory 201636 kb
Host smart-55f2df45-ae34-47dd-bf7f-de59e5c1fd01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840109639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1840109639
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1228089069
Short name T816
Test name
Test status
Simulation time 466047372 ps
CPU time 3.37 seconds
Started Jun 28 06:59:01 PM PDT 24
Finished Jun 28 06:59:08 PM PDT 24
Peak memory 209948 kb
Host smart-5d0cb021-fba8-4faf-a1b2-de874a67d4ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228089069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1228089069
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2662304523
Short name T909
Test name
Test status
Simulation time 508978248 ps
CPU time 1.36 seconds
Started Jun 28 06:59:13 PM PDT 24
Finished Jun 28 06:59:19 PM PDT 24
Peak memory 201536 kb
Host smart-4b2a9dc0-e13e-4395-a7a1-6c80877eadb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662304523 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2662304523
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.464894406
Short name T859
Test name
Test status
Simulation time 535726542 ps
CPU time 0.97 seconds
Started Jun 28 06:59:10 PM PDT 24
Finished Jun 28 06:59:13 PM PDT 24
Peak memory 201516 kb
Host smart-f05dc182-c6b9-48e4-94a1-982d7a1f0094
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464894406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.464894406
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2980326006
Short name T837
Test name
Test status
Simulation time 396565402 ps
CPU time 1.03 seconds
Started Jun 28 06:59:10 PM PDT 24
Finished Jun 28 06:59:14 PM PDT 24
Peak memory 201436 kb
Host smart-adff9a08-3a5b-47c9-894a-f8e7c2ad88a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980326006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2980326006
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2314990414
Short name T918
Test name
Test status
Simulation time 4858117649 ps
CPU time 3.7 seconds
Started Jun 28 06:59:10 PM PDT 24
Finished Jun 28 06:59:15 PM PDT 24
Peak memory 201876 kb
Host smart-ed2d9ae7-b82d-4488-8732-b3cf32f0f922
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314990414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2314990414
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2704743516
Short name T883
Test name
Test status
Simulation time 537480301 ps
CPU time 3.09 seconds
Started Jun 28 06:59:01 PM PDT 24
Finished Jun 28 06:59:07 PM PDT 24
Peak memory 201792 kb
Host smart-ef3def5e-a68f-4199-bc99-0e4368f68550
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704743516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2704743516
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3236513578
Short name T72
Test name
Test status
Simulation time 7867364168 ps
CPU time 8.42 seconds
Started Jun 28 06:59:11 PM PDT 24
Finished Jun 28 06:59:22 PM PDT 24
Peak memory 201816 kb
Host smart-fe649f64-7cc7-467e-bfe3-b56418d8b126
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236513578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3236513578
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2669117669
Short name T864
Test name
Test status
Simulation time 644738387 ps
CPU time 1.29 seconds
Started Jun 28 06:59:14 PM PDT 24
Finished Jun 28 06:59:19 PM PDT 24
Peak memory 201584 kb
Host smart-c8538e03-b416-4add-865d-3c6147980859
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669117669 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2669117669
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.909416262
Short name T105
Test name
Test status
Simulation time 527105723 ps
CPU time 2.09 seconds
Started Jun 28 06:59:10 PM PDT 24
Finished Jun 28 06:59:15 PM PDT 24
Peak memory 201512 kb
Host smart-7b35dbfd-06f1-4a2c-a0d7-f0ea02a515ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909416262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.909416262
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4114347709
Short name T880
Test name
Test status
Simulation time 399115216 ps
CPU time 0.76 seconds
Started Jun 28 06:59:11 PM PDT 24
Finished Jun 28 06:59:15 PM PDT 24
Peak memory 201440 kb
Host smart-7ddc380d-3729-4dce-862a-5e830c2125bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114347709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4114347709
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.589036629
Short name T847
Test name
Test status
Simulation time 4171575114 ps
CPU time 9.76 seconds
Started Jun 28 06:59:10 PM PDT 24
Finished Jun 28 06:59:23 PM PDT 24
Peak memory 201904 kb
Host smart-3af4e23a-dd6a-4717-97c7-158cdc5f4166
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589036629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.589036629
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1352056886
Short name T878
Test name
Test status
Simulation time 834048522 ps
CPU time 2.07 seconds
Started Jun 28 06:59:12 PM PDT 24
Finished Jun 28 06:59:19 PM PDT 24
Peak memory 209972 kb
Host smart-85d9d054-7809-4a10-ac40-723d16b6dfea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352056886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1352056886
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.49573900
Short name T363
Test name
Test status
Simulation time 8466969351 ps
CPU time 5.83 seconds
Started Jun 28 06:59:14 PM PDT 24
Finished Jun 28 06:59:24 PM PDT 24
Peak memory 201848 kb
Host smart-3b5e1449-569d-47a6-9be6-adad080d7620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49573900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_int
g_err.49573900
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1667826040
Short name T826
Test name
Test status
Simulation time 516090833 ps
CPU time 1.87 seconds
Started Jun 28 06:59:14 PM PDT 24
Finished Jun 28 06:59:20 PM PDT 24
Peak memory 201576 kb
Host smart-917f593c-ba6d-4a62-b278-6d266ab7fa31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667826040 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1667826040
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.400805710
Short name T120
Test name
Test status
Simulation time 511320046 ps
CPU time 1.15 seconds
Started Jun 28 06:59:14 PM PDT 24
Finished Jun 28 06:59:19 PM PDT 24
Peak memory 201524 kb
Host smart-1d765999-9223-49b3-8986-31a20ccd172b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400805710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.400805710
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3227413997
Short name T828
Test name
Test status
Simulation time 464705503 ps
CPU time 1.75 seconds
Started Jun 28 06:59:14 PM PDT 24
Finished Jun 28 06:59:20 PM PDT 24
Peak memory 201444 kb
Host smart-9295e502-35f8-4410-ba97-ec3577e785df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227413997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3227413997
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2255102227
Short name T902
Test name
Test status
Simulation time 4242845546 ps
CPU time 2.42 seconds
Started Jun 28 06:59:12 PM PDT 24
Finished Jun 28 06:59:18 PM PDT 24
Peak memory 201832 kb
Host smart-663bb1a9-2e3e-465d-be2c-2617be8c47fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255102227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2255102227
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2848183189
Short name T851
Test name
Test status
Simulation time 616001515 ps
CPU time 2.93 seconds
Started Jun 28 06:59:10 PM PDT 24
Finished Jun 28 06:59:15 PM PDT 24
Peak memory 201812 kb
Host smart-e8c55a1f-2f65-40cf-9e14-7da6a79e3a51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848183189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2848183189
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3539378829
Short name T57
Test name
Test status
Simulation time 8413291688 ps
CPU time 21.68 seconds
Started Jun 28 06:59:10 PM PDT 24
Finished Jun 28 06:59:33 PM PDT 24
Peak memory 201888 kb
Host smart-65ce950f-0542-4288-bc7f-a83ef1208642
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539378829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3539378829
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2387190683
Short name T869
Test name
Test status
Simulation time 1438576309 ps
CPU time 3.17 seconds
Started Jun 28 06:57:51 PM PDT 24
Finished Jun 28 06:57:55 PM PDT 24
Peak memory 201664 kb
Host smart-e7a061ac-313b-4403-a1f8-d5c341913de2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387190683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2387190683
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.719865217
Short name T51
Test name
Test status
Simulation time 2537294184 ps
CPU time 11.36 seconds
Started Jun 28 06:57:54 PM PDT 24
Finished Jun 28 06:58:07 PM PDT 24
Peak memory 201800 kb
Host smart-68fd0e61-43b5-43d3-9b9c-6186269d7fbd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719865217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.719865217
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.229305235
Short name T898
Test name
Test status
Simulation time 1316626936 ps
CPU time 1.97 seconds
Started Jun 28 06:57:51 PM PDT 24
Finished Jun 28 06:57:54 PM PDT 24
Peak memory 201532 kb
Host smart-b76b68d8-3740-4af1-8253-17730c8cd9e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229305235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.229305235
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1572159874
Short name T842
Test name
Test status
Simulation time 516512491 ps
CPU time 1.49 seconds
Started Jun 28 06:57:50 PM PDT 24
Finished Jun 28 06:57:53 PM PDT 24
Peak memory 218124 kb
Host smart-c57499ec-6137-48c1-9625-56477e23d306
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572159874 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1572159874
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2275273653
Short name T108
Test name
Test status
Simulation time 577211268 ps
CPU time 0.86 seconds
Started Jun 28 06:57:50 PM PDT 24
Finished Jun 28 06:57:53 PM PDT 24
Peak memory 201512 kb
Host smart-ab6f4ce8-d24f-4b2f-bb9f-f29330d2f56e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275273653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2275273653
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1485468213
Short name T884
Test name
Test status
Simulation time 432163379 ps
CPU time 1.6 seconds
Started Jun 28 06:57:52 PM PDT 24
Finished Jun 28 06:57:55 PM PDT 24
Peak memory 201424 kb
Host smart-64a8723f-7041-416a-a667-1ecd31b8bf74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485468213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1485468213
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3260480483
Short name T112
Test name
Test status
Simulation time 4962068614 ps
CPU time 2.81 seconds
Started Jun 28 06:57:54 PM PDT 24
Finished Jun 28 06:57:58 PM PDT 24
Peak memory 201856 kb
Host smart-f88cbffc-7c3f-4efe-8bc7-2f37546b060c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260480483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3260480483
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3212576429
Short name T60
Test name
Test status
Simulation time 471651242 ps
CPU time 2.57 seconds
Started Jun 28 06:57:46 PM PDT 24
Finished Jun 28 06:57:51 PM PDT 24
Peak memory 201760 kb
Host smart-083141c3-0864-4c1d-a44b-a1d2c5082831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212576429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3212576429
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1421028879
Short name T897
Test name
Test status
Simulation time 8684765267 ps
CPU time 4.92 seconds
Started Jun 28 06:57:48 PM PDT 24
Finished Jun 28 06:57:55 PM PDT 24
Peak memory 201848 kb
Host smart-96bf2df2-32cb-4795-a089-c0047f95ef08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421028879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1421028879
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.726202630
Short name T832
Test name
Test status
Simulation time 326906717 ps
CPU time 0.84 seconds
Started Jun 28 06:59:10 PM PDT 24
Finished Jun 28 06:59:14 PM PDT 24
Peak memory 201432 kb
Host smart-b91b80b9-909e-41b3-9f00-04bf8ad168ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726202630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.726202630
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2167165895
Short name T810
Test name
Test status
Simulation time 460973188 ps
CPU time 0.77 seconds
Started Jun 28 06:59:11 PM PDT 24
Finished Jun 28 06:59:16 PM PDT 24
Peak memory 201416 kb
Host smart-f40d1803-7e88-402c-9814-f74ab0c1a3f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167165895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2167165895
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1998111647
Short name T841
Test name
Test status
Simulation time 291412274 ps
CPU time 0.95 seconds
Started Jun 28 06:59:09 PM PDT 24
Finished Jun 28 06:59:12 PM PDT 24
Peak memory 201436 kb
Host smart-cceec0e0-9174-4a81-9c34-d27799a7ea00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998111647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1998111647
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2920839933
Short name T891
Test name
Test status
Simulation time 473460851 ps
CPU time 0.87 seconds
Started Jun 28 06:59:10 PM PDT 24
Finished Jun 28 06:59:13 PM PDT 24
Peak memory 201440 kb
Host smart-0a8c61b4-ba45-4dcc-b6d4-6c46cc70c565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920839933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2920839933
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3820713033
Short name T865
Test name
Test status
Simulation time 485365008 ps
CPU time 1.79 seconds
Started Jun 28 06:59:13 PM PDT 24
Finished Jun 28 06:59:19 PM PDT 24
Peak memory 201436 kb
Host smart-6271992b-e6d1-4cc1-92b2-10c242b56a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820713033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3820713033
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.361641991
Short name T914
Test name
Test status
Simulation time 301768736 ps
CPU time 0.83 seconds
Started Jun 28 06:59:14 PM PDT 24
Finished Jun 28 06:59:19 PM PDT 24
Peak memory 201440 kb
Host smart-56b3b421-c5b7-489f-8554-40c412e24f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361641991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.361641991
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1333575524
Short name T868
Test name
Test status
Simulation time 389941513 ps
CPU time 1.47 seconds
Started Jun 28 06:59:13 PM PDT 24
Finished Jun 28 06:59:18 PM PDT 24
Peak memory 201400 kb
Host smart-74a8fe12-343a-43e0-bcff-4aa521454f2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333575524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1333575524
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1515977832
Short name T814
Test name
Test status
Simulation time 403747494 ps
CPU time 0.89 seconds
Started Jun 28 06:59:14 PM PDT 24
Finished Jun 28 06:59:19 PM PDT 24
Peak memory 201440 kb
Host smart-f40755be-d5a1-4848-b99a-c6f4fe4c549c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515977832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1515977832
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1466715636
Short name T888
Test name
Test status
Simulation time 533208865 ps
CPU time 1.09 seconds
Started Jun 28 06:59:21 PM PDT 24
Finished Jun 28 06:59:24 PM PDT 24
Peak memory 201436 kb
Host smart-61077040-849c-472d-8892-b6b6aeb8d177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466715636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1466715636
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4187789166
Short name T917
Test name
Test status
Simulation time 428297391 ps
CPU time 0.87 seconds
Started Jun 28 06:59:20 PM PDT 24
Finished Jun 28 06:59:22 PM PDT 24
Peak memory 201412 kb
Host smart-a4a25bd9-1f27-4f0c-b568-ed70538c3600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187789166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4187789166
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4194527650
Short name T107
Test name
Test status
Simulation time 905715149 ps
CPU time 2.75 seconds
Started Jun 28 06:58:03 PM PDT 24
Finished Jun 28 06:58:07 PM PDT 24
Peak memory 201692 kb
Host smart-1b45376f-7a6a-4b26-b44a-4640cc6a5244
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194527650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.4194527650
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3633546552
Short name T103
Test name
Test status
Simulation time 48325451054 ps
CPU time 86.72 seconds
Started Jun 28 06:58:04 PM PDT 24
Finished Jun 28 06:59:33 PM PDT 24
Peak memory 201836 kb
Host smart-d25e2e70-c39d-4f8b-87e1-5ff5cc3ce941
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633546552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3633546552
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.885071423
Short name T118
Test name
Test status
Simulation time 678723786 ps
CPU time 2.25 seconds
Started Jun 28 06:58:02 PM PDT 24
Finished Jun 28 06:58:06 PM PDT 24
Peak memory 201516 kb
Host smart-094c05b5-0bec-4cfd-ae2d-8fac4c480012
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885071423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.885071423
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4191971179
Short name T860
Test name
Test status
Simulation time 466877171 ps
CPU time 1.49 seconds
Started Jun 28 06:58:04 PM PDT 24
Finished Jun 28 06:58:08 PM PDT 24
Peak memory 201560 kb
Host smart-8f24524f-ef32-4844-99ce-c27122f73482
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191971179 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.4191971179
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.568295792
Short name T876
Test name
Test status
Simulation time 321062579 ps
CPU time 1.5 seconds
Started Jun 28 06:58:02 PM PDT 24
Finished Jun 28 06:58:06 PM PDT 24
Peak memory 201524 kb
Host smart-4a83caf5-6038-49d4-bf8c-b5f67071d7bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568295792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.568295792
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3855062677
Short name T863
Test name
Test status
Simulation time 390501982 ps
CPU time 0.89 seconds
Started Jun 28 06:58:03 PM PDT 24
Finished Jun 28 06:58:05 PM PDT 24
Peak memory 201436 kb
Host smart-8ffe700c-f2f8-4ca8-8932-929f7a31e6e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855062677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3855062677
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.417263861
Short name T117
Test name
Test status
Simulation time 2440710827 ps
CPU time 5.75 seconds
Started Jun 28 06:58:03 PM PDT 24
Finished Jun 28 06:58:10 PM PDT 24
Peak memory 201640 kb
Host smart-0ce6552d-83ce-46f9-b3f1-7124b1b992ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417263861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.417263861
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3412307736
Short name T907
Test name
Test status
Simulation time 463601974 ps
CPU time 1.48 seconds
Started Jun 28 06:57:51 PM PDT 24
Finished Jun 28 06:57:54 PM PDT 24
Peak memory 201788 kb
Host smart-8551a9c0-586a-4e2e-8321-539889c4e670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412307736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3412307736
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1608334737
Short name T58
Test name
Test status
Simulation time 4771850591 ps
CPU time 11.55 seconds
Started Jun 28 06:57:50 PM PDT 24
Finished Jun 28 06:58:03 PM PDT 24
Peak memory 201800 kb
Host smart-ce66bccf-779a-408a-972c-5a7dc2c2f509
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608334737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1608334737
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4054045262
Short name T882
Test name
Test status
Simulation time 517865231 ps
CPU time 0.77 seconds
Started Jun 28 06:59:23 PM PDT 24
Finished Jun 28 06:59:26 PM PDT 24
Peak memory 201416 kb
Host smart-a3ee2d99-e356-40b3-b0e0-cbe00cf02323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054045262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.4054045262
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3126816461
Short name T867
Test name
Test status
Simulation time 544662409 ps
CPU time 1.04 seconds
Started Jun 28 06:59:19 PM PDT 24
Finished Jun 28 06:59:22 PM PDT 24
Peak memory 201428 kb
Host smart-9eff773b-d99e-46df-be92-c84bc48d0cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126816461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3126816461
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.766454345
Short name T839
Test name
Test status
Simulation time 416919709 ps
CPU time 0.83 seconds
Started Jun 28 06:59:22 PM PDT 24
Finished Jun 28 06:59:24 PM PDT 24
Peak memory 201432 kb
Host smart-257e8391-89ac-4a91-91ff-78bf060102b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766454345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.766454345
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3552081899
Short name T893
Test name
Test status
Simulation time 542145274 ps
CPU time 0.96 seconds
Started Jun 28 06:59:23 PM PDT 24
Finished Jun 28 06:59:26 PM PDT 24
Peak memory 201412 kb
Host smart-0ce6307f-a208-4517-ab64-1f6e4ec4238f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552081899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3552081899
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.548927949
Short name T805
Test name
Test status
Simulation time 408735147 ps
CPU time 1.08 seconds
Started Jun 28 06:59:20 PM PDT 24
Finished Jun 28 06:59:23 PM PDT 24
Peak memory 201436 kb
Host smart-3e8b4be8-d4e4-4f07-a814-a99cac3a2a51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548927949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.548927949
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3957120488
Short name T908
Test name
Test status
Simulation time 496901783 ps
CPU time 0.96 seconds
Started Jun 28 06:59:22 PM PDT 24
Finished Jun 28 06:59:24 PM PDT 24
Peak memory 201208 kb
Host smart-afc82b2c-bf98-4b43-9d34-ec05fac272ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957120488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3957120488
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3707325439
Short name T845
Test name
Test status
Simulation time 514944236 ps
CPU time 1.8 seconds
Started Jun 28 06:59:20 PM PDT 24
Finished Jun 28 06:59:23 PM PDT 24
Peak memory 201600 kb
Host smart-038ba156-8fbc-4272-8a15-088002d456ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707325439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3707325439
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.643552937
Short name T848
Test name
Test status
Simulation time 428962978 ps
CPU time 1.67 seconds
Started Jun 28 06:59:21 PM PDT 24
Finished Jun 28 06:59:24 PM PDT 24
Peak memory 201440 kb
Host smart-bebc008f-dbab-4f47-a056-703bab87324d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643552937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.643552937
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3387887766
Short name T854
Test name
Test status
Simulation time 327535902 ps
CPU time 0.83 seconds
Started Jun 28 06:59:21 PM PDT 24
Finished Jun 28 06:59:24 PM PDT 24
Peak memory 201436 kb
Host smart-4b260238-c722-4003-b249-9f561a137f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387887766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3387887766
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1921479220
Short name T910
Test name
Test status
Simulation time 436695310 ps
CPU time 0.89 seconds
Started Jun 28 06:59:21 PM PDT 24
Finished Jun 28 06:59:24 PM PDT 24
Peak memory 201436 kb
Host smart-d5a6564e-ec86-4c9d-b8bc-c1b5df622a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921479220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1921479220
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.502343757
Short name T110
Test name
Test status
Simulation time 512896702 ps
CPU time 2.57 seconds
Started Jun 28 06:58:18 PM PDT 24
Finished Jun 28 06:58:24 PM PDT 24
Peak memory 201740 kb
Host smart-9d5db648-5823-4fa4-a7ae-d62a9cc6c1f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502343757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.502343757
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.846482506
Short name T52
Test name
Test status
Simulation time 52272471270 ps
CPU time 29.03 seconds
Started Jun 28 06:58:14 PM PDT 24
Finished Jun 28 06:58:45 PM PDT 24
Peak memory 201836 kb
Host smart-eb637abc-b6be-4bf4-b000-52a7aaab4a17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846482506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.846482506
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4175767450
Short name T109
Test name
Test status
Simulation time 665691071 ps
CPU time 2.23 seconds
Started Jun 28 06:58:04 PM PDT 24
Finished Jun 28 06:58:08 PM PDT 24
Peak memory 201512 kb
Host smart-43b20140-ca1a-42a1-ab24-0ca50dcde9af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175767450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.4175767450
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3974964073
Short name T85
Test name
Test status
Simulation time 553668849 ps
CPU time 2.09 seconds
Started Jun 28 06:58:18 PM PDT 24
Finished Jun 28 06:58:24 PM PDT 24
Peak memory 201512 kb
Host smart-4245f2d9-2385-4c31-a631-b13128ac1f09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974964073 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3974964073
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3350359580
Short name T894
Test name
Test status
Simulation time 414382988 ps
CPU time 1.82 seconds
Started Jun 28 06:58:19 PM PDT 24
Finished Jun 28 06:58:24 PM PDT 24
Peak memory 201516 kb
Host smart-0f0801be-e9dd-4c12-b860-255b890ac100
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350359580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3350359580
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1425693903
Short name T895
Test name
Test status
Simulation time 381484318 ps
CPU time 0.81 seconds
Started Jun 28 06:58:03 PM PDT 24
Finished Jun 28 06:58:06 PM PDT 24
Peak memory 201436 kb
Host smart-66216187-db3b-46b7-9c74-7fcfeba4ff06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425693903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1425693903
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1240938548
Short name T53
Test name
Test status
Simulation time 2619438533 ps
CPU time 7.11 seconds
Started Jun 28 06:58:17 PM PDT 24
Finished Jun 28 06:58:28 PM PDT 24
Peak memory 201636 kb
Host smart-a343a610-89ec-4cb0-8a08-c4b13c104670
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240938548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1240938548
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.792880169
Short name T881
Test name
Test status
Simulation time 462799328 ps
CPU time 1.62 seconds
Started Jun 28 06:58:05 PM PDT 24
Finished Jun 28 06:58:08 PM PDT 24
Peak memory 201784 kb
Host smart-ea452e2a-2344-492e-8d47-f629b1dea0e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792880169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.792880169
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2128454736
Short name T912
Test name
Test status
Simulation time 9045626886 ps
CPU time 3.64 seconds
Started Jun 28 06:58:04 PM PDT 24
Finished Jun 28 06:58:09 PM PDT 24
Peak memory 201820 kb
Host smart-35ffec82-2c12-49ff-bc24-97f1cd3eba01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128454736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2128454736
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2107990110
Short name T858
Test name
Test status
Simulation time 519544988 ps
CPU time 1.26 seconds
Started Jun 28 06:59:21 PM PDT 24
Finished Jun 28 06:59:24 PM PDT 24
Peak memory 201420 kb
Host smart-2a65622f-c13a-4ddd-a367-c6009d950e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107990110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2107990110
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2520037954
Short name T913
Test name
Test status
Simulation time 292694947 ps
CPU time 1.33 seconds
Started Jun 28 06:59:20 PM PDT 24
Finished Jun 28 06:59:23 PM PDT 24
Peak memory 201436 kb
Host smart-5012e066-f5fc-4180-bd92-54a5423f7492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520037954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2520037954
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2349476738
Short name T827
Test name
Test status
Simulation time 518121250 ps
CPU time 0.75 seconds
Started Jun 28 06:59:19 PM PDT 24
Finished Jun 28 06:59:22 PM PDT 24
Peak memory 201440 kb
Host smart-e49a0177-3ebc-4512-8aea-fc4ef36a6a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349476738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2349476738
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4051731608
Short name T850
Test name
Test status
Simulation time 475804406 ps
CPU time 1.71 seconds
Started Jun 28 06:59:21 PM PDT 24
Finished Jun 28 06:59:24 PM PDT 24
Peak memory 201440 kb
Host smart-60ea6c2f-d0a2-41bf-8caa-6a0d871d7eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051731608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.4051731608
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3514404635
Short name T861
Test name
Test status
Simulation time 428735303 ps
CPU time 1.64 seconds
Started Jun 28 06:59:22 PM PDT 24
Finished Jun 28 06:59:25 PM PDT 24
Peak memory 201208 kb
Host smart-efb47ae4-0208-400b-bdd1-ab9cda7685f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514404635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3514404635
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3229769895
Short name T834
Test name
Test status
Simulation time 558839641 ps
CPU time 1.04 seconds
Started Jun 28 06:59:22 PM PDT 24
Finished Jun 28 06:59:25 PM PDT 24
Peak memory 201440 kb
Host smart-1730456c-909c-4bb5-b2db-871989e2ba25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229769895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3229769895
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1887163872
Short name T838
Test name
Test status
Simulation time 343023794 ps
CPU time 0.85 seconds
Started Jun 28 06:59:33 PM PDT 24
Finished Jun 28 06:59:36 PM PDT 24
Peak memory 201436 kb
Host smart-cea9d528-f5dc-470f-951f-eb21cd5e4e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887163872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1887163872
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2602530244
Short name T890
Test name
Test status
Simulation time 480221126 ps
CPU time 0.92 seconds
Started Jun 28 06:59:34 PM PDT 24
Finished Jun 28 06:59:37 PM PDT 24
Peak memory 201600 kb
Host smart-ff1adc40-2dbd-415d-bc47-45f4c02ff396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602530244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2602530244
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2770290780
Short name T813
Test name
Test status
Simulation time 504615612 ps
CPU time 0.97 seconds
Started Jun 28 06:59:34 PM PDT 24
Finished Jun 28 06:59:37 PM PDT 24
Peak memory 201416 kb
Host smart-99313f55-6132-4906-bfb2-6310bf3031a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770290780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2770290780
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1307464669
Short name T808
Test name
Test status
Simulation time 525659173 ps
CPU time 0.96 seconds
Started Jun 28 06:59:31 PM PDT 24
Finished Jun 28 06:59:33 PM PDT 24
Peak memory 201372 kb
Host smart-50ff3f5b-9fa9-46c7-8362-f17c272a8103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307464669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1307464669
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1997916365
Short name T896
Test name
Test status
Simulation time 496661043 ps
CPU time 1.97 seconds
Started Jun 28 06:58:16 PM PDT 24
Finished Jun 28 06:58:19 PM PDT 24
Peak memory 201572 kb
Host smart-bc1e183a-1740-4163-a092-ef8fc4a7ce77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997916365 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1997916365
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2263850301
Short name T99
Test name
Test status
Simulation time 524190265 ps
CPU time 1.44 seconds
Started Jun 28 06:58:15 PM PDT 24
Finished Jun 28 06:58:18 PM PDT 24
Peak memory 201508 kb
Host smart-85f43e8c-9214-4c50-beab-1417e4411d4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263850301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2263850301
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3790618402
Short name T846
Test name
Test status
Simulation time 349120505 ps
CPU time 1.05 seconds
Started Jun 28 06:58:18 PM PDT 24
Finished Jun 28 06:58:23 PM PDT 24
Peak memory 201312 kb
Host smart-21e92125-2a4e-4cd9-8f49-561db5b5dea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790618402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3790618402
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3841283475
Short name T116
Test name
Test status
Simulation time 2800206297 ps
CPU time 11.92 seconds
Started Jun 28 06:58:16 PM PDT 24
Finished Jun 28 06:58:29 PM PDT 24
Peak memory 201640 kb
Host smart-45c8eb2c-ba40-41b8-b508-85aed2a2271f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841283475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3841283475
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2394527822
Short name T874
Test name
Test status
Simulation time 423955074 ps
CPU time 1.67 seconds
Started Jun 28 06:58:20 PM PDT 24
Finished Jun 28 06:58:24 PM PDT 24
Peak memory 201784 kb
Host smart-93421c86-0f77-4c0a-824c-6605940758e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394527822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2394527822
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.569533284
Short name T56
Test name
Test status
Simulation time 4397964247 ps
CPU time 12.22 seconds
Started Jun 28 06:58:17 PM PDT 24
Finished Jun 28 06:58:33 PM PDT 24
Peak memory 201800 kb
Host smart-9f970a20-9c4e-4254-b443-c365edcedfe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569533284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.569533284
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4219780430
Short name T821
Test name
Test status
Simulation time 466497690 ps
CPU time 1.85 seconds
Started Jun 28 06:58:16 PM PDT 24
Finished Jun 28 06:58:19 PM PDT 24
Peak memory 201576 kb
Host smart-31f078b0-ef78-4c11-b2db-6ab06d4bf8c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219780430 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.4219780430
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.196934167
Short name T114
Test name
Test status
Simulation time 558188521 ps
CPU time 1.37 seconds
Started Jun 28 06:58:20 PM PDT 24
Finished Jun 28 06:58:24 PM PDT 24
Peak memory 201516 kb
Host smart-e22b1b1f-01af-4868-894d-9cac7edfd259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196934167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.196934167
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3565323140
Short name T833
Test name
Test status
Simulation time 439086968 ps
CPU time 1.64 seconds
Started Jun 28 06:58:17 PM PDT 24
Finished Jun 28 06:58:23 PM PDT 24
Peak memory 201448 kb
Host smart-eec330ea-4e6f-46ee-9a82-efddb8acbcc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565323140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3565323140
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.359450711
Short name T911
Test name
Test status
Simulation time 4824650857 ps
CPU time 15.31 seconds
Started Jun 28 06:58:14 PM PDT 24
Finished Jun 28 06:58:31 PM PDT 24
Peak memory 201848 kb
Host smart-13a0056c-de32-4eba-a873-6c38858771c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359450711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.359450711
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2542347879
Short name T840
Test name
Test status
Simulation time 484367314 ps
CPU time 2.74 seconds
Started Jun 28 06:58:15 PM PDT 24
Finished Jun 28 06:58:20 PM PDT 24
Peak memory 217588 kb
Host smart-dadd0212-fc29-4039-ab85-b0841066205d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542347879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2542347879
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2825526596
Short name T71
Test name
Test status
Simulation time 8136927455 ps
CPU time 6.92 seconds
Started Jun 28 06:58:17 PM PDT 24
Finished Jun 28 06:58:26 PM PDT 24
Peak memory 201780 kb
Host smart-fcde3ee5-5eb3-43bd-9827-b2761cac57ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825526596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2825526596
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2795168023
Short name T812
Test name
Test status
Simulation time 532248915 ps
CPU time 1.42 seconds
Started Jun 28 06:58:19 PM PDT 24
Finished Jun 28 06:58:23 PM PDT 24
Peak memory 201576 kb
Host smart-71ff63d2-814c-4f2f-92ea-585c5335fbca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795168023 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2795168023
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2922781493
Short name T98
Test name
Test status
Simulation time 471996856 ps
CPU time 1.4 seconds
Started Jun 28 06:58:18 PM PDT 24
Finished Jun 28 06:58:23 PM PDT 24
Peak memory 201512 kb
Host smart-b17b96d2-0190-49dd-a338-f7fb53f12887
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922781493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2922781493
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2461566713
Short name T901
Test name
Test status
Simulation time 448952216 ps
CPU time 1.65 seconds
Started Jun 28 06:58:14 PM PDT 24
Finished Jun 28 06:58:17 PM PDT 24
Peak memory 201436 kb
Host smart-fe38b7d0-bd2a-4670-83f8-27bfbb666081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461566713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2461566713
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.590105664
Short name T906
Test name
Test status
Simulation time 2435161537 ps
CPU time 2.92 seconds
Started Jun 28 06:58:15 PM PDT 24
Finished Jun 28 06:58:19 PM PDT 24
Peak memory 201636 kb
Host smart-9f285529-17fb-4ab4-a5ca-94326318c3b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590105664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.590105664
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1115884745
Short name T825
Test name
Test status
Simulation time 485077999 ps
CPU time 1.52 seconds
Started Jun 28 06:58:15 PM PDT 24
Finished Jun 28 06:58:18 PM PDT 24
Peak memory 201732 kb
Host smart-b37669d1-33a5-4139-8fdc-cf29d7cc61e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115884745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1115884745
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2333599842
Short name T830
Test name
Test status
Simulation time 4703899155 ps
CPU time 3.91 seconds
Started Jun 28 06:58:17 PM PDT 24
Finished Jun 28 06:58:25 PM PDT 24
Peak memory 201852 kb
Host smart-32f16327-e82e-4917-9785-7ee421dd3d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333599842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2333599842
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1353774289
Short name T919
Test name
Test status
Simulation time 562435781 ps
CPU time 1.65 seconds
Started Jun 28 06:58:31 PM PDT 24
Finished Jun 28 06:58:34 PM PDT 24
Peak memory 201572 kb
Host smart-e54c2307-19b9-4a66-b91d-06c6283d8aa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353774289 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1353774289
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.877695565
Short name T871
Test name
Test status
Simulation time 472222199 ps
CPU time 1.01 seconds
Started Jun 28 06:58:32 PM PDT 24
Finished Jun 28 06:58:34 PM PDT 24
Peak memory 201516 kb
Host smart-14b8a154-35c3-4cd4-b5cc-e02f9ef37c39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877695565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.877695565
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4065389043
Short name T849
Test name
Test status
Simulation time 422532295 ps
CPU time 1.16 seconds
Started Jun 28 06:58:29 PM PDT 24
Finished Jun 28 06:58:31 PM PDT 24
Peak memory 201440 kb
Host smart-1e5f4d4e-a39b-494e-9ba9-cf23daea90ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065389043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.4065389043
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.623965106
Short name T886
Test name
Test status
Simulation time 5305375131 ps
CPU time 12.56 seconds
Started Jun 28 06:58:29 PM PDT 24
Finished Jun 28 06:58:42 PM PDT 24
Peak memory 201864 kb
Host smart-be0a22d3-8510-4a74-816e-5cc274f09ecc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623965106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.623965106
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.156936310
Short name T65
Test name
Test status
Simulation time 427466117 ps
CPU time 3.52 seconds
Started Jun 28 06:58:16 PM PDT 24
Finished Jun 28 06:58:21 PM PDT 24
Peak memory 201756 kb
Host smart-59547bc4-3e13-4724-a181-a62cd737a6af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156936310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.156936310
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.4291657806
Short name T364
Test name
Test status
Simulation time 4155800158 ps
CPU time 11.45 seconds
Started Jun 28 06:58:15 PM PDT 24
Finished Jun 28 06:58:28 PM PDT 24
Peak memory 201848 kb
Host smart-07827302-5328-45c7-ab92-acbde4877e72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291657806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.4291657806
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.103551490
Short name T822
Test name
Test status
Simulation time 684841611 ps
CPU time 1.21 seconds
Started Jun 28 06:58:48 PM PDT 24
Finished Jun 28 06:58:52 PM PDT 24
Peak memory 201572 kb
Host smart-cc2abd8c-523a-403d-8540-3cb6c570cdc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103551490 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.103551490
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2456649260
Short name T104
Test name
Test status
Simulation time 519658497 ps
CPU time 1.3 seconds
Started Jun 28 06:58:30 PM PDT 24
Finished Jun 28 06:58:33 PM PDT 24
Peak memory 201508 kb
Host smart-05152da2-136a-4337-99f6-c212c3bfdf8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456649260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2456649260
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.926151923
Short name T831
Test name
Test status
Simulation time 519021077 ps
CPU time 1.26 seconds
Started Jun 28 06:58:31 PM PDT 24
Finished Jun 28 06:58:34 PM PDT 24
Peak memory 201436 kb
Host smart-66408f64-b2d9-47e4-9a03-4bcca8ccdc02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926151923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.926151923
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2769367475
Short name T875
Test name
Test status
Simulation time 4472242834 ps
CPU time 17.62 seconds
Started Jun 28 06:58:32 PM PDT 24
Finished Jun 28 06:58:51 PM PDT 24
Peak memory 201848 kb
Host smart-49a72c98-af75-4641-9ce3-58760df43fe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769367475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2769367475
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.10502999
Short name T820
Test name
Test status
Simulation time 4464179334 ps
CPU time 3.74 seconds
Started Jun 28 06:58:31 PM PDT 24
Finished Jun 28 06:58:37 PM PDT 24
Peak memory 201852 kb
Host smart-c1c4281c-8851-4e17-9d07-f3d9e5a33b53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10502999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg
_err.10502999
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1824449150
Short name T586
Test name
Test status
Simulation time 526171298 ps
CPU time 1.46 seconds
Started Jun 28 06:59:44 PM PDT 24
Finished Jun 28 06:59:47 PM PDT 24
Peak memory 201540 kb
Host smart-41fed022-d9b1-4436-a8c2-c95ed48f0bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824449150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1824449150
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2432039551
Short name T357
Test name
Test status
Simulation time 327627123580 ps
CPU time 193.91 seconds
Started Jun 28 06:59:34 PM PDT 24
Finished Jun 28 07:02:50 PM PDT 24
Peak memory 201884 kb
Host smart-1c047eac-6f8a-4b13-9b87-64235f1650e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432039551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2432039551
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1878995550
Short name T714
Test name
Test status
Simulation time 159831836835 ps
CPU time 183.59 seconds
Started Jun 28 06:59:34 PM PDT 24
Finished Jun 28 07:02:40 PM PDT 24
Peak memory 201844 kb
Host smart-b398c151-59b3-4ab4-9d9d-deadd1d91d16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878995550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1878995550
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.245949712
Short name T153
Test name
Test status
Simulation time 174321608905 ps
CPU time 206.61 seconds
Started Jun 28 06:59:37 PM PDT 24
Finished Jun 28 07:03:05 PM PDT 24
Peak memory 201928 kb
Host smart-382db76e-b08b-4f93-869c-2db9ae781604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245949712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.245949712
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3545472380
Short name T215
Test name
Test status
Simulation time 334291287272 ps
CPU time 717.96 seconds
Started Jun 28 06:59:33 PM PDT 24
Finished Jun 28 07:11:34 PM PDT 24
Peak memory 201868 kb
Host smart-b7f78131-4b71-4b7a-9ea6-5f0344a956c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545472380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3545472380
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3364394564
Short name T347
Test name
Test status
Simulation time 363207093518 ps
CPU time 569.21 seconds
Started Jun 28 06:59:31 PM PDT 24
Finished Jun 28 07:09:02 PM PDT 24
Peak memory 201904 kb
Host smart-83779d5a-2b23-4ce4-b481-d14a2d15a7d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364394564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3364394564
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.99056371
Short name T218
Test name
Test status
Simulation time 123121630043 ps
CPU time 632.15 seconds
Started Jun 28 06:59:32 PM PDT 24
Finished Jun 28 07:10:06 PM PDT 24
Peak memory 202272 kb
Host smart-31da1f14-f7c2-4a78-9467-66fe20e739a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99056371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.99056371
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.880610069
Short name T200
Test name
Test status
Simulation time 42998078506 ps
CPU time 91.7 seconds
Started Jun 28 06:59:32 PM PDT 24
Finished Jun 28 07:01:05 PM PDT 24
Peak memory 201680 kb
Host smart-51ab4769-5847-4a06-a354-bd83830bb51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880610069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.880610069
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2494420818
Short name T601
Test name
Test status
Simulation time 5211435192 ps
CPU time 11.95 seconds
Started Jun 28 06:59:33 PM PDT 24
Finished Jun 28 06:59:47 PM PDT 24
Peak memory 201680 kb
Host smart-d1aa4343-b3e0-407b-ac23-eeb0d101ea3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494420818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2494420818
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.71695534
Short name T63
Test name
Test status
Simulation time 7941045903 ps
CPU time 8.84 seconds
Started Jun 28 06:59:42 PM PDT 24
Finished Jun 28 06:59:52 PM PDT 24
Peak memory 218240 kb
Host smart-c822b1a8-2d17-478b-b416-3c846a277528
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71695534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.71695534
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1694474195
Short name T394
Test name
Test status
Simulation time 5854003769 ps
CPU time 14.1 seconds
Started Jun 28 06:59:33 PM PDT 24
Finished Jun 28 06:59:49 PM PDT 24
Peak memory 201684 kb
Host smart-190acb8c-b41a-4d9f-845d-8c164147964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694474195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1694474195
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2793350758
Short name T92
Test name
Test status
Simulation time 499360523011 ps
CPU time 285.35 seconds
Started Jun 28 06:59:42 PM PDT 24
Finished Jun 28 07:04:28 PM PDT 24
Peak memory 201808 kb
Host smart-003cdfde-39e9-4ac1-b37d-ffe5349b2ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793350758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2793350758
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2235870683
Short name T506
Test name
Test status
Simulation time 327579430740 ps
CPU time 300.08 seconds
Started Jun 28 06:59:43 PM PDT 24
Finished Jun 28 07:04:46 PM PDT 24
Peak memory 201864 kb
Host smart-c0526082-32db-46cd-be8c-d042bf38a44b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235870683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2235870683
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1383949942
Short name T502
Test name
Test status
Simulation time 325020754608 ps
CPU time 371.72 seconds
Started Jun 28 06:59:44 PM PDT 24
Finished Jun 28 07:05:58 PM PDT 24
Peak memory 201884 kb
Host smart-d9d844ba-97fd-4164-af48-d33ebe4ecd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383949942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1383949942
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.4118516081
Short name T423
Test name
Test status
Simulation time 166658988984 ps
CPU time 398.41 seconds
Started Jun 28 06:59:43 PM PDT 24
Finished Jun 28 07:06:24 PM PDT 24
Peak memory 201928 kb
Host smart-725520bc-9b33-4ee8-8c32-2746b3e78924
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118516081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.4118516081
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3329700078
Short name T691
Test name
Test status
Simulation time 599461625281 ps
CPU time 368.76 seconds
Started Jun 28 06:59:43 PM PDT 24
Finished Jun 28 07:05:54 PM PDT 24
Peak memory 201840 kb
Host smart-5a4e3b51-a9f1-4501-a015-67d978bf15ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329700078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3329700078
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1115912810
Short name T607
Test name
Test status
Simulation time 78959310016 ps
CPU time 254.49 seconds
Started Jun 28 06:59:42 PM PDT 24
Finished Jun 28 07:03:59 PM PDT 24
Peak memory 202184 kb
Host smart-5af04dea-763a-442d-bda7-13b8d179918f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115912810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1115912810
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.240627858
Short name T405
Test name
Test status
Simulation time 38685643710 ps
CPU time 21.23 seconds
Started Jun 28 06:59:42 PM PDT 24
Finished Jun 28 07:00:04 PM PDT 24
Peak memory 201672 kb
Host smart-4c27895b-652a-4f8b-9b00-02741884bd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240627858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.240627858
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3746328201
Short name T464
Test name
Test status
Simulation time 5211361600 ps
CPU time 3.65 seconds
Started Jun 28 06:59:42 PM PDT 24
Finished Jun 28 06:59:47 PM PDT 24
Peak memory 201672 kb
Host smart-f8cc093d-ad0c-4d1b-8d37-d581eec5e2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746328201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3746328201
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3583092621
Short name T403
Test name
Test status
Simulation time 6185144633 ps
CPU time 4.8 seconds
Started Jun 28 06:59:42 PM PDT 24
Finished Jun 28 06:59:49 PM PDT 24
Peak memory 201684 kb
Host smart-0c66d95c-dce4-4a3d-9d26-6bc1f163d5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583092621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3583092621
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2471844384
Short name T272
Test name
Test status
Simulation time 277055452924 ps
CPU time 937.84 seconds
Started Jun 28 06:59:42 PM PDT 24
Finished Jun 28 07:15:22 PM PDT 24
Peak memory 218528 kb
Host smart-725abc0e-e90f-450d-88f1-4633b1f0af15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471844384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2471844384
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2446229263
Short name T471
Test name
Test status
Simulation time 290366765 ps
CPU time 0.99 seconds
Started Jun 28 07:01:25 PM PDT 24
Finished Jun 28 07:01:28 PM PDT 24
Peak memory 201620 kb
Host smart-5e52ab43-b71c-476a-97d0-89627ee1f78d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446229263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2446229263
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2607811173
Short name T205
Test name
Test status
Simulation time 340699204391 ps
CPU time 374.87 seconds
Started Jun 28 07:01:26 PM PDT 24
Finished Jun 28 07:07:43 PM PDT 24
Peak memory 201852 kb
Host smart-652ebdca-2a50-45a5-a9c1-5c51c8d364e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607811173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2607811173
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1419360662
Short name T137
Test name
Test status
Simulation time 337150071690 ps
CPU time 701.92 seconds
Started Jun 28 07:01:16 PM PDT 24
Finished Jun 28 07:13:01 PM PDT 24
Peak memory 201856 kb
Host smart-d761a0a0-df9b-4218-983b-a992a8fafa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419360662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1419360662
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.376667848
Short name T801
Test name
Test status
Simulation time 321967188102 ps
CPU time 190.21 seconds
Started Jun 28 07:01:25 PM PDT 24
Finished Jun 28 07:04:38 PM PDT 24
Peak memory 201868 kb
Host smart-c96d26e9-3174-4574-9a4e-22ea0a130bea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=376667848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.376667848
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2238432938
Short name T310
Test name
Test status
Simulation time 332070374902 ps
CPU time 742.83 seconds
Started Jun 28 07:01:17 PM PDT 24
Finished Jun 28 07:13:44 PM PDT 24
Peak memory 201892 kb
Host smart-81b97a6b-61bd-4cd8-b818-42c746b97379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238432938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2238432938
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2302508047
Short name T96
Test name
Test status
Simulation time 494181751177 ps
CPU time 1186.81 seconds
Started Jun 28 07:01:15 PM PDT 24
Finished Jun 28 07:21:06 PM PDT 24
Peak memory 201876 kb
Host smart-3f7ccf28-0191-4ac1-8fab-dcbbdbbe10b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302508047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2302508047
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3934329719
Short name T688
Test name
Test status
Simulation time 193570132543 ps
CPU time 413.42 seconds
Started Jun 28 07:01:26 PM PDT 24
Finished Jun 28 07:08:22 PM PDT 24
Peak memory 201856 kb
Host smart-4236bed1-54dd-4e30-8a28-71e6a53010b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934329719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3934329719
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3008743353
Short name T365
Test name
Test status
Simulation time 106837245322 ps
CPU time 532.09 seconds
Started Jun 28 07:01:26 PM PDT 24
Finished Jun 28 07:10:21 PM PDT 24
Peak memory 202244 kb
Host smart-04456d60-ae64-4b10-9acb-21eb83a33eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008743353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3008743353
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3205482491
Short name T559
Test name
Test status
Simulation time 47221868490 ps
CPU time 100.26 seconds
Started Jun 28 07:01:25 PM PDT 24
Finished Jun 28 07:03:08 PM PDT 24
Peak memory 201688 kb
Host smart-5c2680ac-bb99-4d98-9a70-4329ec7a9d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205482491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3205482491
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1819317295
Short name T768
Test name
Test status
Simulation time 4061583354 ps
CPU time 2.93 seconds
Started Jun 28 07:01:25 PM PDT 24
Finished Jun 28 07:01:31 PM PDT 24
Peak memory 201684 kb
Host smart-b26396db-669c-47a3-b70f-7beef2a09454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819317295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1819317295
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.417286635
Short name T715
Test name
Test status
Simulation time 5556938907 ps
CPU time 3.67 seconds
Started Jun 28 07:01:18 PM PDT 24
Finished Jun 28 07:01:25 PM PDT 24
Peak memory 201664 kb
Host smart-5b1cf2bb-6af6-4a0d-93b8-5e10a7650c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417286635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.417286635
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2461323730
Short name T736
Test name
Test status
Simulation time 342381693209 ps
CPU time 489.63 seconds
Started Jun 28 07:01:26 PM PDT 24
Finished Jun 28 07:09:38 PM PDT 24
Peak memory 201924 kb
Host smart-fd94556d-731b-4910-850a-930f2b20cbac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461323730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2461323730
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.4290701707
Short name T39
Test name
Test status
Simulation time 23097473650 ps
CPU time 42.74 seconds
Started Jun 28 07:01:26 PM PDT 24
Finished Jun 28 07:02:12 PM PDT 24
Peak memory 202324 kb
Host smart-bb912b0f-6d37-4ea4-964c-ef5e85bc2434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290701707 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.4290701707
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.91551096
Short name T401
Test name
Test status
Simulation time 335048912 ps
CPU time 0.85 seconds
Started Jun 28 07:01:48 PM PDT 24
Finished Jun 28 07:01:50 PM PDT 24
Peak memory 201632 kb
Host smart-a5d50404-f372-4b14-b0d3-8fa42ff5d2b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91551096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.91551096
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2145729988
Short name T135
Test name
Test status
Simulation time 528952403122 ps
CPU time 1223.03 seconds
Started Jun 28 07:01:36 PM PDT 24
Finished Jun 28 07:22:00 PM PDT 24
Peak memory 201872 kb
Host smart-04bbb1d7-8277-4f38-9b54-a4e043baf56f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145729988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2145729988
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2577104205
Short name T724
Test name
Test status
Simulation time 516073358805 ps
CPU time 291.73 seconds
Started Jun 28 07:01:35 PM PDT 24
Finished Jun 28 07:06:28 PM PDT 24
Peak memory 201948 kb
Host smart-fba099f0-c714-46ef-9bdc-9d7c54dfa8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577104205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2577104205
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3639216920
Short name T794
Test name
Test status
Simulation time 167633727915 ps
CPU time 61.61 seconds
Started Jun 28 07:01:25 PM PDT 24
Finished Jun 28 07:02:29 PM PDT 24
Peak memory 201844 kb
Host smart-ab9d22fd-dade-4979-836a-c5f16fa73dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639216920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3639216920
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.870444506
Short name T147
Test name
Test status
Simulation time 339451787732 ps
CPU time 182.17 seconds
Started Jun 28 07:01:25 PM PDT 24
Finished Jun 28 07:04:30 PM PDT 24
Peak memory 201840 kb
Host smart-9b4671b2-0d35-43f1-aaa6-6b8d81c948e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=870444506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.870444506
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.419149481
Short name T284
Test name
Test status
Simulation time 323840101514 ps
CPU time 185.96 seconds
Started Jun 28 07:01:25 PM PDT 24
Finished Jun 28 07:04:34 PM PDT 24
Peak memory 201960 kb
Host smart-2d4d1a92-4517-48b8-98fc-108b9d37ff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419149481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.419149481
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3165804345
Short name T743
Test name
Test status
Simulation time 163456555641 ps
CPU time 96.52 seconds
Started Jun 28 07:01:24 PM PDT 24
Finished Jun 28 07:03:03 PM PDT 24
Peak memory 201836 kb
Host smart-b7f7991e-fc7a-4189-8c35-9fb500cd3ea0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165804345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3165804345
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.958458456
Short name T208
Test name
Test status
Simulation time 367527980123 ps
CPU time 398.52 seconds
Started Jun 28 07:01:37 PM PDT 24
Finished Jun 28 07:08:16 PM PDT 24
Peak memory 201876 kb
Host smart-e7514cfb-23bf-44eb-9515-9049b025dcfa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958458456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.958458456
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1076630820
Short name T528
Test name
Test status
Simulation time 605833218533 ps
CPU time 736.39 seconds
Started Jun 28 07:01:38 PM PDT 24
Finished Jun 28 07:13:56 PM PDT 24
Peak memory 201840 kb
Host smart-8aeb8a38-eda8-41fd-870b-ed78acc4d09d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076630820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1076630820
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2124738047
Short name T410
Test name
Test status
Simulation time 128865134302 ps
CPU time 533.35 seconds
Started Jun 28 07:01:48 PM PDT 24
Finished Jun 28 07:10:44 PM PDT 24
Peak memory 202192 kb
Host smart-c4d8f038-f99a-40e5-b67e-cc1e391eeced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124738047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2124738047
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2142990096
Short name T380
Test name
Test status
Simulation time 39208092805 ps
CPU time 28.96 seconds
Started Jun 28 07:01:36 PM PDT 24
Finished Jun 28 07:02:06 PM PDT 24
Peak memory 201668 kb
Host smart-9561b942-d502-4ab6-a86c-85faf204d262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142990096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2142990096
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3245000562
Short name T149
Test name
Test status
Simulation time 4053587270 ps
CPU time 2.46 seconds
Started Jun 28 07:01:36 PM PDT 24
Finished Jun 28 07:01:39 PM PDT 24
Peak memory 201684 kb
Host smart-d49dfe23-0b9c-4984-8565-4bbd9284c465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245000562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3245000562
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2187469600
Short name T732
Test name
Test status
Simulation time 5880171865 ps
CPU time 2.46 seconds
Started Jun 28 07:01:25 PM PDT 24
Finished Jun 28 07:01:30 PM PDT 24
Peak memory 201676 kb
Host smart-f0e957a3-2fb1-4d27-8698-62a47ed7c37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187469600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2187469600
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3070829588
Short name T420
Test name
Test status
Simulation time 127749311856 ps
CPU time 652.93 seconds
Started Jun 28 07:01:53 PM PDT 24
Finished Jun 28 07:12:48 PM PDT 24
Peak memory 202236 kb
Host smart-0cab1961-f77a-4da0-b99a-95d1360ae15b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070829588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3070829588
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1455749539
Short name T400
Test name
Test status
Simulation time 328365169 ps
CPU time 1.35 seconds
Started Jun 28 07:02:11 PM PDT 24
Finished Jun 28 07:02:14 PM PDT 24
Peak memory 201628 kb
Host smart-8c1aa1eb-823c-4f2f-9281-ae4fea353820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455749539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1455749539
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2134392007
Short name T359
Test name
Test status
Simulation time 166992635589 ps
CPU time 40.92 seconds
Started Jun 28 07:02:03 PM PDT 24
Finished Jun 28 07:02:47 PM PDT 24
Peak memory 201888 kb
Host smart-d36f1fda-86d8-4fad-a961-17d912cb2ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134392007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2134392007
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.31240053
Short name T393
Test name
Test status
Simulation time 502051982243 ps
CPU time 1170.98 seconds
Started Jun 28 07:01:48 PM PDT 24
Finished Jun 28 07:21:21 PM PDT 24
Peak memory 201788 kb
Host smart-0594ff8f-49f6-4ac8-9636-8904d4ae34f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=31240053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt
_fixed.31240053
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2323342956
Short name T27
Test name
Test status
Simulation time 328321424446 ps
CPU time 429.69 seconds
Started Jun 28 07:01:48 PM PDT 24
Finished Jun 28 07:08:59 PM PDT 24
Peak memory 201808 kb
Host smart-b919c364-560a-4783-a6b1-96c87fdae3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323342956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2323342956
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2870870779
Short name T484
Test name
Test status
Simulation time 329638794194 ps
CPU time 441.58 seconds
Started Jun 28 07:01:53 PM PDT 24
Finished Jun 28 07:09:17 PM PDT 24
Peak memory 201848 kb
Host smart-8a9f1365-6dee-491c-8a90-1a97e6687c42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870870779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2870870779
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2827658604
Short name T626
Test name
Test status
Simulation time 394793003740 ps
CPU time 764.17 seconds
Started Jun 28 07:01:59 PM PDT 24
Finished Jun 28 07:14:46 PM PDT 24
Peak memory 201856 kb
Host smart-35647a92-a531-4614-936a-b9b495530983
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827658604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2827658604
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.4150355500
Short name T472
Test name
Test status
Simulation time 205773438197 ps
CPU time 118.84 seconds
Started Jun 28 07:01:58 PM PDT 24
Finished Jun 28 07:04:00 PM PDT 24
Peak memory 201852 kb
Host smart-27e81aa0-94ab-46bf-84fa-7ef06d4ac1bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150355500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.4150355500
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2190082864
Short name T413
Test name
Test status
Simulation time 110760414746 ps
CPU time 351.82 seconds
Started Jun 28 07:01:59 PM PDT 24
Finished Jun 28 07:07:54 PM PDT 24
Peak memory 202192 kb
Host smart-39c9f154-dec3-4248-aa4f-042d0f9ef3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190082864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2190082864
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3348754280
Short name T377
Test name
Test status
Simulation time 42415688290 ps
CPU time 14.2 seconds
Started Jun 28 07:01:59 PM PDT 24
Finished Jun 28 07:02:16 PM PDT 24
Peak memory 201684 kb
Host smart-878bd48c-821a-47fb-8483-83139660b8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348754280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3348754280
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.188275653
Short name T606
Test name
Test status
Simulation time 4122174606 ps
CPU time 3.23 seconds
Started Jun 28 07:02:00 PM PDT 24
Finished Jun 28 07:02:07 PM PDT 24
Peak memory 201688 kb
Host smart-a9bd1b2b-40ba-491e-800e-4418b0f24163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188275653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.188275653
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2384678426
Short name T44
Test name
Test status
Simulation time 5770388550 ps
CPU time 14.05 seconds
Started Jun 28 07:01:47 PM PDT 24
Finished Jun 28 07:02:02 PM PDT 24
Peak memory 201664 kb
Host smart-48c0a1f3-448a-4405-8f74-0b2298721809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384678426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2384678426
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1534448989
Short name T435
Test name
Test status
Simulation time 318217136 ps
CPU time 1 seconds
Started Jun 28 07:02:23 PM PDT 24
Finished Jun 28 07:02:25 PM PDT 24
Peak memory 201632 kb
Host smart-af264e29-fdb2-4a09-b40e-7b7dfddb4016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534448989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1534448989
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1359762828
Short name T154
Test name
Test status
Simulation time 502337734448 ps
CPU time 518.49 seconds
Started Jun 28 07:02:22 PM PDT 24
Finished Jun 28 07:11:02 PM PDT 24
Peak memory 201832 kb
Host smart-c1cd7731-1396-402f-920b-f7aada8ddd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359762828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1359762828
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.816968202
Short name T588
Test name
Test status
Simulation time 166717669890 ps
CPU time 35.9 seconds
Started Jun 28 07:02:10 PM PDT 24
Finished Jun 28 07:02:47 PM PDT 24
Peak memory 201880 kb
Host smart-cd42dbc8-16ab-4e62-a115-2b4c637254f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816968202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.816968202
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2871368238
Short name T561
Test name
Test status
Simulation time 325501124807 ps
CPU time 186.42 seconds
Started Jun 28 07:02:10 PM PDT 24
Finished Jun 28 07:05:18 PM PDT 24
Peak memory 201840 kb
Host smart-ff49aad4-4817-4160-931b-3bb328f4c133
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871368238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2871368238
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3401129924
Short name T705
Test name
Test status
Simulation time 163137048742 ps
CPU time 231.54 seconds
Started Jun 28 07:02:14 PM PDT 24
Finished Jun 28 07:06:08 PM PDT 24
Peak memory 201884 kb
Host smart-50646ccc-c7c6-4f5f-aa24-3acefe9c66f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401129924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3401129924
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3579899444
Short name T665
Test name
Test status
Simulation time 165106418612 ps
CPU time 387.35 seconds
Started Jun 28 07:02:09 PM PDT 24
Finished Jun 28 07:08:39 PM PDT 24
Peak memory 201904 kb
Host smart-1588f71e-df58-405c-8590-9e82d4222fbd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579899444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3579899444
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2941824483
Short name T124
Test name
Test status
Simulation time 617713827518 ps
CPU time 171.77 seconds
Started Jun 28 07:02:09 PM PDT 24
Finished Jun 28 07:05:03 PM PDT 24
Peak memory 201816 kb
Host smart-11a0fd9d-e8fe-4506-ba82-f643b1659c21
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941824483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2941824483
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3159939822
Short name T190
Test name
Test status
Simulation time 121686774786 ps
CPU time 377.81 seconds
Started Jun 28 07:02:23 PM PDT 24
Finished Jun 28 07:08:42 PM PDT 24
Peak memory 202192 kb
Host smart-acef5268-6dfa-4c2c-915a-e3b6381c6674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159939822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3159939822
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1593671784
Short name T540
Test name
Test status
Simulation time 32283591608 ps
CPU time 73.35 seconds
Started Jun 28 07:02:21 PM PDT 24
Finished Jun 28 07:03:37 PM PDT 24
Peak memory 201704 kb
Host smart-019c5d23-d1fa-4785-b6bf-d9e383ffdca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593671784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1593671784
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.296126849
Short name T428
Test name
Test status
Simulation time 4916907020 ps
CPU time 3.57 seconds
Started Jun 28 07:02:22 PM PDT 24
Finished Jun 28 07:02:27 PM PDT 24
Peak memory 201700 kb
Host smart-ccc38126-d2af-4ca0-8b3d-46a32d83bf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296126849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.296126849
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.45625685
Short name T796
Test name
Test status
Simulation time 5694586240 ps
CPU time 7.32 seconds
Started Jun 28 07:02:14 PM PDT 24
Finished Jun 28 07:02:23 PM PDT 24
Peak memory 201676 kb
Host smart-ed8cbce9-1d7c-4e2e-8b96-67a33e731a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45625685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.45625685
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.634083181
Short name T130
Test name
Test status
Simulation time 169879107531 ps
CPU time 262.85 seconds
Started Jun 28 07:02:21 PM PDT 24
Finished Jun 28 07:06:46 PM PDT 24
Peak memory 201872 kb
Host smart-a8f11fdc-8603-42ca-8b08-e575b4fe63a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634083181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
634083181
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4117577117
Short name T21
Test name
Test status
Simulation time 361320604289 ps
CPU time 390.24 seconds
Started Jun 28 07:02:22 PM PDT 24
Finished Jun 28 07:08:54 PM PDT 24
Peak memory 210520 kb
Host smart-e9471935-4a17-4836-afe6-51691b9d80ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117577117 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.4117577117
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.111246656
Short name T761
Test name
Test status
Simulation time 402903706 ps
CPU time 1.07 seconds
Started Jun 28 07:02:45 PM PDT 24
Finished Jun 28 07:02:47 PM PDT 24
Peak memory 201628 kb
Host smart-0aab88f7-3058-45b1-b848-f6b201cecfbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111246656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.111246656
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2753795087
Short name T262
Test name
Test status
Simulation time 530417052876 ps
CPU time 1117.2 seconds
Started Jun 28 07:02:34 PM PDT 24
Finished Jun 28 07:21:13 PM PDT 24
Peak memory 201856 kb
Host smart-014f545e-b220-4762-af36-f92514b92049
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753795087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2753795087
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3547133195
Short name T350
Test name
Test status
Simulation time 166335627973 ps
CPU time 374.36 seconds
Started Jun 28 07:02:34 PM PDT 24
Finished Jun 28 07:08:49 PM PDT 24
Peak memory 201964 kb
Host smart-a4063834-9c0b-4e25-a91d-cef9efdaf003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547133195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3547133195
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3958148221
Short name T685
Test name
Test status
Simulation time 336425676811 ps
CPU time 203.84 seconds
Started Jun 28 07:02:21 PM PDT 24
Finished Jun 28 07:05:47 PM PDT 24
Peak memory 201880 kb
Host smart-cf976561-ca76-4252-84a6-c8e359aef376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958148221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3958148221
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1959828052
Short name T244
Test name
Test status
Simulation time 159942145217 ps
CPU time 99.95 seconds
Started Jun 28 07:02:34 PM PDT 24
Finished Jun 28 07:04:15 PM PDT 24
Peak memory 201884 kb
Host smart-25de0aa0-b28d-4754-9d08-8c77410e0906
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959828052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1959828052
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.527005749
Short name T667
Test name
Test status
Simulation time 323390838768 ps
CPU time 696.46 seconds
Started Jun 28 07:02:23 PM PDT 24
Finished Jun 28 07:14:01 PM PDT 24
Peak memory 201896 kb
Host smart-514e69e2-b9e0-4857-8f32-92240ded47c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527005749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.527005749
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.709878615
Short name T431
Test name
Test status
Simulation time 494183244660 ps
CPU time 507.68 seconds
Started Jun 28 07:02:21 PM PDT 24
Finished Jun 28 07:10:51 PM PDT 24
Peak memory 201872 kb
Host smart-1af15308-f8df-41e1-8740-d02e9664c510
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=709878615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.709878615
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1388931031
Short name T181
Test name
Test status
Simulation time 381959214459 ps
CPU time 230.93 seconds
Started Jun 28 07:02:36 PM PDT 24
Finished Jun 28 07:06:28 PM PDT 24
Peak memory 201904 kb
Host smart-fc38d730-693c-4f7d-a84d-eb9d0f09b610
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388931031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1388931031
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.623213970
Short name T524
Test name
Test status
Simulation time 617138459065 ps
CPU time 399.11 seconds
Started Jun 28 07:02:34 PM PDT 24
Finished Jun 28 07:09:14 PM PDT 24
Peak memory 201808 kb
Host smart-9c9a22e3-fdfa-4cee-a3d7-ef6894c96231
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623213970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.623213970
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1871916719
Short name T548
Test name
Test status
Simulation time 85315873843 ps
CPU time 431.63 seconds
Started Jun 28 07:02:34 PM PDT 24
Finished Jun 28 07:09:47 PM PDT 24
Peak memory 202252 kb
Host smart-4218eaef-7149-46a1-a7b7-8ce47f2fb98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871916719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1871916719
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.4160974853
Short name T538
Test name
Test status
Simulation time 42043201885 ps
CPU time 90.81 seconds
Started Jun 28 07:02:34 PM PDT 24
Finished Jun 28 07:04:06 PM PDT 24
Peak memory 201692 kb
Host smart-a561feef-a84a-4ff4-897d-ceb1fb45f616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160974853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4160974853
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3092829021
Short name T599
Test name
Test status
Simulation time 4922132151 ps
CPU time 12.22 seconds
Started Jun 28 07:02:35 PM PDT 24
Finished Jun 28 07:02:49 PM PDT 24
Peak memory 201696 kb
Host smart-5bd641cf-17e2-4e7f-bd57-e290682d8b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092829021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3092829021
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3748011370
Short name T641
Test name
Test status
Simulation time 5961596161 ps
CPU time 14.46 seconds
Started Jun 28 07:02:21 PM PDT 24
Finished Jun 28 07:02:38 PM PDT 24
Peak memory 201680 kb
Host smart-27b9ec29-6198-4550-bfef-c6a84677dfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748011370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3748011370
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2032263131
Short name T33
Test name
Test status
Simulation time 19794666772 ps
CPU time 46.55 seconds
Started Jun 28 07:02:45 PM PDT 24
Finished Jun 28 07:03:33 PM PDT 24
Peak memory 201840 kb
Host smart-d08efb67-1391-4cc9-97bb-51c5d2ce44f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032263131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2032263131
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3818402521
Short name T35
Test name
Test status
Simulation time 1736382801587 ps
CPU time 591.68 seconds
Started Jun 28 07:02:45 PM PDT 24
Finished Jun 28 07:12:37 PM PDT 24
Peak memory 211544 kb
Host smart-e96049e7-c746-4c91-9354-4a95662cd61d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818402521 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3818402521
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1819405670
Short name T643
Test name
Test status
Simulation time 291540697 ps
CPU time 1.13 seconds
Started Jun 28 07:03:13 PM PDT 24
Finished Jun 28 07:03:15 PM PDT 24
Peak memory 201632 kb
Host smart-f9715cef-9ae7-44d2-9e9a-3adbab10fd32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819405670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1819405670
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3265520144
Short name T294
Test name
Test status
Simulation time 167754266507 ps
CPU time 346.79 seconds
Started Jun 28 07:02:56 PM PDT 24
Finished Jun 28 07:08:44 PM PDT 24
Peak memory 201856 kb
Host smart-e2620dc1-2aef-416d-93d3-735cf7413fd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265520144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3265520144
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1082215858
Short name T206
Test name
Test status
Simulation time 542893770521 ps
CPU time 1277.94 seconds
Started Jun 28 07:02:55 PM PDT 24
Finished Jun 28 07:24:14 PM PDT 24
Peak memory 201864 kb
Host smart-474838b3-e255-460b-a075-65b09e42c241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082215858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1082215858
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.4201463286
Short name T432
Test name
Test status
Simulation time 160323476527 ps
CPU time 351.82 seconds
Started Jun 28 07:02:56 PM PDT 24
Finished Jun 28 07:08:49 PM PDT 24
Peak memory 201848 kb
Host smart-3525bf97-87d8-4b1a-9eaf-f6ef0261c915
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201463286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.4201463286
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.686830371
Short name T497
Test name
Test status
Simulation time 165651867945 ps
CPU time 300.03 seconds
Started Jun 28 07:02:44 PM PDT 24
Finished Jun 28 07:07:45 PM PDT 24
Peak memory 201880 kb
Host smart-23d8645e-7cfc-4794-9d4c-62a97fe6093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686830371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.686830371
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3883693195
Short name T551
Test name
Test status
Simulation time 495000044315 ps
CPU time 1139.51 seconds
Started Jun 28 07:02:45 PM PDT 24
Finished Jun 28 07:21:45 PM PDT 24
Peak memory 201864 kb
Host smart-9a465ba0-8b58-48d5-8e48-b12576c1d8bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883693195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3883693195
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3007538139
Short name T754
Test name
Test status
Simulation time 335769429792 ps
CPU time 804.11 seconds
Started Jun 28 07:02:57 PM PDT 24
Finished Jun 28 07:16:22 PM PDT 24
Peak memory 201960 kb
Host smart-6a10debc-ad28-4381-90ca-b5bb7bab2cd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007538139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3007538139
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1514920121
Short name T798
Test name
Test status
Simulation time 202450461374 ps
CPU time 145.18 seconds
Started Jun 28 07:02:55 PM PDT 24
Finished Jun 28 07:05:22 PM PDT 24
Peak memory 201872 kb
Host smart-5b9e2beb-d087-45ed-8bfe-0eee5f2a5fca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514920121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1514920121
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.4257538018
Short name T439
Test name
Test status
Simulation time 70117540096 ps
CPU time 234.32 seconds
Started Jun 28 07:03:14 PM PDT 24
Finished Jun 28 07:07:09 PM PDT 24
Peak memory 202392 kb
Host smart-069a4c8e-ab8c-4410-a15a-7b3a6b488bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257538018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.4257538018
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3346095613
Short name T612
Test name
Test status
Simulation time 28674429481 ps
CPU time 16.71 seconds
Started Jun 28 07:02:53 PM PDT 24
Finished Jun 28 07:03:10 PM PDT 24
Peak memory 201676 kb
Host smart-de1d68a4-3018-489c-90ae-a0eabf3f2c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346095613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3346095613
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1660540908
Short name T578
Test name
Test status
Simulation time 2932995553 ps
CPU time 2.38 seconds
Started Jun 28 07:02:54 PM PDT 24
Finished Jun 28 07:02:57 PM PDT 24
Peak memory 201688 kb
Host smart-cb030499-89ed-44c4-adca-65ba1d2aa14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660540908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1660540908
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.472592899
Short name T766
Test name
Test status
Simulation time 5947284175 ps
CPU time 15.39 seconds
Started Jun 28 07:02:45 PM PDT 24
Finished Jun 28 07:03:02 PM PDT 24
Peak memory 201696 kb
Host smart-66d94c40-1754-49a8-8534-0715dde685e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472592899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.472592899
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2418185870
Short name T591
Test name
Test status
Simulation time 421647102200 ps
CPU time 421.42 seconds
Started Jun 28 07:03:13 PM PDT 24
Finished Jun 28 07:10:16 PM PDT 24
Peak memory 218540 kb
Host smart-510ff18e-f19d-4c8f-b731-907722a4f035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418185870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2418185870
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3603151559
Short name T627
Test name
Test status
Simulation time 76439692813 ps
CPU time 160.19 seconds
Started Jun 28 07:03:12 PM PDT 24
Finished Jun 28 07:05:53 PM PDT 24
Peak memory 210532 kb
Host smart-5fc4c92f-2aa6-4470-bcbc-3c38ff1e0be2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603151559 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3603151559
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2377834014
Short name T433
Test name
Test status
Simulation time 333542653 ps
CPU time 1.44 seconds
Started Jun 28 07:03:36 PM PDT 24
Finished Jun 28 07:03:38 PM PDT 24
Peak memory 201632 kb
Host smart-0230adde-94dd-4700-978f-9fa327a88044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377834014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2377834014
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2352731693
Short name T123
Test name
Test status
Simulation time 331548317245 ps
CPU time 177.85 seconds
Started Jun 28 07:03:24 PM PDT 24
Finished Jun 28 07:06:24 PM PDT 24
Peak memory 201872 kb
Host smart-f961b601-6efc-40ab-ba19-9396062d3a58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352731693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2352731693
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1195927302
Short name T719
Test name
Test status
Simulation time 335141849584 ps
CPU time 480.91 seconds
Started Jun 28 07:03:25 PM PDT 24
Finished Jun 28 07:11:28 PM PDT 24
Peak memory 201892 kb
Host smart-fe2241f3-d727-4c06-aa36-94bd9519555e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195927302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1195927302
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2795705909
Short name T487
Test name
Test status
Simulation time 326181078968 ps
CPU time 109.52 seconds
Started Jun 28 07:03:26 PM PDT 24
Finished Jun 28 07:05:16 PM PDT 24
Peak memory 201856 kb
Host smart-1df25875-9bae-4967-b177-1d46c3cf8a91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795705909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2795705909
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.821874201
Short name T41
Test name
Test status
Simulation time 168223221711 ps
CPU time 67.09 seconds
Started Jun 28 07:03:24 PM PDT 24
Finished Jun 28 07:04:32 PM PDT 24
Peak memory 201892 kb
Host smart-d818a526-935e-42ab-b3bb-961e945fe10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821874201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.821874201
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2909100515
Short name T574
Test name
Test status
Simulation time 329737988817 ps
CPU time 762.24 seconds
Started Jun 28 07:03:24 PM PDT 24
Finished Jun 28 07:16:08 PM PDT 24
Peak memory 201852 kb
Host smart-e25793c3-5657-4993-9dba-659aec112189
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909100515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2909100515
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2122436032
Short name T159
Test name
Test status
Simulation time 531628123961 ps
CPU time 1257.52 seconds
Started Jun 28 07:03:24 PM PDT 24
Finished Jun 28 07:24:23 PM PDT 24
Peak memory 201872 kb
Host smart-0c09569b-3287-4996-9f5f-d5ebe19a9afa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122436032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2122436032
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3282114351
Short name T402
Test name
Test status
Simulation time 200128265508 ps
CPU time 166.38 seconds
Started Jun 28 07:03:24 PM PDT 24
Finished Jun 28 07:06:12 PM PDT 24
Peak memory 201800 kb
Host smart-772f0f7c-92d3-4d0d-89e5-20da2d7639f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282114351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3282114351
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3889607500
Short name T529
Test name
Test status
Simulation time 71341589815 ps
CPU time 283.47 seconds
Started Jun 28 07:03:37 PM PDT 24
Finished Jun 28 07:08:21 PM PDT 24
Peak memory 202196 kb
Host smart-e7dcd282-8475-4301-806b-70218bdbf12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889607500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3889607500
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.613109419
Short name T476
Test name
Test status
Simulation time 37820009190 ps
CPU time 41.52 seconds
Started Jun 28 07:03:36 PM PDT 24
Finished Jun 28 07:04:19 PM PDT 24
Peak memory 201688 kb
Host smart-190cc97c-5a82-4758-9947-526f87715815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613109419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.613109419
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.4165403829
Short name T372
Test name
Test status
Simulation time 3752974228 ps
CPU time 2.05 seconds
Started Jun 28 07:03:24 PM PDT 24
Finished Jun 28 07:03:28 PM PDT 24
Peak memory 201688 kb
Host smart-96c0fa8e-cbde-4cf5-9b0e-bd4e069285c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165403829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.4165403829
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1359173679
Short name T737
Test name
Test status
Simulation time 5941576120 ps
CPU time 13.66 seconds
Started Jun 28 07:03:12 PM PDT 24
Finished Jun 28 07:03:26 PM PDT 24
Peak memory 201676 kb
Host smart-02ed7356-36e5-4acc-b06f-9623f89503f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359173679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1359173679
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3529143263
Short name T139
Test name
Test status
Simulation time 404946485720 ps
CPU time 374.65 seconds
Started Jun 28 07:03:34 PM PDT 24
Finished Jun 28 07:09:50 PM PDT 24
Peak memory 201864 kb
Host smart-0ddfbb3f-7c1b-4e2e-85ac-0b72527d308f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529143263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3529143263
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1473815471
Short name T462
Test name
Test status
Simulation time 487395528 ps
CPU time 0.84 seconds
Started Jun 28 07:03:50 PM PDT 24
Finished Jun 28 07:03:53 PM PDT 24
Peak memory 201632 kb
Host smart-a64ea7ca-3561-451a-8e93-ce823df703aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473815471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1473815471
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1022864012
Short name T249
Test name
Test status
Simulation time 358697366672 ps
CPU time 179.52 seconds
Started Jun 28 07:03:50 PM PDT 24
Finished Jun 28 07:06:52 PM PDT 24
Peak memory 201924 kb
Host smart-81e0aab0-7084-45dd-8b8c-ae39e0e73ed1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022864012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1022864012
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3351797374
Short name T600
Test name
Test status
Simulation time 166527129144 ps
CPU time 91.43 seconds
Started Jun 28 07:03:49 PM PDT 24
Finished Jun 28 07:05:23 PM PDT 24
Peak memory 201892 kb
Host smart-70ad451e-c535-467f-8d96-9eff7a8fb328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351797374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3351797374
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1550206066
Short name T692
Test name
Test status
Simulation time 330090069522 ps
CPU time 729.25 seconds
Started Jun 28 07:03:36 PM PDT 24
Finished Jun 28 07:15:46 PM PDT 24
Peak memory 201824 kb
Host smart-2e2db464-d1f1-47e6-9625-3f91b0063ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550206066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1550206066
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2508195248
Short name T501
Test name
Test status
Simulation time 331288680599 ps
CPU time 209.7 seconds
Started Jun 28 07:03:36 PM PDT 24
Finished Jun 28 07:07:07 PM PDT 24
Peak memory 201844 kb
Host smart-e2504978-4dea-47f8-810f-8c7b1617079a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508195248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2508195248
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.934126146
Short name T584
Test name
Test status
Simulation time 158475306127 ps
CPU time 199.67 seconds
Started Jun 28 07:03:36 PM PDT 24
Finished Jun 28 07:06:56 PM PDT 24
Peak memory 201912 kb
Host smart-c42791d3-9e30-41be-86cc-f655191ab8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934126146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.934126146
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1770284681
Short name T397
Test name
Test status
Simulation time 160478050032 ps
CPU time 98.03 seconds
Started Jun 28 07:03:36 PM PDT 24
Finished Jun 28 07:05:15 PM PDT 24
Peak memory 201868 kb
Host smart-c82010b1-c933-4c35-8ae9-21c32e28a668
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770284681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1770284681
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1664387884
Short name T264
Test name
Test status
Simulation time 165776143786 ps
CPU time 27.28 seconds
Started Jun 28 07:03:50 PM PDT 24
Finished Jun 28 07:04:19 PM PDT 24
Peak memory 201964 kb
Host smart-5a7b6aa1-a0c4-4d3b-a188-a8515fb58c7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664387884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1664387884
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2578745952
Short name T618
Test name
Test status
Simulation time 604626274775 ps
CPU time 356.87 seconds
Started Jun 28 07:03:49 PM PDT 24
Finished Jun 28 07:09:48 PM PDT 24
Peak memory 201860 kb
Host smart-a97f9989-f245-4979-b230-9fbe517d1113
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578745952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2578745952
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1335097498
Short name T366
Test name
Test status
Simulation time 67585398604 ps
CPU time 359.58 seconds
Started Jun 28 07:03:49 PM PDT 24
Finished Jun 28 07:09:51 PM PDT 24
Peak memory 202256 kb
Host smart-ef94fc52-426c-4d7d-8f0e-b097165c00aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335097498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1335097498
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.4288380719
Short name T198
Test name
Test status
Simulation time 41018367546 ps
CPU time 94.3 seconds
Started Jun 28 07:03:49 PM PDT 24
Finished Jun 28 07:05:26 PM PDT 24
Peak memory 201676 kb
Host smart-9a118039-18f9-4895-8330-fab7973ec526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288380719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.4288380719
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3910120773
Short name T621
Test name
Test status
Simulation time 2817823022 ps
CPU time 4.03 seconds
Started Jun 28 07:03:49 PM PDT 24
Finished Jun 28 07:03:55 PM PDT 24
Peak memory 201680 kb
Host smart-3addf4bc-9875-4914-952d-b83527a07aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910120773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3910120773
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1300056735
Short name T94
Test name
Test status
Simulation time 6069550405 ps
CPU time 4.4 seconds
Started Jun 28 07:03:36 PM PDT 24
Finished Jun 28 07:03:41 PM PDT 24
Peak memory 201676 kb
Host smart-c287cc67-4099-4f9b-8da4-b69179180dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300056735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1300056735
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.856471992
Short name T537
Test name
Test status
Simulation time 195889856733 ps
CPU time 211.07 seconds
Started Jun 28 07:03:51 PM PDT 24
Finished Jun 28 07:07:24 PM PDT 24
Peak memory 201872 kb
Host smart-a645205c-516f-475e-a881-4e7b8fd4fabe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856471992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
856471992
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2760312287
Short name T295
Test name
Test status
Simulation time 148786522926 ps
CPU time 159.89 seconds
Started Jun 28 07:03:49 PM PDT 24
Finished Jun 28 07:06:31 PM PDT 24
Peak memory 210132 kb
Host smart-547c686e-b365-45d5-97ef-183b34708b13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760312287 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2760312287
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2067107627
Short name T661
Test name
Test status
Simulation time 302675782 ps
CPU time 1.31 seconds
Started Jun 28 07:04:00 PM PDT 24
Finished Jun 28 07:04:03 PM PDT 24
Peak memory 201632 kb
Host smart-b67e4704-99ab-4fba-b08e-9d089d6d6fba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067107627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2067107627
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3256284452
Short name T248
Test name
Test status
Simulation time 178915278406 ps
CPU time 63.05 seconds
Started Jun 28 07:04:02 PM PDT 24
Finished Jun 28 07:05:07 PM PDT 24
Peak memory 201928 kb
Host smart-a5c6b9d2-3d3c-4a19-bc05-aeab10013786
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256284452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3256284452
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2055757591
Short name T169
Test name
Test status
Simulation time 484758000400 ps
CPU time 302.4 seconds
Started Jun 28 07:04:03 PM PDT 24
Finished Jun 28 07:09:07 PM PDT 24
Peak memory 201892 kb
Host smart-5d58f603-8c65-4c7f-a091-3fac432270c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055757591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2055757591
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2230220519
Short name T687
Test name
Test status
Simulation time 338963074348 ps
CPU time 122.68 seconds
Started Jun 28 07:04:07 PM PDT 24
Finished Jun 28 07:06:11 PM PDT 24
Peak memory 201860 kb
Host smart-c73873bd-fc74-4a51-8cf6-b21ee8bcbd11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230220519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2230220519
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.4153893084
Short name T583
Test name
Test status
Simulation time 163640075212 ps
CPU time 108.55 seconds
Started Jun 28 07:04:01 PM PDT 24
Finished Jun 28 07:05:51 PM PDT 24
Peak memory 201952 kb
Host smart-80a4f1f8-737e-4d78-9829-4faf08d9b637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153893084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4153893084
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2616305972
Short name T709
Test name
Test status
Simulation time 496571910907 ps
CPU time 530.05 seconds
Started Jun 28 07:04:07 PM PDT 24
Finished Jun 28 07:12:59 PM PDT 24
Peak memory 201844 kb
Host smart-9186d7f1-9576-43b7-bda5-3eb133c3a1c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616305972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2616305972
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1836871400
Short name T351
Test name
Test status
Simulation time 177483085509 ps
CPU time 425.76 seconds
Started Jun 28 07:04:01 PM PDT 24
Finished Jun 28 07:11:09 PM PDT 24
Peak memory 201936 kb
Host smart-ad15e984-d58d-4317-ac9f-545d5b486da8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836871400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1836871400
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.597924304
Short name T650
Test name
Test status
Simulation time 588768269432 ps
CPU time 656.84 seconds
Started Jun 28 07:04:10 PM PDT 24
Finished Jun 28 07:15:08 PM PDT 24
Peak memory 201856 kb
Host smart-cb3199c9-7210-4596-a531-d253164b8227
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597924304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.597924304
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2515083948
Short name T672
Test name
Test status
Simulation time 115947481971 ps
CPU time 344.41 seconds
Started Jun 28 07:04:02 PM PDT 24
Finished Jun 28 07:09:48 PM PDT 24
Peak memory 202208 kb
Host smart-0e1b2b1d-65a3-43f8-ba1b-3e7b049983e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515083948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2515083948
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.908107963
Short name T427
Test name
Test status
Simulation time 29256145870 ps
CPU time 17.82 seconds
Started Jun 28 07:04:00 PM PDT 24
Finished Jun 28 07:04:19 PM PDT 24
Peak memory 201656 kb
Host smart-c8d54dcf-9ae1-4265-a046-9b92d42feb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908107963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.908107963
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1245433783
Short name T793
Test name
Test status
Simulation time 4738682371 ps
CPU time 5.89 seconds
Started Jun 28 07:04:02 PM PDT 24
Finished Jun 28 07:04:09 PM PDT 24
Peak memory 201688 kb
Host smart-9d3b1500-d512-421e-83f9-05e04dec92f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245433783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1245433783
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1488238550
Short name T543
Test name
Test status
Simulation time 5997272135 ps
CPU time 14.4 seconds
Started Jun 28 07:04:01 PM PDT 24
Finished Jun 28 07:04:17 PM PDT 24
Peak memory 201676 kb
Host smart-215a3dc0-aad2-458f-bf8c-905debf2b4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488238550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1488238550
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1602990206
Short name T645
Test name
Test status
Simulation time 330877393057 ps
CPU time 203.35 seconds
Started Jun 28 07:04:02 PM PDT 24
Finished Jun 28 07:07:27 PM PDT 24
Peak memory 201856 kb
Host smart-ee2865ce-e6d6-41b9-b448-175581590ae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602990206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1602990206
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2565183547
Short name T678
Test name
Test status
Simulation time 24585073655 ps
CPU time 105.96 seconds
Started Jun 28 07:04:00 PM PDT 24
Finished Jun 28 07:05:47 PM PDT 24
Peak memory 210588 kb
Host smart-127e53e0-502a-4a9e-ba1c-a6475a9d7c31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565183547 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2565183547
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1562384572
Short name T659
Test name
Test status
Simulation time 484970643 ps
CPU time 0.8 seconds
Started Jun 28 07:04:34 PM PDT 24
Finished Jun 28 07:04:36 PM PDT 24
Peak memory 201624 kb
Host smart-efc7f43b-49ca-4259-bb00-869afe1fd166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562384572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1562384572
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2262804948
Short name T647
Test name
Test status
Simulation time 168950094162 ps
CPU time 378.46 seconds
Started Jun 28 07:04:24 PM PDT 24
Finished Jun 28 07:10:44 PM PDT 24
Peak memory 201876 kb
Host smart-89516d13-f4d3-4d99-be88-cb84407125fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262804948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2262804948
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2223952351
Short name T470
Test name
Test status
Simulation time 164941775212 ps
CPU time 386.22 seconds
Started Jun 28 07:04:13 PM PDT 24
Finished Jun 28 07:10:41 PM PDT 24
Peak memory 201968 kb
Host smart-476d64de-9775-440b-b110-817692eee4c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223952351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2223952351
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.29896425
Short name T763
Test name
Test status
Simulation time 164426011684 ps
CPU time 63.39 seconds
Started Jun 28 07:04:12 PM PDT 24
Finished Jun 28 07:05:16 PM PDT 24
Peak memory 201868 kb
Host smart-27c7de23-3bd9-4493-a238-9effe5773164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29896425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.29896425
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.194455555
Short name T681
Test name
Test status
Simulation time 498185366744 ps
CPU time 263.78 seconds
Started Jun 28 07:04:11 PM PDT 24
Finished Jun 28 07:08:36 PM PDT 24
Peak memory 201852 kb
Host smart-776b7b44-e03f-48d7-a678-283e0d1e53be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=194455555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.194455555
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1306450201
Short name T257
Test name
Test status
Simulation time 173397445287 ps
CPU time 95.78 seconds
Started Jun 28 07:04:11 PM PDT 24
Finished Jun 28 07:05:48 PM PDT 24
Peak memory 201948 kb
Host smart-2299c211-5653-4652-b52f-eb2a5a9c1c59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306450201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1306450201
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.609196809
Short name T448
Test name
Test status
Simulation time 614711344588 ps
CPU time 1459.46 seconds
Started Jun 28 07:04:29 PM PDT 24
Finished Jun 28 07:28:50 PM PDT 24
Peak memory 201856 kb
Host smart-86d13d93-db30-407e-84ac-72261d4f675e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609196809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.609196809
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2525334166
Short name T49
Test name
Test status
Simulation time 87717161625 ps
CPU time 455.03 seconds
Started Jun 28 07:04:26 PM PDT 24
Finished Jun 28 07:12:02 PM PDT 24
Peak memory 202252 kb
Host smart-bf8a3959-5d45-4e28-9c56-8558d20e684c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525334166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2525334166
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2029746773
Short name T748
Test name
Test status
Simulation time 35808118189 ps
CPU time 19.83 seconds
Started Jun 28 07:04:24 PM PDT 24
Finished Jun 28 07:04:45 PM PDT 24
Peak memory 201680 kb
Host smart-e90e0b9d-4e97-4590-af25-d011d874cc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029746773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2029746773
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1802426241
Short name T765
Test name
Test status
Simulation time 5789063239 ps
CPU time 2.13 seconds
Started Jun 28 07:04:29 PM PDT 24
Finished Jun 28 07:04:33 PM PDT 24
Peak memory 201676 kb
Host smart-c7e081c5-bfa6-4012-96ca-6ad9e891ed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802426241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1802426241
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3398171807
Short name T566
Test name
Test status
Simulation time 5954037315 ps
CPU time 14.96 seconds
Started Jun 28 07:04:13 PM PDT 24
Finished Jun 28 07:04:29 PM PDT 24
Peak memory 201684 kb
Host smart-ac4bbbda-1358-4808-b2ee-448e0a06a735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398171807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3398171807
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1708751975
Short name T360
Test name
Test status
Simulation time 336424245892 ps
CPU time 179.33 seconds
Started Jun 28 07:04:34 PM PDT 24
Finished Jun 28 07:07:35 PM PDT 24
Peak memory 201928 kb
Host smart-841eda32-50bc-4cce-8304-831e62e16e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708751975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1708751975
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3820050576
Short name T642
Test name
Test status
Simulation time 288506902 ps
CPU time 1.3 seconds
Started Jun 28 06:59:54 PM PDT 24
Finished Jun 28 06:59:58 PM PDT 24
Peak memory 201628 kb
Host smart-f3b4180f-eb8b-457f-a56f-19941440ee71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820050576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3820050576
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.454400916
Short name T550
Test name
Test status
Simulation time 331373113520 ps
CPU time 382.11 seconds
Started Jun 28 06:59:53 PM PDT 24
Finished Jun 28 07:06:17 PM PDT 24
Peak memory 201864 kb
Host smart-e8668459-ba9e-4caf-bee5-3402f58ccbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454400916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.454400916
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3417747666
Short name T701
Test name
Test status
Simulation time 494131705361 ps
CPU time 590.13 seconds
Started Jun 28 06:59:55 PM PDT 24
Finished Jun 28 07:09:47 PM PDT 24
Peak memory 201800 kb
Host smart-0c1c5cc6-6a77-4f0b-a4de-c236f26dca04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417747666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3417747666
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.392984181
Short name T163
Test name
Test status
Simulation time 480856300076 ps
CPU time 325.85 seconds
Started Jun 28 06:59:42 PM PDT 24
Finished Jun 28 07:05:10 PM PDT 24
Peak memory 201896 kb
Host smart-50fe9b05-61c8-4b66-aeff-4efc949317f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392984181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.392984181
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.944720600
Short name T466
Test name
Test status
Simulation time 325864037991 ps
CPU time 341.22 seconds
Started Jun 28 06:59:42 PM PDT 24
Finished Jun 28 07:05:25 PM PDT 24
Peak memory 201872 kb
Host smart-8c505345-e35f-4d9c-bbef-a9f135556282
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=944720600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.944720600
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3329891423
Short name T788
Test name
Test status
Simulation time 385946231033 ps
CPU time 410.38 seconds
Started Jun 28 06:59:54 PM PDT 24
Finished Jun 28 07:06:46 PM PDT 24
Peak memory 201888 kb
Host smart-fecaa1cb-21ae-41b8-b5ab-f2fb2d04092a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329891423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3329891423
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2810923762
Short name T575
Test name
Test status
Simulation time 208409809007 ps
CPU time 122.88 seconds
Started Jun 28 06:59:53 PM PDT 24
Finished Jun 28 07:01:58 PM PDT 24
Peak memory 201868 kb
Host smart-e27d2d1d-750d-4a76-8e66-f61bb2e0db65
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810923762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2810923762
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3331916364
Short name T791
Test name
Test status
Simulation time 115811393123 ps
CPU time 589.63 seconds
Started Jun 28 06:59:53 PM PDT 24
Finished Jun 28 07:09:44 PM PDT 24
Peak memory 202204 kb
Host smart-ff8e8298-e784-4928-889e-debef2398c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331916364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3331916364
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.4266253214
Short name T587
Test name
Test status
Simulation time 32023363482 ps
CPU time 73.89 seconds
Started Jun 28 06:59:55 PM PDT 24
Finished Jun 28 07:01:11 PM PDT 24
Peak memory 201684 kb
Host smart-d3dd98b2-b1bf-448b-8dd0-8a6a36e92f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266253214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.4266253214
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2435139385
Short name T480
Test name
Test status
Simulation time 3327431527 ps
CPU time 2.19 seconds
Started Jun 28 06:59:54 PM PDT 24
Finished Jun 28 06:59:59 PM PDT 24
Peak memory 201688 kb
Host smart-8f0508a9-368f-45b0-bfcc-a825ad2c8873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435139385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2435139385
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1074875345
Short name T74
Test name
Test status
Simulation time 8219962326 ps
CPU time 5.44 seconds
Started Jun 28 06:59:54 PM PDT 24
Finished Jun 28 07:00:02 PM PDT 24
Peak memory 218236 kb
Host smart-ce56242d-bf04-4729-b79e-047a68177b6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074875345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1074875345
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2761139359
Short name T604
Test name
Test status
Simulation time 5897447811 ps
CPU time 13.12 seconds
Started Jun 28 06:59:44 PM PDT 24
Finished Jun 28 06:59:59 PM PDT 24
Peak memory 201684 kb
Host smart-a8be1fc2-cfb6-4a04-b959-99e755f4ea60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761139359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2761139359
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2967979403
Short name T711
Test name
Test status
Simulation time 27910493219 ps
CPU time 77.04 seconds
Started Jun 28 06:59:54 PM PDT 24
Finished Jun 28 07:01:13 PM PDT 24
Peak memory 218188 kb
Host smart-4f82afba-4cb9-474a-bcaa-728eefcd2b10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967979403 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2967979403
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3163953192
Short name T474
Test name
Test status
Simulation time 404463239 ps
CPU time 1.08 seconds
Started Jun 28 07:04:56 PM PDT 24
Finished Jun 28 07:04:59 PM PDT 24
Peak memory 201604 kb
Host smart-6b0066bd-ce3f-4ee9-aeea-0aa5aaf5ee1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163953192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3163953192
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2352490522
Short name T696
Test name
Test status
Simulation time 458630108480 ps
CPU time 1059.11 seconds
Started Jun 28 07:04:46 PM PDT 24
Finished Jun 28 07:22:27 PM PDT 24
Peak memory 201860 kb
Host smart-03e53b15-7f97-46b1-aaed-26798e007f80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352490522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2352490522
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1614725453
Short name T323
Test name
Test status
Simulation time 339352166582 ps
CPU time 782.02 seconds
Started Jun 28 07:04:47 PM PDT 24
Finished Jun 28 07:17:51 PM PDT 24
Peak memory 201948 kb
Host smart-86837c92-6f4e-4189-a84d-7f592a387710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614725453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1614725453
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3447592406
Short name T172
Test name
Test status
Simulation time 327529683152 ps
CPU time 177.4 seconds
Started Jun 28 07:04:35 PM PDT 24
Finished Jun 28 07:07:34 PM PDT 24
Peak memory 201880 kb
Host smart-0f897805-b149-43fd-a143-64a416833877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447592406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3447592406
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1687476112
Short name T628
Test name
Test status
Simulation time 162749945266 ps
CPU time 26.25 seconds
Started Jun 28 07:04:34 PM PDT 24
Finished Jun 28 07:05:01 PM PDT 24
Peak memory 201856 kb
Host smart-e5135f04-1d65-4380-8338-34bd49c8e364
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687476112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1687476112
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3192446188
Short name T734
Test name
Test status
Simulation time 168156070384 ps
CPU time 174.73 seconds
Started Jun 28 07:04:37 PM PDT 24
Finished Jun 28 07:07:33 PM PDT 24
Peak memory 201884 kb
Host smart-c097bd06-7083-4a85-8fbc-59baab6cc92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192446188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3192446188
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3823882804
Short name T24
Test name
Test status
Simulation time 490375400589 ps
CPU time 584.97 seconds
Started Jun 28 07:04:38 PM PDT 24
Finished Jun 28 07:14:24 PM PDT 24
Peak memory 201848 kb
Host smart-c3c5eac2-282d-42cf-8e37-ae137b1bf01f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823882804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3823882804
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1353871209
Short name T317
Test name
Test status
Simulation time 183476622267 ps
CPU time 431.46 seconds
Started Jun 28 07:04:34 PM PDT 24
Finished Jun 28 07:11:46 PM PDT 24
Peak memory 201956 kb
Host smart-5564d5ce-f11c-49e1-9482-38d1cfd994d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353871209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1353871209
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2414895333
Short name T767
Test name
Test status
Simulation time 209563818788 ps
CPU time 471.87 seconds
Started Jun 28 07:04:34 PM PDT 24
Finished Jun 28 07:12:27 PM PDT 24
Peak memory 201864 kb
Host smart-5cf5e040-e3dc-4d5c-972a-4fe7a2a6c821
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414895333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2414895333
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1081073870
Short name T371
Test name
Test status
Simulation time 94080743231 ps
CPU time 333.06 seconds
Started Jun 28 07:04:45 PM PDT 24
Finished Jun 28 07:10:19 PM PDT 24
Peak memory 202272 kb
Host smart-d9a67e91-5a59-45c1-a84a-033cb39716b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081073870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1081073870
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3792308637
Short name T404
Test name
Test status
Simulation time 44874636466 ps
CPU time 13.07 seconds
Started Jun 28 07:04:45 PM PDT 24
Finished Jun 28 07:04:59 PM PDT 24
Peak memory 201680 kb
Host smart-8d09413d-2900-4846-b925-a77e51c16517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792308637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3792308637
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2808114303
Short name T558
Test name
Test status
Simulation time 4496036042 ps
CPU time 3.24 seconds
Started Jun 28 07:04:46 PM PDT 24
Finished Jun 28 07:04:50 PM PDT 24
Peak memory 201688 kb
Host smart-e35d3891-2b61-4ce9-a9bb-0f052cf3def5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808114303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2808114303
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3613219670
Short name T613
Test name
Test status
Simulation time 6008957061 ps
CPU time 13.41 seconds
Started Jun 28 07:04:34 PM PDT 24
Finished Jun 28 07:04:49 PM PDT 24
Peak memory 201648 kb
Host smart-7b7a5e1b-169a-45a1-8fb7-0849947f18a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613219670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3613219670
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2195688055
Short name T31
Test name
Test status
Simulation time 187922553455 ps
CPU time 423.28 seconds
Started Jun 28 07:04:57 PM PDT 24
Finished Jun 28 07:12:01 PM PDT 24
Peak memory 201880 kb
Host smart-9ea44a34-38c0-4f35-ba45-af9c83a759e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195688055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2195688055
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2338196095
Short name T617
Test name
Test status
Simulation time 33824649749 ps
CPU time 103.98 seconds
Started Jun 28 07:04:56 PM PDT 24
Finished Jun 28 07:06:41 PM PDT 24
Peak memory 210600 kb
Host smart-063bbfe7-ce3d-40af-8e4d-9f9b5f1ce45a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338196095 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2338196095
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2551494144
Short name T637
Test name
Test status
Simulation time 489522717 ps
CPU time 1.73 seconds
Started Jun 28 07:05:27 PM PDT 24
Finished Jun 28 07:05:31 PM PDT 24
Peak memory 201632 kb
Host smart-28a3c228-5283-45a7-b1e5-0f7cd6859ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551494144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2551494144
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1627936690
Short name T207
Test name
Test status
Simulation time 329344146776 ps
CPU time 650.33 seconds
Started Jun 28 07:05:07 PM PDT 24
Finished Jun 28 07:15:59 PM PDT 24
Peak memory 201876 kb
Host smart-21ba8a37-0e70-40be-96af-4bfc40d3ec5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627936690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1627936690
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3585361630
Short name T787
Test name
Test status
Simulation time 437485260137 ps
CPU time 482.13 seconds
Started Jun 28 07:05:07 PM PDT 24
Finished Jun 28 07:13:11 PM PDT 24
Peak memory 201888 kb
Host smart-b24057fe-3c86-4b1c-a5ee-a66d91f5e50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585361630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3585361630
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2700466305
Short name T160
Test name
Test status
Simulation time 496448723092 ps
CPU time 81.79 seconds
Started Jun 28 07:05:07 PM PDT 24
Finished Jun 28 07:06:31 PM PDT 24
Peak memory 201880 kb
Host smart-dda7696f-78fd-45ed-beef-658ac389b043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700466305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2700466305
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3171119368
Short name T580
Test name
Test status
Simulation time 491528927650 ps
CPU time 1131.92 seconds
Started Jun 28 07:05:06 PM PDT 24
Finished Jun 28 07:24:00 PM PDT 24
Peak memory 201840 kb
Host smart-3e5db64c-94bb-4c59-b54c-7034a749d332
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171119368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3171119368
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2251997392
Short name T495
Test name
Test status
Simulation time 159550880595 ps
CPU time 100.16 seconds
Started Jun 28 07:05:07 PM PDT 24
Finished Jun 28 07:06:49 PM PDT 24
Peak memory 201764 kb
Host smart-c4039fea-e931-4f42-b462-a6e65b0bcdca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251997392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2251997392
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2402738333
Short name T556
Test name
Test status
Simulation time 171065601911 ps
CPU time 252.11 seconds
Started Jun 28 07:05:06 PM PDT 24
Finished Jun 28 07:09:20 PM PDT 24
Peak memory 201932 kb
Host smart-457e3be3-13fd-485e-8d64-fb1ea142a980
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402738333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2402738333
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.397732172
Short name T441
Test name
Test status
Simulation time 394778287334 ps
CPU time 919.82 seconds
Started Jun 28 07:05:07 PM PDT 24
Finished Jun 28 07:20:29 PM PDT 24
Peak memory 201864 kb
Host smart-3b1711d3-7ef9-4337-9101-3d2d2c8f6c86
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397732172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.397732172
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1275264225
Short name T79
Test name
Test status
Simulation time 117610426146 ps
CPU time 599.62 seconds
Started Jun 28 07:05:28 PM PDT 24
Finished Jun 28 07:15:29 PM PDT 24
Peak memory 202192 kb
Host smart-71489ec3-dd0e-4154-a85c-6f4d53ff2a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275264225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1275264225
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3637081628
Short name T729
Test name
Test status
Simulation time 39229134644 ps
CPU time 22.58 seconds
Started Jun 28 07:05:26 PM PDT 24
Finished Jun 28 07:05:49 PM PDT 24
Peak memory 201680 kb
Host smart-7f9cd460-95a2-4122-9f76-6411f1659841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637081628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3637081628
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1057730316
Short name T469
Test name
Test status
Simulation time 4971717284 ps
CPU time 3.38 seconds
Started Jun 28 07:05:27 PM PDT 24
Finished Jun 28 07:05:32 PM PDT 24
Peak memory 201668 kb
Host smart-b05183e4-2c31-437f-8fb9-431e6bc15842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057730316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1057730316
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2262809555
Short name T95
Test name
Test status
Simulation time 5842756164 ps
CPU time 14.04 seconds
Started Jun 28 07:04:55 PM PDT 24
Finished Jun 28 07:05:10 PM PDT 24
Peak memory 201684 kb
Host smart-f8e50123-eb17-4c40-9c0b-96815b2da543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262809555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2262809555
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3721231127
Short name T491
Test name
Test status
Simulation time 205554048739 ps
CPU time 226.45 seconds
Started Jun 28 07:05:28 PM PDT 24
Finished Jun 28 07:09:16 PM PDT 24
Peak memory 218112 kb
Host smart-6cb17d57-6b74-4cee-8895-f4cd0e295388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721231127 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3721231127
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.143978389
Short name T545
Test name
Test status
Simulation time 565572167 ps
CPU time 0.91 seconds
Started Jun 28 07:05:43 PM PDT 24
Finished Jun 28 07:05:44 PM PDT 24
Peak memory 201628 kb
Host smart-f7917fe7-30c6-449b-8635-edad12f1ee25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143978389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.143978389
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.4108570872
Short name T268
Test name
Test status
Simulation time 180845949993 ps
CPU time 112.54 seconds
Started Jun 28 07:05:42 PM PDT 24
Finished Jun 28 07:07:36 PM PDT 24
Peak memory 201848 kb
Host smart-3fbee475-6db8-4a4d-96f2-32145c795e68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108570872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.4108570872
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2421024045
Short name T525
Test name
Test status
Simulation time 162715775497 ps
CPU time 102.72 seconds
Started Jun 28 07:05:41 PM PDT 24
Finished Jun 28 07:07:25 PM PDT 24
Peak memory 201892 kb
Host smart-e734afd0-cc45-40eb-b7c1-1e1f2a029e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421024045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2421024045
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2546532081
Short name T76
Test name
Test status
Simulation time 320779248014 ps
CPU time 747.53 seconds
Started Jun 28 07:05:26 PM PDT 24
Finished Jun 28 07:17:54 PM PDT 24
Peak memory 201956 kb
Host smart-c5896643-8531-44b1-817e-c9b802ae1251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546532081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2546532081
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.660232875
Short name T274
Test name
Test status
Simulation time 330635358470 ps
CPU time 521.58 seconds
Started Jun 28 07:05:28 PM PDT 24
Finished Jun 28 07:14:11 PM PDT 24
Peak memory 201888 kb
Host smart-e54c15fd-feb5-4a6c-bb6f-abe956232d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660232875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.660232875
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2870514368
Short name T379
Test name
Test status
Simulation time 500992503965 ps
CPU time 782.81 seconds
Started Jun 28 07:05:28 PM PDT 24
Finished Jun 28 07:18:32 PM PDT 24
Peak memory 201848 kb
Host smart-93d4fda8-d360-4f94-8bb5-09318c40db08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870514368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2870514368
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1004409579
Short name T193
Test name
Test status
Simulation time 373754936386 ps
CPU time 187.99 seconds
Started Jun 28 07:05:40 PM PDT 24
Finished Jun 28 07:08:49 PM PDT 24
Peak memory 201876 kb
Host smart-f1d39577-51ac-4f51-b9ef-f344c7435977
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004409579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1004409579
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2501235491
Short name T451
Test name
Test status
Simulation time 604047204415 ps
CPU time 667.84 seconds
Started Jun 28 07:05:40 PM PDT 24
Finished Jun 28 07:16:48 PM PDT 24
Peak memory 201840 kb
Host smart-ce47584c-c5c4-4b08-ac55-b0ba93909630
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501235491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2501235491
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3315421650
Short name T46
Test name
Test status
Simulation time 90019947486 ps
CPU time 385.69 seconds
Started Jun 28 07:05:42 PM PDT 24
Finished Jun 28 07:12:09 PM PDT 24
Peak memory 202204 kb
Host smart-f50469bd-9051-4e1c-bc25-c08f4c45603a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315421650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3315421650
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1303496360
Short name T716
Test name
Test status
Simulation time 31739832108 ps
CPU time 18.66 seconds
Started Jun 28 07:05:41 PM PDT 24
Finished Jun 28 07:06:01 PM PDT 24
Peak memory 201648 kb
Host smart-9fe776cc-1ea7-4ad3-86f0-9fe03fc221e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303496360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1303496360
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1674057097
Short name T90
Test name
Test status
Simulation time 4315429198 ps
CPU time 10.82 seconds
Started Jun 28 07:05:41 PM PDT 24
Finished Jun 28 07:05:54 PM PDT 24
Peak memory 201696 kb
Host smart-0419ba1e-395c-423b-af95-3ef18231bcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674057097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1674057097
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1579186506
Short name T657
Test name
Test status
Simulation time 5960747057 ps
CPU time 7.81 seconds
Started Jun 28 07:05:27 PM PDT 24
Finished Jun 28 07:05:37 PM PDT 24
Peak memory 201676 kb
Host smart-858e17fd-b806-4707-aec5-e8e50454531e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579186506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1579186506
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1395790923
Short name T18
Test name
Test status
Simulation time 279113235629 ps
CPU time 138.28 seconds
Started Jun 28 07:05:41 PM PDT 24
Finished Jun 28 07:08:00 PM PDT 24
Peak memory 210508 kb
Host smart-1555d7e8-8aa6-4722-bf13-ff61d3e42112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395790923 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1395790923
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2943911715
Short name T488
Test name
Test status
Simulation time 490290051 ps
CPU time 1.66 seconds
Started Jun 28 07:06:04 PM PDT 24
Finished Jun 28 07:06:07 PM PDT 24
Peak memory 201624 kb
Host smart-17c6724c-f0e9-42f5-939b-9bef47945fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943911715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2943911715
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.726286469
Short name T290
Test name
Test status
Simulation time 164141293226 ps
CPU time 188.53 seconds
Started Jun 28 07:05:53 PM PDT 24
Finished Jun 28 07:09:02 PM PDT 24
Peak memory 201888 kb
Host smart-6dff4de6-f6c2-49f2-a377-ba3bd3c23510
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726286469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.726286469
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3714148276
Short name T539
Test name
Test status
Simulation time 327214620654 ps
CPU time 405.04 seconds
Started Jun 28 07:05:54 PM PDT 24
Finished Jun 28 07:12:40 PM PDT 24
Peak memory 201892 kb
Host smart-695fb984-5c32-4a6c-a653-89079a2432c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714148276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3714148276
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3189777320
Short name T239
Test name
Test status
Simulation time 333629682776 ps
CPU time 755.74 seconds
Started Jun 28 07:05:53 PM PDT 24
Finished Jun 28 07:18:30 PM PDT 24
Peak memory 201880 kb
Host smart-907b5482-be58-434d-8b24-69d75a29c365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189777320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3189777320
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.959422265
Short name T567
Test name
Test status
Simulation time 493901545496 ps
CPU time 285.19 seconds
Started Jun 28 07:05:54 PM PDT 24
Finished Jun 28 07:10:41 PM PDT 24
Peak memory 201868 kb
Host smart-110816be-ba8e-45a8-bf05-3812e2798098
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=959422265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.959422265
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3632405003
Short name T717
Test name
Test status
Simulation time 160853457709 ps
CPU time 99.21 seconds
Started Jun 28 07:05:41 PM PDT 24
Finished Jun 28 07:07:22 PM PDT 24
Peak memory 201944 kb
Host smart-4760da6e-c5b3-4952-a649-f3246f016cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632405003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3632405003
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.778222509
Short name T412
Test name
Test status
Simulation time 327882091989 ps
CPU time 182.29 seconds
Started Jun 28 07:05:53 PM PDT 24
Finished Jun 28 07:08:57 PM PDT 24
Peak memory 201872 kb
Host smart-1bbc01a5-7b3f-4dbe-b21e-951a3626d0b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=778222509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.778222509
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.653005282
Short name T654
Test name
Test status
Simulation time 397787024534 ps
CPU time 234.43 seconds
Started Jun 28 07:05:53 PM PDT 24
Finished Jun 28 07:09:48 PM PDT 24
Peak memory 201852 kb
Host smart-f91240a7-59cd-4e22-aa10-337ef777e69b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653005282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.653005282
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3633096877
Short name T47
Test name
Test status
Simulation time 73893598561 ps
CPU time 250.33 seconds
Started Jun 28 07:06:04 PM PDT 24
Finished Jun 28 07:10:16 PM PDT 24
Peak memory 202192 kb
Host smart-c07ab540-3721-4bc6-af48-0dc68112f03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633096877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3633096877
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2567620021
Short name T426
Test name
Test status
Simulation time 28957279498 ps
CPU time 18.23 seconds
Started Jun 28 07:05:55 PM PDT 24
Finished Jun 28 07:06:14 PM PDT 24
Peak memory 201688 kb
Host smart-88b34b96-3686-4b1c-adbc-62b4c509d7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567620021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2567620021
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.122449566
Short name T623
Test name
Test status
Simulation time 3321125672 ps
CPU time 8.26 seconds
Started Jun 28 07:05:56 PM PDT 24
Finished Jun 28 07:06:05 PM PDT 24
Peak memory 201684 kb
Host smart-b1f44ca1-242e-4128-8b5b-2021d3cc8caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122449566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.122449566
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.943998789
Short name T749
Test name
Test status
Simulation time 5788295571 ps
CPU time 4.5 seconds
Started Jun 28 07:05:43 PM PDT 24
Finished Jun 28 07:05:48 PM PDT 24
Peak memory 201680 kb
Host smart-7d4f7157-5347-4b27-8b63-0d781eb82dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943998789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.943998789
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3658622355
Short name T479
Test name
Test status
Simulation time 169290083868 ps
CPU time 208.24 seconds
Started Jun 28 07:06:04 PM PDT 24
Finished Jun 28 07:09:34 PM PDT 24
Peak memory 201872 kb
Host smart-fa6c0e46-74b9-4353-87c1-a825bcdd34fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658622355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3658622355
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3611419716
Short name T531
Test name
Test status
Simulation time 494495830 ps
CPU time 0.91 seconds
Started Jun 28 07:06:28 PM PDT 24
Finished Jun 28 07:06:30 PM PDT 24
Peak memory 201624 kb
Host smart-6c7e0993-9024-48a0-bd3b-bbe84b2cbf26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611419716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3611419716
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1923408749
Short name T753
Test name
Test status
Simulation time 206202536798 ps
CPU time 220.83 seconds
Started Jun 28 07:06:16 PM PDT 24
Finished Jun 28 07:09:59 PM PDT 24
Peak memory 201892 kb
Host smart-9ea692f7-827b-4c7f-ad3d-e0278c26419d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923408749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1923408749
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4056070871
Short name T557
Test name
Test status
Simulation time 164769495803 ps
CPU time 366.47 seconds
Started Jun 28 07:06:03 PM PDT 24
Finished Jun 28 07:12:10 PM PDT 24
Peak memory 201824 kb
Host smart-01057979-263f-4bcf-bc27-88c3111874f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056070871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.4056070871
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1685309482
Short name T303
Test name
Test status
Simulation time 165594855700 ps
CPU time 367.53 seconds
Started Jun 28 07:06:03 PM PDT 24
Finished Jun 28 07:12:13 PM PDT 24
Peak memory 201960 kb
Host smart-9aa84fe2-07cf-4ad8-80eb-21452ce9e2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685309482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1685309482
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2478876326
Short name T442
Test name
Test status
Simulation time 327009417573 ps
CPU time 720.66 seconds
Started Jun 28 07:06:04 PM PDT 24
Finished Jun 28 07:18:06 PM PDT 24
Peak memory 201840 kb
Host smart-ed6e3286-4602-44a0-9b1f-26929819cc7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478876326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2478876326
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.4118228940
Short name T746
Test name
Test status
Simulation time 343765860313 ps
CPU time 708.82 seconds
Started Jun 28 07:06:03 PM PDT 24
Finished Jun 28 07:17:54 PM PDT 24
Peak memory 201880 kb
Host smart-d47e2fa9-51e5-4e3c-9fdc-a9e1a8905932
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118228940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.4118228940
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3944617905
Short name T660
Test name
Test status
Simulation time 609048548957 ps
CPU time 215.28 seconds
Started Jun 28 07:06:16 PM PDT 24
Finished Jun 28 07:09:53 PM PDT 24
Peak memory 201864 kb
Host smart-e01521c7-86c2-4299-980c-f8228a55f9f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944617905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3944617905
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2330553767
Short name T367
Test name
Test status
Simulation time 56791146910 ps
CPU time 250.23 seconds
Started Jun 28 07:06:16 PM PDT 24
Finished Jun 28 07:10:28 PM PDT 24
Peak memory 202252 kb
Host smart-ad75c19c-a4eb-4c7a-9a14-7d812de3fd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330553767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2330553767
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2463111603
Short name T552
Test name
Test status
Simulation time 24684758151 ps
CPU time 27.29 seconds
Started Jun 28 07:06:19 PM PDT 24
Finished Jun 28 07:06:48 PM PDT 24
Peak memory 201676 kb
Host smart-fbdf1cfc-5e48-4ab9-8d94-a8e631935296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463111603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2463111603
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2390131612
Short name T676
Test name
Test status
Simulation time 3577459321 ps
CPU time 2.88 seconds
Started Jun 28 07:06:17 PM PDT 24
Finished Jun 28 07:06:22 PM PDT 24
Peak memory 201664 kb
Host smart-f5110ef6-06f0-42ca-b202-c4c2ef2e1736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390131612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2390131612
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.675715321
Short name T689
Test name
Test status
Simulation time 5817388929 ps
CPU time 3.01 seconds
Started Jun 28 07:06:04 PM PDT 24
Finished Jun 28 07:06:09 PM PDT 24
Peak memory 201684 kb
Host smart-29e0631a-d5ce-4250-92fe-8f6ad42d7c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675715321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.675715321
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1165966840
Short name T673
Test name
Test status
Simulation time 497214384 ps
CPU time 0.91 seconds
Started Jun 28 07:06:37 PM PDT 24
Finished Jun 28 07:06:39 PM PDT 24
Peak memory 201628 kb
Host smart-32e723a5-041b-4fd0-a3df-8736c34249a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165966840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1165966840
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1402965987
Short name T183
Test name
Test status
Simulation time 325962802238 ps
CPU time 413.17 seconds
Started Jun 28 07:06:40 PM PDT 24
Finished Jun 28 07:13:35 PM PDT 24
Peak memory 201864 kb
Host smart-f4fe5e1d-6469-4ab1-87bb-c3136731ef19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402965987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1402965987
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1821643332
Short name T340
Test name
Test status
Simulation time 159406200801 ps
CPU time 100.87 seconds
Started Jun 28 07:06:36 PM PDT 24
Finished Jun 28 07:08:18 PM PDT 24
Peak memory 201812 kb
Host smart-f2eb2c90-17ad-4a9e-a9a3-e8775b4069f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821643332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1821643332
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2938128710
Short name T465
Test name
Test status
Simulation time 167254801847 ps
CPU time 98.54 seconds
Started Jun 28 07:06:27 PM PDT 24
Finished Jun 28 07:08:07 PM PDT 24
Peak memory 201872 kb
Host smart-0f207207-7143-4e49-a55c-ce9bb30915b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938128710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2938128710
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1620140893
Short name T242
Test name
Test status
Simulation time 321900680422 ps
CPU time 761.44 seconds
Started Jun 28 07:06:26 PM PDT 24
Finished Jun 28 07:19:09 PM PDT 24
Peak memory 201888 kb
Host smart-9f55a47a-6343-4e0b-99ba-ee9160d6f54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620140893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1620140893
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1196946275
Short name T789
Test name
Test status
Simulation time 478776752117 ps
CPU time 122.35 seconds
Started Jun 28 07:06:28 PM PDT 24
Finished Jun 28 07:08:32 PM PDT 24
Peak memory 201912 kb
Host smart-6357dcb6-2747-4b10-a953-90cd2905e7e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196946275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1196946275
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.121941167
Short name T328
Test name
Test status
Simulation time 528045880685 ps
CPU time 329.77 seconds
Started Jun 28 07:06:38 PM PDT 24
Finished Jun 28 07:12:09 PM PDT 24
Peak memory 201884 kb
Host smart-cb39620e-44e9-4e0e-a514-00c736b782dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121941167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.121941167
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.539539206
Short name T447
Test name
Test status
Simulation time 197159105641 ps
CPU time 83.17 seconds
Started Jun 28 07:06:39 PM PDT 24
Finished Jun 28 07:08:03 PM PDT 24
Peak memory 201856 kb
Host smart-20982991-7747-44e0-9f5c-6ea24ab2f178
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539539206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.539539206
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1174122103
Short name T219
Test name
Test status
Simulation time 70461648625 ps
CPU time 303.79 seconds
Started Jun 28 07:06:36 PM PDT 24
Finished Jun 28 07:11:41 PM PDT 24
Peak memory 202260 kb
Host smart-c5c42ee8-6c42-4780-8d6c-b63091beac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174122103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1174122103
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.976993238
Short name T542
Test name
Test status
Simulation time 41893630278 ps
CPU time 96.45 seconds
Started Jun 28 07:06:36 PM PDT 24
Finished Jun 28 07:08:13 PM PDT 24
Peak memory 201700 kb
Host smart-258d6602-3034-4335-8892-f6c319c455e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976993238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.976993238
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3437900920
Short name T570
Test name
Test status
Simulation time 3545194533 ps
CPU time 4.58 seconds
Started Jun 28 07:06:40 PM PDT 24
Finished Jun 28 07:06:46 PM PDT 24
Peak memory 201676 kb
Host smart-42a611b6-ec1d-40ad-b0a8-e3b2e685260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437900920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3437900920
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3673894369
Short name T555
Test name
Test status
Simulation time 5855767239 ps
CPU time 14.46 seconds
Started Jun 28 07:06:27 PM PDT 24
Finished Jun 28 07:06:43 PM PDT 24
Peak memory 201664 kb
Host smart-d9027342-8053-4b85-b694-fbc8d5460dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673894369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3673894369
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1041297847
Short name T176
Test name
Test status
Simulation time 77130976752 ps
CPU time 179.6 seconds
Started Jun 28 07:06:38 PM PDT 24
Finished Jun 28 07:09:38 PM PDT 24
Peak memory 201656 kb
Host smart-10a28101-4271-4a3e-b505-d5ba29683dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041297847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1041297847
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.496830787
Short name T293
Test name
Test status
Simulation time 162554577604 ps
CPU time 104.79 seconds
Started Jun 28 07:06:36 PM PDT 24
Finished Jun 28 07:08:21 PM PDT 24
Peak memory 210512 kb
Host smart-d010527b-afbb-4117-836e-801a7949c6c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496830787 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.496830787
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.329805947
Short name T576
Test name
Test status
Simulation time 439587331 ps
CPU time 0.69 seconds
Started Jun 28 07:08:26 PM PDT 24
Finished Jun 28 07:08:30 PM PDT 24
Peak memory 201616 kb
Host smart-c0686c22-2a94-4703-a8ae-e5f2a9f50a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329805947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.329805947
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.611554262
Short name T166
Test name
Test status
Simulation time 330009950225 ps
CPU time 70.86 seconds
Started Jun 28 07:08:27 PM PDT 24
Finished Jun 28 07:09:41 PM PDT 24
Peak memory 201876 kb
Host smart-c2639abc-b2a8-4ac9-85f7-ab671194be9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611554262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.611554262
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1544361230
Short name T482
Test name
Test status
Simulation time 173575612720 ps
CPU time 188.34 seconds
Started Jun 28 07:06:47 PM PDT 24
Finished Jun 28 07:09:57 PM PDT 24
Peak memory 201884 kb
Host smart-f1e09000-02cc-4240-b9da-21270d8e7dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544361230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1544361230
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3568358828
Short name T616
Test name
Test status
Simulation time 168395783766 ps
CPU time 102.4 seconds
Started Jun 28 07:06:49 PM PDT 24
Finished Jun 28 07:08:32 PM PDT 24
Peak memory 201868 kb
Host smart-63551fa3-4756-4e68-9ab0-650acd275f1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568358828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3568358828
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1774416147
Short name T314
Test name
Test status
Simulation time 503236534945 ps
CPU time 590.07 seconds
Started Jun 28 07:06:50 PM PDT 24
Finished Jun 28 07:16:41 PM PDT 24
Peak memory 201808 kb
Host smart-443b3055-28d8-4623-8397-223dd0419ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774416147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1774416147
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3789507689
Short name T565
Test name
Test status
Simulation time 495142988476 ps
CPU time 614.89 seconds
Started Jun 28 07:06:52 PM PDT 24
Finished Jun 28 07:17:08 PM PDT 24
Peak memory 201844 kb
Host smart-9f7a6d63-1801-4ff9-b50c-48067e028e4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789507689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3789507689
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2837328412
Short name T651
Test name
Test status
Simulation time 222944408948 ps
CPU time 48.62 seconds
Started Jun 28 07:06:50 PM PDT 24
Finished Jun 28 07:07:40 PM PDT 24
Peak memory 201868 kb
Host smart-4262ad25-dfd6-4def-a8b6-2cf49e40db6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837328412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2837328412
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.877146838
Short name T504
Test name
Test status
Simulation time 600053500738 ps
CPU time 76.56 seconds
Started Jun 28 07:08:27 PM PDT 24
Finished Jun 28 07:09:47 PM PDT 24
Peak memory 201848 kb
Host smart-e7a5f8ef-8943-4705-94b9-d20c165b6409
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877146838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.877146838
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1829540884
Short name T694
Test name
Test status
Simulation time 42072130935 ps
CPU time 98.55 seconds
Started Jun 28 07:08:26 PM PDT 24
Finished Jun 28 07:10:08 PM PDT 24
Peak memory 201680 kb
Host smart-bde9adcf-fe15-4c44-b5af-1fa084d07c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829540884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1829540884
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1399457397
Short name T43
Test name
Test status
Simulation time 2898541163 ps
CPU time 7.93 seconds
Started Jun 28 07:08:27 PM PDT 24
Finished Jun 28 07:08:39 PM PDT 24
Peak memory 201684 kb
Host smart-6b03f62b-9a38-4d59-abf3-45c47eee9807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399457397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1399457397
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3251733922
Short name T594
Test name
Test status
Simulation time 5790593177 ps
CPU time 3.22 seconds
Started Jun 28 07:06:50 PM PDT 24
Finished Jun 28 07:06:54 PM PDT 24
Peak memory 201604 kb
Host smart-84a3a421-902e-431d-81c5-38f01addf009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251733922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3251733922
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2554788842
Short name T128
Test name
Test status
Simulation time 199423561022 ps
CPU time 420.2 seconds
Started Jun 28 07:08:27 PM PDT 24
Finished Jun 28 07:15:31 PM PDT 24
Peak memory 201896 kb
Host smart-74b2270e-5571-4ad3-bdbf-338c8c70b27a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554788842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2554788842
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.744405956
Short name T452
Test name
Test status
Simulation time 463191772 ps
CPU time 0.89 seconds
Started Jun 28 07:08:27 PM PDT 24
Finished Jun 28 07:08:32 PM PDT 24
Peak memory 201632 kb
Host smart-605146a3-ae99-4a56-9eb4-cd85a938c872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744405956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.744405956
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3974267596
Short name T276
Test name
Test status
Simulation time 371195284699 ps
CPU time 235.07 seconds
Started Jun 28 07:08:28 PM PDT 24
Finished Jun 28 07:12:26 PM PDT 24
Peak memory 201864 kb
Host smart-8d92a67e-24c2-4fca-911a-f1779a381382
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974267596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3974267596
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3195036772
Short name T683
Test name
Test status
Simulation time 330006793613 ps
CPU time 715.5 seconds
Started Jun 28 07:08:28 PM PDT 24
Finished Jun 28 07:20:27 PM PDT 24
Peak memory 201868 kb
Host smart-ef28cc3c-7745-48b8-bd7c-c8941d59430b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195036772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3195036772
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3055689000
Short name T679
Test name
Test status
Simulation time 498618894878 ps
CPU time 101.66 seconds
Started Jun 28 07:08:26 PM PDT 24
Finished Jun 28 07:10:11 PM PDT 24
Peak memory 201840 kb
Host smart-2d4eff8e-fe12-4795-a919-fdd66272bdb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055689000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3055689000
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1617670440
Short name T291
Test name
Test status
Simulation time 327518949345 ps
CPU time 740.49 seconds
Started Jun 28 07:08:27 PM PDT 24
Finished Jun 28 07:20:51 PM PDT 24
Peak memory 201928 kb
Host smart-ac9dcac3-92fc-4858-bb24-d285b56d08f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617670440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1617670440
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.166885725
Short name T757
Test name
Test status
Simulation time 330092955975 ps
CPU time 792.03 seconds
Started Jun 28 07:08:27 PM PDT 24
Finished Jun 28 07:21:42 PM PDT 24
Peak memory 201864 kb
Host smart-568c69d5-6bb3-4068-be72-41c04976ff26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=166885725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.166885725
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.455558371
Short name T533
Test name
Test status
Simulation time 189714713752 ps
CPU time 443.05 seconds
Started Jun 28 07:08:28 PM PDT 24
Finished Jun 28 07:15:54 PM PDT 24
Peak memory 202028 kb
Host smart-dbbdc78a-3b1d-46d4-86be-c3d049064df4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455558371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.455558371
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1137646615
Short name T636
Test name
Test status
Simulation time 402949962947 ps
CPU time 94.48 seconds
Started Jun 28 07:08:27 PM PDT 24
Finished Jun 28 07:10:05 PM PDT 24
Peak memory 201872 kb
Host smart-41b760ac-f86a-4831-a107-eae8fdab9cb3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137646615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1137646615
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1824217701
Short name T682
Test name
Test status
Simulation time 21621042334 ps
CPU time 24.66 seconds
Started Jun 28 07:08:27 PM PDT 24
Finished Jun 28 07:08:55 PM PDT 24
Peak memory 201668 kb
Host smart-5534ece8-d508-412c-829a-d9dc1c1feaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824217701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1824217701
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2357652920
Short name T635
Test name
Test status
Simulation time 3594809950 ps
CPU time 8.05 seconds
Started Jun 28 07:08:28 PM PDT 24
Finished Jun 28 07:08:39 PM PDT 24
Peak memory 201836 kb
Host smart-d52c83b0-4706-434e-a6be-3f6fb34a1e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357652920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2357652920
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3883423131
Short name T609
Test name
Test status
Simulation time 5815421446 ps
CPU time 12.71 seconds
Started Jun 28 07:08:28 PM PDT 24
Finished Jun 28 07:08:44 PM PDT 24
Peak memory 201672 kb
Host smart-9f30789b-bb6b-4650-b7da-a2ccd4d43340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883423131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3883423131
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3382347398
Short name T138
Test name
Test status
Simulation time 45958652455 ps
CPU time 162.74 seconds
Started Jun 28 07:08:27 PM PDT 24
Finished Jun 28 07:11:14 PM PDT 24
Peak memory 217752 kb
Host smart-906bd491-0169-4131-bac7-f95914c78722
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382347398 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3382347398
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.852824147
Short name T785
Test name
Test status
Simulation time 433009826 ps
CPU time 0.86 seconds
Started Jun 28 07:08:49 PM PDT 24
Finished Jun 28 07:08:53 PM PDT 24
Peak memory 201544 kb
Host smart-b2a56f77-ec99-4120-bd41-fab064f72b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852824147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.852824147
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.921625726
Short name T158
Test name
Test status
Simulation time 323148850009 ps
CPU time 710.24 seconds
Started Jun 28 07:08:48 PM PDT 24
Finished Jun 28 07:20:42 PM PDT 24
Peak memory 201884 kb
Host smart-51302eb9-d877-441b-83b2-860f40f8ef5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921625726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.921625726
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3272112359
Short name T202
Test name
Test status
Simulation time 339513423795 ps
CPU time 242.62 seconds
Started Jun 28 07:08:53 PM PDT 24
Finished Jun 28 07:12:57 PM PDT 24
Peak memory 201876 kb
Host smart-4389ac73-3fe4-49e2-beed-76f962dc0d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272112359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3272112359
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3051020015
Short name T289
Test name
Test status
Simulation time 483037684716 ps
CPU time 315.89 seconds
Started Jun 28 07:08:54 PM PDT 24
Finished Jun 28 07:14:12 PM PDT 24
Peak memory 201896 kb
Host smart-36a8c057-35ed-430a-92f3-33dd29e71d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051020015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3051020015
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1561260019
Short name T388
Test name
Test status
Simulation time 334274051117 ps
CPU time 388.93 seconds
Started Jun 28 07:08:55 PM PDT 24
Finished Jun 28 07:15:25 PM PDT 24
Peak memory 201856 kb
Host smart-25a3702e-33cf-43e6-9ee0-9f31491cab13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561260019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1561260019
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3343621381
Short name T662
Test name
Test status
Simulation time 161426894341 ps
CPU time 93.13 seconds
Started Jun 28 07:08:49 PM PDT 24
Finished Jun 28 07:10:26 PM PDT 24
Peak memory 201928 kb
Host smart-425d3ffc-ddce-4f27-b6fa-7a363d98bc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343621381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3343621381
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1198810021
Short name T747
Test name
Test status
Simulation time 164244329386 ps
CPU time 249.65 seconds
Started Jun 28 07:08:49 PM PDT 24
Finished Jun 28 07:13:02 PM PDT 24
Peak memory 201856 kb
Host smart-9d3831c1-8d28-403b-8026-3b6e235a9731
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198810021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1198810021
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3437526206
Short name T554
Test name
Test status
Simulation time 644018650717 ps
CPU time 408.57 seconds
Started Jun 28 07:08:48 PM PDT 24
Finished Jun 28 07:15:41 PM PDT 24
Peak memory 201896 kb
Host smart-a613fd22-64db-494f-affe-d2eff6da863c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437526206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3437526206
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3804257643
Short name T177
Test name
Test status
Simulation time 190986056864 ps
CPU time 112.91 seconds
Started Jun 28 07:08:47 PM PDT 24
Finished Jun 28 07:10:45 PM PDT 24
Peak memory 201912 kb
Host smart-ace0a80b-0e99-4440-88c2-b9ab72a5a653
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804257643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3804257643
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3284419147
Short name T81
Test name
Test status
Simulation time 121071138191 ps
CPU time 620.47 seconds
Started Jun 28 07:08:48 PM PDT 24
Finished Jun 28 07:19:13 PM PDT 24
Peak memory 202224 kb
Host smart-985a421e-5d06-43df-af55-e1112c3fd7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284419147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3284419147
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.424190267
Short name T456
Test name
Test status
Simulation time 43377037321 ps
CPU time 23.88 seconds
Started Jun 28 07:08:47 PM PDT 24
Finished Jun 28 07:09:15 PM PDT 24
Peak memory 201680 kb
Host smart-1dcecfb2-57d6-472b-af8a-fa923df4d314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424190267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.424190267
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.511251574
Short name T668
Test name
Test status
Simulation time 4362057507 ps
CPU time 2.97 seconds
Started Jun 28 07:08:48 PM PDT 24
Finished Jun 28 07:08:55 PM PDT 24
Peak memory 201676 kb
Host smart-ecfc3fda-cfd5-4d5e-b468-1293013668fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511251574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.511251574
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3691307525
Short name T686
Test name
Test status
Simulation time 6127009119 ps
CPU time 7.72 seconds
Started Jun 28 07:08:27 PM PDT 24
Finished Jun 28 07:08:38 PM PDT 24
Peak memory 201684 kb
Host smart-0a0913eb-8306-4fda-82e3-d2cc48446fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691307525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3691307525
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3067003870
Short name T605
Test name
Test status
Simulation time 39837023473 ps
CPU time 66.15 seconds
Started Jun 28 07:08:48 PM PDT 24
Finished Jun 28 07:09:58 PM PDT 24
Peak memory 210568 kb
Host smart-4ff6aab9-2e15-4f25-bf98-9df01fe09e5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067003870 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3067003870
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1221101982
Short name T530
Test name
Test status
Simulation time 377392246 ps
CPU time 0.84 seconds
Started Jun 28 07:09:08 PM PDT 24
Finished Jun 28 07:09:13 PM PDT 24
Peak memory 201632 kb
Host smart-486f5eb9-56da-4dd0-9eee-f7da77739b35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221101982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1221101982
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3612703879
Short name T270
Test name
Test status
Simulation time 167703342213 ps
CPU time 354.18 seconds
Started Jun 28 07:09:09 PM PDT 24
Finished Jun 28 07:15:07 PM PDT 24
Peak memory 201792 kb
Host smart-5ecdf220-eacf-4a43-a1d0-91331f67ffd4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612703879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3612703879
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2091211497
Short name T593
Test name
Test status
Simulation time 274596880118 ps
CPU time 138.57 seconds
Started Jun 28 07:09:10 PM PDT 24
Finished Jun 28 07:11:33 PM PDT 24
Peak memory 201900 kb
Host smart-c55719c4-9271-4ad7-be99-2294ce589f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091211497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2091211497
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1173242461
Short name T494
Test name
Test status
Simulation time 163703817459 ps
CPU time 101.97 seconds
Started Jun 28 07:08:48 PM PDT 24
Finished Jun 28 07:10:34 PM PDT 24
Peak memory 201816 kb
Host smart-bfc867e3-06db-4576-a059-e50f351d562e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173242461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1173242461
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2915143158
Short name T771
Test name
Test status
Simulation time 491629112966 ps
CPU time 1118.68 seconds
Started Jun 28 07:08:47 PM PDT 24
Finished Jun 28 07:27:30 PM PDT 24
Peak memory 201836 kb
Host smart-61432a03-ed26-4f03-8801-ad59bf10866c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915143158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2915143158
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2062874497
Short name T240
Test name
Test status
Simulation time 320452312579 ps
CPU time 190.34 seconds
Started Jun 28 07:08:47 PM PDT 24
Finished Jun 28 07:12:02 PM PDT 24
Peak memory 201896 kb
Host smart-57d6aeea-4fe0-47f5-ba55-5e9cc4187ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062874497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2062874497
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.956233591
Short name T742
Test name
Test status
Simulation time 168976312665 ps
CPU time 367.61 seconds
Started Jun 28 07:08:55 PM PDT 24
Finished Jun 28 07:15:04 PM PDT 24
Peak memory 201928 kb
Host smart-aacb048f-ee11-4f87-abde-b538de5b7b12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=956233591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.956233591
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.628813388
Short name T180
Test name
Test status
Simulation time 571891713193 ps
CPU time 329.77 seconds
Started Jun 28 07:08:53 PM PDT 24
Finished Jun 28 07:14:24 PM PDT 24
Peak memory 201928 kb
Host smart-b179503f-3a2b-4968-9aeb-2fa79b009d99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628813388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.628813388
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.4190545491
Short name T395
Test name
Test status
Simulation time 197562877113 ps
CPU time 305.28 seconds
Started Jun 28 07:09:10 PM PDT 24
Finished Jun 28 07:14:21 PM PDT 24
Peak memory 201840 kb
Host smart-39f1c50c-cdf8-4c9d-9b73-15aedfdf26f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190545491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.4190545491
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3524168624
Short name T370
Test name
Test status
Simulation time 123286297210 ps
CPU time 461.95 seconds
Started Jun 28 07:09:10 PM PDT 24
Finished Jun 28 07:16:56 PM PDT 24
Peak memory 202120 kb
Host smart-b45cb176-1ec0-4c3c-989c-0712855cd6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524168624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3524168624
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.361093114
Short name T664
Test name
Test status
Simulation time 26342025282 ps
CPU time 31.5 seconds
Started Jun 28 07:09:09 PM PDT 24
Finished Jun 28 07:09:46 PM PDT 24
Peak memory 201704 kb
Host smart-70be88db-18a5-45ae-a192-1d416fa5cd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361093114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.361093114
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3943322350
Short name T381
Test name
Test status
Simulation time 4771135959 ps
CPU time 7.01 seconds
Started Jun 28 07:09:08 PM PDT 24
Finished Jun 28 07:09:20 PM PDT 24
Peak memory 201672 kb
Host smart-06e01ad4-a687-4ff8-9201-b7238691d8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943322350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3943322350
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.494994283
Short name T490
Test name
Test status
Simulation time 5600183021 ps
CPU time 12.72 seconds
Started Jun 28 07:08:54 PM PDT 24
Finished Jun 28 07:09:08 PM PDT 24
Peak memory 201672 kb
Host smart-00ddaf12-19fc-46b3-bfdb-df0f4e55e248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494994283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.494994283
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.538593442
Short name T786
Test name
Test status
Simulation time 74427226343 ps
CPU time 309.57 seconds
Started Jun 28 07:09:11 PM PDT 24
Finished Jun 28 07:14:25 PM PDT 24
Peak memory 202196 kb
Host smart-1460ad32-ba2e-49a4-a34b-a16b94b972e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538593442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
538593442
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.127506459
Short name T489
Test name
Test status
Simulation time 417059269 ps
CPU time 1.54 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:00:11 PM PDT 24
Peak memory 201624 kb
Host smart-03437a8a-4c6a-4599-af60-66cb19e017fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127506459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.127506459
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3862019172
Short name T277
Test name
Test status
Simulation time 322978516191 ps
CPU time 102.8 seconds
Started Jun 28 06:59:55 PM PDT 24
Finished Jun 28 07:01:40 PM PDT 24
Peak memory 201880 kb
Host smart-a6f86d3a-563f-47ee-ac13-2721ab6d444b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862019172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3862019172
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.4197775681
Short name T658
Test name
Test status
Simulation time 512254900098 ps
CPU time 1091.76 seconds
Started Jun 28 06:59:54 PM PDT 24
Finished Jun 28 07:18:08 PM PDT 24
Peak memory 201892 kb
Host smart-5f68c9d8-41c7-4380-b169-f06693116e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197775681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.4197775681
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.749431568
Short name T150
Test name
Test status
Simulation time 327418542274 ps
CPU time 195.02 seconds
Started Jun 28 06:59:55 PM PDT 24
Finished Jun 28 07:03:12 PM PDT 24
Peak memory 201952 kb
Host smart-2dabb0f3-dfec-4d97-98b9-a92dfa5f7229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749431568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.749431568
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3828473245
Short name T577
Test name
Test status
Simulation time 161424217307 ps
CPU time 189.55 seconds
Started Jun 28 06:59:58 PM PDT 24
Finished Jun 28 07:03:09 PM PDT 24
Peak memory 200504 kb
Host smart-000e68e6-0a86-4985-bef8-6255d072912b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828473245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3828473245
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1880798659
Short name T283
Test name
Test status
Simulation time 498914932127 ps
CPU time 1026.59 seconds
Started Jun 28 06:59:53 PM PDT 24
Finished Jun 28 07:17:01 PM PDT 24
Peak memory 201956 kb
Host smart-d6345809-1bd2-4692-a433-a23a617a9453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880798659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1880798659
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3721184204
Short name T648
Test name
Test status
Simulation time 328956539527 ps
CPU time 789.59 seconds
Started Jun 28 06:59:58 PM PDT 24
Finished Jun 28 07:13:09 PM PDT 24
Peak memory 200600 kb
Host smart-11e6e373-cc92-4697-89ed-dc32392c8be8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721184204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3721184204
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2702121515
Short name T273
Test name
Test status
Simulation time 177524590739 ps
CPU time 201.68 seconds
Started Jun 28 06:59:53 PM PDT 24
Finished Jun 28 07:03:15 PM PDT 24
Peak memory 201940 kb
Host smart-d1c19253-cc0b-4968-8d3b-78b6a0269619
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702121515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2702121515
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2887559064
Short name T622
Test name
Test status
Simulation time 609721092243 ps
CPU time 372.66 seconds
Started Jun 28 06:59:54 PM PDT 24
Finished Jun 28 07:06:08 PM PDT 24
Peak memory 201848 kb
Host smart-0606be53-fba0-4173-a3de-4d74c3423306
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887559064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2887559064
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.551379424
Short name T619
Test name
Test status
Simulation time 68442226808 ps
CPU time 229.55 seconds
Started Jun 28 06:59:56 PM PDT 24
Finished Jun 28 07:03:48 PM PDT 24
Peak memory 202192 kb
Host smart-da8b2d43-97d9-4c25-84d6-d3438095c9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551379424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.551379424
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2464160407
Short name T387
Test name
Test status
Simulation time 38301709413 ps
CPU time 13.92 seconds
Started Jun 28 06:59:54 PM PDT 24
Finished Jun 28 07:00:10 PM PDT 24
Peak memory 201676 kb
Host smart-f1c7876f-1b50-4ba5-9ac5-cc7e684c80f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464160407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2464160407
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1901749890
Short name T792
Test name
Test status
Simulation time 4595255927 ps
CPU time 3.47 seconds
Started Jun 28 06:59:56 PM PDT 24
Finished Jun 28 07:00:01 PM PDT 24
Peak memory 201692 kb
Host smart-7d966576-1b01-499f-b4d9-7a1ad1b04a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901749890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1901749890
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2358157891
Short name T64
Test name
Test status
Simulation time 3840628418 ps
CPU time 6.56 seconds
Started Jun 28 07:00:05 PM PDT 24
Finished Jun 28 07:00:16 PM PDT 24
Peak memory 217108 kb
Host smart-82ef3849-45e6-4c00-a365-8315dfbb5c24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358157891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2358157891
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.723467540
Short name T196
Test name
Test status
Simulation time 5840980225 ps
CPU time 2.24 seconds
Started Jun 28 06:59:54 PM PDT 24
Finished Jun 28 06:59:58 PM PDT 24
Peak memory 201680 kb
Host smart-7d9c7ae0-5f61-4734-b519-b0025454e077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723467540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.723467540
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1504562535
Short name T356
Test name
Test status
Simulation time 160731617619 ps
CPU time 89.93 seconds
Started Jun 28 06:59:54 PM PDT 24
Finished Jun 28 07:01:26 PM PDT 24
Peak memory 210212 kb
Host smart-f36401e3-a105-42a4-99b0-0bdda8595a29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504562535 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1504562535
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3668832080
Short name T399
Test name
Test status
Simulation time 346100911 ps
CPU time 1.31 seconds
Started Jun 28 07:09:10 PM PDT 24
Finished Jun 28 07:09:17 PM PDT 24
Peak memory 201544 kb
Host smart-c3ae5d7a-04a3-4049-b000-b92fa7e8e748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668832080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3668832080
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1950131746
Short name T246
Test name
Test status
Simulation time 356386727413 ps
CPU time 469.65 seconds
Started Jun 28 07:09:09 PM PDT 24
Finished Jun 28 07:17:03 PM PDT 24
Peak memory 201864 kb
Host smart-00897168-5c77-4b84-ba66-44e788b7923a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950131746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1950131746
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3928635724
Short name T311
Test name
Test status
Simulation time 594210647854 ps
CPU time 705.37 seconds
Started Jun 28 07:09:10 PM PDT 24
Finished Jun 28 07:21:00 PM PDT 24
Peak memory 201888 kb
Host smart-2e03b4aa-394a-4ac4-9630-4436e0f7dc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928635724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3928635724
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3990890641
Short name T603
Test name
Test status
Simulation time 160560182300 ps
CPU time 26.72 seconds
Started Jun 28 07:09:10 PM PDT 24
Finished Jun 28 07:09:41 PM PDT 24
Peak memory 201948 kb
Host smart-16d6076d-22d5-48ca-a569-f927fa22cca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990890641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3990890641
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3176670920
Short name T406
Test name
Test status
Simulation time 164219905010 ps
CPU time 359.7 seconds
Started Jun 28 07:09:09 PM PDT 24
Finished Jun 28 07:15:13 PM PDT 24
Peak memory 201860 kb
Host smart-eae94d4d-eb52-4d6e-bd4b-fe799d75169e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176670920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3176670920
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.641994944
Short name T322
Test name
Test status
Simulation time 327568742113 ps
CPU time 733.43 seconds
Started Jun 28 07:09:07 PM PDT 24
Finished Jun 28 07:21:25 PM PDT 24
Peak memory 201892 kb
Host smart-152184cc-2e7c-434d-9eb7-ed6d95116e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641994944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.641994944
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.4015634449
Short name T608
Test name
Test status
Simulation time 334764050433 ps
CPU time 171.41 seconds
Started Jun 28 07:09:11 PM PDT 24
Finished Jun 28 07:12:07 PM PDT 24
Peak memory 201868 kb
Host smart-c8c2acb2-7247-48ae-ae02-d7d69bbee6ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015634449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.4015634449
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1208377397
Short name T697
Test name
Test status
Simulation time 588167667526 ps
CPU time 1430.57 seconds
Started Jun 28 07:09:09 PM PDT 24
Finished Jun 28 07:33:04 PM PDT 24
Peak memory 201856 kb
Host smart-11761606-2586-47cf-b2ca-4127dd69015d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208377397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1208377397
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3421814634
Short name T535
Test name
Test status
Simulation time 70449867449 ps
CPU time 363.28 seconds
Started Jun 28 07:09:10 PM PDT 24
Finished Jun 28 07:15:18 PM PDT 24
Peak memory 202188 kb
Host smart-3ad46ddc-70ef-407b-adf2-cb308b7700a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421814634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3421814634
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3850245879
Short name T93
Test name
Test status
Simulation time 43549165726 ps
CPU time 38.24 seconds
Started Jun 28 07:09:08 PM PDT 24
Finished Jun 28 07:09:51 PM PDT 24
Peak memory 201660 kb
Host smart-fa6a6b82-bccb-45cb-bb45-89d20d7da329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850245879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3850245879
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.577061625
Short name T776
Test name
Test status
Simulation time 5352739346 ps
CPU time 12.18 seconds
Started Jun 28 07:09:11 PM PDT 24
Finished Jun 28 07:09:28 PM PDT 24
Peak memory 201692 kb
Host smart-e136fd2b-28a4-4bd6-a3bf-5a152f7bc289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577061625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.577061625
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1777372403
Short name T28
Test name
Test status
Simulation time 6104821805 ps
CPU time 14.72 seconds
Started Jun 28 07:09:09 PM PDT 24
Finished Jun 28 07:09:29 PM PDT 24
Peak memory 201664 kb
Host smart-6efd6a8c-9d04-478c-b3d3-d57723d9293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777372403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1777372403
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3383453366
Short name T505
Test name
Test status
Simulation time 82609238770 ps
CPU time 174.71 seconds
Started Jun 28 07:09:08 PM PDT 24
Finished Jun 28 07:12:07 PM PDT 24
Peak memory 201680 kb
Host smart-46748f3b-9c89-497e-93fb-ac15c5f5e3d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383453366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3383453366
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2130210786
Short name T774
Test name
Test status
Simulation time 118339355307 ps
CPU time 31.3 seconds
Started Jun 28 07:09:08 PM PDT 24
Finished Jun 28 07:09:44 PM PDT 24
Peak memory 210204 kb
Host smart-7ef6a989-65b8-42b7-8223-0addf8e22660
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130210786 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2130210786
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3338974831
Short name T436
Test name
Test status
Simulation time 337604294 ps
CPU time 0.93 seconds
Started Jun 28 07:09:28 PM PDT 24
Finished Jun 28 07:09:35 PM PDT 24
Peak memory 201648 kb
Host smart-734efbf9-b87b-4093-9ef7-6fbfc0f86b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338974831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3338974831
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3931250018
Short name T261
Test name
Test status
Simulation time 335214087074 ps
CPU time 157.88 seconds
Started Jun 28 07:09:32 PM PDT 24
Finished Jun 28 07:12:13 PM PDT 24
Peak memory 201536 kb
Host smart-c00f94cd-0e46-4d0b-b377-731971a8c156
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931250018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3931250018
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2515854008
Short name T320
Test name
Test status
Simulation time 484539303882 ps
CPU time 1125.1 seconds
Started Jun 28 07:09:10 PM PDT 24
Finished Jun 28 07:28:00 PM PDT 24
Peak memory 201884 kb
Host smart-bbfd77f8-62a6-4c5b-8749-70d1344a7504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515854008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2515854008
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3405823485
Short name T386
Test name
Test status
Simulation time 333775500105 ps
CPU time 226.37 seconds
Started Jun 28 07:09:11 PM PDT 24
Finished Jun 28 07:13:02 PM PDT 24
Peak memory 201856 kb
Host smart-6e8d0133-f38a-4fba-a923-353bda802f4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405823485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3405823485
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3717945096
Short name T234
Test name
Test status
Simulation time 322500141479 ps
CPU time 690.7 seconds
Started Jun 28 07:09:11 PM PDT 24
Finished Jun 28 07:20:47 PM PDT 24
Peak memory 201888 kb
Host smart-ddcf4781-f9e7-4dfa-887d-d143f868d4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717945096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3717945096
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3350445052
Short name T378
Test name
Test status
Simulation time 164101404228 ps
CPU time 93.73 seconds
Started Jun 28 07:09:10 PM PDT 24
Finished Jun 28 07:10:49 PM PDT 24
Peak memory 201840 kb
Host smart-b43d07f6-3c3f-4ce3-9f0d-93f4e5511611
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350445052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3350445052
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.4250671841
Short name T308
Test name
Test status
Simulation time 361945022480 ps
CPU time 423.33 seconds
Started Jun 28 07:09:10 PM PDT 24
Finished Jun 28 07:16:18 PM PDT 24
Peak memory 201884 kb
Host smart-d45e449f-49fc-40f9-9cb9-8196b6f64d78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250671841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.4250671841
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1536877921
Short name T477
Test name
Test status
Simulation time 411463990719 ps
CPU time 968.54 seconds
Started Jun 28 07:09:11 PM PDT 24
Finished Jun 28 07:25:24 PM PDT 24
Peak memory 201856 kb
Host smart-e0709c7a-2466-4c91-a43c-fcbaf8e560b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536877921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1536877921
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.154363766
Short name T547
Test name
Test status
Simulation time 28085794463 ps
CPU time 13.77 seconds
Started Jun 28 07:09:27 PM PDT 24
Finished Jun 28 07:09:46 PM PDT 24
Peak memory 201680 kb
Host smart-9c7f94fa-5361-4d38-8698-741c0cbaf1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154363766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.154363766
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1464985742
Short name T677
Test name
Test status
Simulation time 3059741041 ps
CPU time 2.56 seconds
Started Jun 28 07:09:32 PM PDT 24
Finished Jun 28 07:09:38 PM PDT 24
Peak memory 201608 kb
Host smart-81c174e1-7baf-432e-abdc-a24828942a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464985742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1464985742
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1418411456
Short name T396
Test name
Test status
Simulation time 5852467940 ps
CPU time 4.81 seconds
Started Jun 28 07:09:10 PM PDT 24
Finished Jun 28 07:09:19 PM PDT 24
Peak memory 201680 kb
Host smart-bd37c0e8-7600-40dc-ab62-b35f876caa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418411456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1418411456
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1550191642
Short name T288
Test name
Test status
Simulation time 364984042470 ps
CPU time 217.55 seconds
Started Jun 28 07:09:28 PM PDT 24
Finished Jun 28 07:13:11 PM PDT 24
Peak memory 201868 kb
Host smart-e8be51b2-f72d-4c4c-bf72-23b3356e4e57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550191642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1550191642
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3316603520
Short name T453
Test name
Test status
Simulation time 492508127 ps
CPU time 0.96 seconds
Started Jun 28 07:09:55 PM PDT 24
Finished Jun 28 07:10:02 PM PDT 24
Peak memory 201632 kb
Host smart-33e0d82e-3f0d-4a91-8d1d-a4fa6fc4759c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316603520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3316603520
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4190385629
Short name T258
Test name
Test status
Simulation time 323349846329 ps
CPU time 226.3 seconds
Started Jun 28 07:09:27 PM PDT 24
Finished Jun 28 07:13:19 PM PDT 24
Peak memory 201920 kb
Host smart-b3c5b062-bb10-4eac-9dc8-35c1872fc284
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190385629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4190385629
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.44061048
Short name T795
Test name
Test status
Simulation time 339675850488 ps
CPU time 184.28 seconds
Started Jun 28 07:09:26 PM PDT 24
Finished Jun 28 07:12:37 PM PDT 24
Peak memory 201892 kb
Host smart-764daaa5-df94-4c38-ad4e-bc5158bb44fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44061048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.44061048
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.801795766
Short name T78
Test name
Test status
Simulation time 168022183629 ps
CPU time 70.57 seconds
Started Jun 28 07:09:27 PM PDT 24
Finished Jun 28 07:10:43 PM PDT 24
Peak memory 201864 kb
Host smart-8342c5ae-a9e9-4c5c-ab25-42ffee4da40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801795766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.801795766
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.110815137
Short name T424
Test name
Test status
Simulation time 502139879647 ps
CPU time 279.1 seconds
Started Jun 28 07:09:26 PM PDT 24
Finished Jun 28 07:14:11 PM PDT 24
Peak memory 201840 kb
Host smart-84d01c1b-bddf-4e68-bd42-bddad195c456
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=110815137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.110815137
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2880092628
Short name T301
Test name
Test status
Simulation time 490666442545 ps
CPU time 1044.84 seconds
Started Jun 28 07:09:28 PM PDT 24
Finished Jun 28 07:26:59 PM PDT 24
Peak memory 201888 kb
Host smart-86cbbd4f-757e-4814-8225-d48ebb896f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880092628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2880092628
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2818676308
Short name T772
Test name
Test status
Simulation time 171277908345 ps
CPU time 207.11 seconds
Started Jun 28 07:09:31 PM PDT 24
Finished Jun 28 07:13:02 PM PDT 24
Peak memory 201780 kb
Host smart-bb9d26ed-afc3-4165-894c-db2d14a51e7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818676308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2818676308
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3782804782
Short name T263
Test name
Test status
Simulation time 173421762155 ps
CPU time 379.45 seconds
Started Jun 28 07:09:27 PM PDT 24
Finished Jun 28 07:15:53 PM PDT 24
Peak memory 201944 kb
Host smart-a81cfaea-447f-41bd-b302-1c6cdb65cd7b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782804782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3782804782
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3845711799
Short name T517
Test name
Test status
Simulation time 201667327272 ps
CPU time 116.2 seconds
Started Jun 28 07:09:27 PM PDT 24
Finished Jun 28 07:11:29 PM PDT 24
Peak memory 201920 kb
Host smart-97f17a06-3601-450b-b74c-28740f30fabc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845711799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3845711799
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1947033635
Short name T459
Test name
Test status
Simulation time 93626070639 ps
CPU time 346.82 seconds
Started Jun 28 07:09:55 PM PDT 24
Finished Jun 28 07:15:48 PM PDT 24
Peak memory 202208 kb
Host smart-92fc67a5-2b20-40a9-93dc-a0cfa808848b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947033635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1947033635
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3438131979
Short name T409
Test name
Test status
Simulation time 29024215076 ps
CPU time 20.2 seconds
Started Jun 28 07:09:55 PM PDT 24
Finished Jun 28 07:10:21 PM PDT 24
Peak memory 201604 kb
Host smart-3f51f7bc-e224-47fd-b727-341fce8b2775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438131979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3438131979
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3555956393
Short name T481
Test name
Test status
Simulation time 3159669766 ps
CPU time 7.89 seconds
Started Jun 28 07:09:27 PM PDT 24
Finished Jun 28 07:09:41 PM PDT 24
Peak memory 201692 kb
Host smart-1fe56953-0db5-4d45-8554-56dfed233507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555956393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3555956393
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2435340846
Short name T699
Test name
Test status
Simulation time 5632710073 ps
CPU time 4.13 seconds
Started Jun 28 07:09:32 PM PDT 24
Finished Jun 28 07:09:39 PM PDT 24
Peak memory 201272 kb
Host smart-779f941c-9c59-4a6a-b9c6-3327e23e8af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435340846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2435340846
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1948673962
Short name T30
Test name
Test status
Simulation time 6845966544 ps
CPU time 15.87 seconds
Started Jun 28 07:09:57 PM PDT 24
Finished Jun 28 07:10:18 PM PDT 24
Peak memory 201668 kb
Host smart-d3c6b824-0d26-4130-b521-216088e66142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948673962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1948673962
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1572626071
Short name T353
Test name
Test status
Simulation time 147885398521 ps
CPU time 428.66 seconds
Started Jun 28 07:09:53 PM PDT 24
Finished Jun 28 07:17:08 PM PDT 24
Peak memory 210500 kb
Host smart-1b859769-3236-4eb2-b7d5-49850dfce565
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572626071 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1572626071
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1512682677
Short name T70
Test name
Test status
Simulation time 442408628 ps
CPU time 1.51 seconds
Started Jun 28 07:09:54 PM PDT 24
Finished Jun 28 07:10:01 PM PDT 24
Peak memory 201628 kb
Host smart-70675802-7780-46af-b3ff-e5f4d0ae2a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512682677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1512682677
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3884285871
Short name T235
Test name
Test status
Simulation time 165520454024 ps
CPU time 21.46 seconds
Started Jun 28 07:09:54 PM PDT 24
Finished Jun 28 07:10:22 PM PDT 24
Peak memory 201864 kb
Host smart-411472ec-922b-436f-9834-19ce87bf7db3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884285871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3884285871
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2495553683
Short name T302
Test name
Test status
Simulation time 335543730452 ps
CPU time 743.08 seconds
Started Jun 28 07:09:54 PM PDT 24
Finished Jun 28 07:22:23 PM PDT 24
Peak memory 201956 kb
Host smart-891e7987-430d-4bfe-a8d4-df7b61764fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495553683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2495553683
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4203499068
Short name T779
Test name
Test status
Simulation time 171364825051 ps
CPU time 403.4 seconds
Started Jun 28 07:09:54 PM PDT 24
Finished Jun 28 07:16:44 PM PDT 24
Peak memory 201852 kb
Host smart-2f543aeb-499e-4209-990d-6756534d108d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203499068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.4203499068
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3875732703
Short name T445
Test name
Test status
Simulation time 163893687723 ps
CPU time 378.51 seconds
Started Jun 28 07:09:56 PM PDT 24
Finished Jun 28 07:16:21 PM PDT 24
Peak memory 201876 kb
Host smart-b84b7432-504d-4223-804b-8a5224550126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875732703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3875732703
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2804459997
Short name T532
Test name
Test status
Simulation time 168900054927 ps
CPU time 387.88 seconds
Started Jun 28 07:09:54 PM PDT 24
Finished Jun 28 07:16:27 PM PDT 24
Peak memory 201852 kb
Host smart-b5eece2b-9493-4c2b-9f5c-85e267523b91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804459997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2804459997
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3863018653
Short name T194
Test name
Test status
Simulation time 536605422987 ps
CPU time 1227.89 seconds
Started Jun 28 07:09:53 PM PDT 24
Finished Jun 28 07:30:27 PM PDT 24
Peak memory 201884 kb
Host smart-c2f8dc2c-d8bd-4347-a8f5-af67a4a93781
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863018653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3863018653
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3187147860
Short name T773
Test name
Test status
Simulation time 597526136598 ps
CPU time 337.98 seconds
Started Jun 28 07:09:56 PM PDT 24
Finished Jun 28 07:15:40 PM PDT 24
Peak memory 201856 kb
Host smart-c04efb34-f78a-4316-b6a6-a5153167345c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187147860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3187147860
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1008955833
Short name T733
Test name
Test status
Simulation time 116988420779 ps
CPU time 661.69 seconds
Started Jun 28 07:09:55 PM PDT 24
Finished Jun 28 07:21:03 PM PDT 24
Peak memory 202176 kb
Host smart-315e75ea-8469-4544-8a7c-fceaec55a63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008955833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1008955833
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3731123071
Short name T461
Test name
Test status
Simulation time 40823846151 ps
CPU time 48.92 seconds
Started Jun 28 07:09:55 PM PDT 24
Finished Jun 28 07:10:51 PM PDT 24
Peak memory 201684 kb
Host smart-537911e6-6828-4fdc-b7dc-637ef3105f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731123071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3731123071
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2777727655
Short name T415
Test name
Test status
Simulation time 2968013657 ps
CPU time 4.22 seconds
Started Jun 28 07:09:54 PM PDT 24
Finished Jun 28 07:10:05 PM PDT 24
Peak memory 201688 kb
Host smart-4283f4fc-a54b-4e7f-ac95-043f3e2c44d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777727655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2777727655
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2471086501
Short name T201
Test name
Test status
Simulation time 5973582615 ps
CPU time 15.07 seconds
Started Jun 28 07:09:54 PM PDT 24
Finished Jun 28 07:10:16 PM PDT 24
Peak memory 201680 kb
Host smart-cf9ca363-5b20-4775-8550-a63c37476b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471086501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2471086501
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2243511152
Short name T339
Test name
Test status
Simulation time 517845181280 ps
CPU time 1714.63 seconds
Started Jun 28 07:09:54 PM PDT 24
Finished Jun 28 07:38:35 PM PDT 24
Peak memory 202192 kb
Host smart-a04780f3-c85a-43a9-8abb-fa2ad87133cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243511152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2243511152
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1318920783
Short name T596
Test name
Test status
Simulation time 191418959613 ps
CPU time 201.33 seconds
Started Jun 28 07:09:54 PM PDT 24
Finished Jun 28 07:13:22 PM PDT 24
Peak memory 210464 kb
Host smart-2c11f62f-7548-4e10-bff2-982f13e8f292
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318920783 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1318920783
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1707280890
Short name T738
Test name
Test status
Simulation time 496122672 ps
CPU time 1.8 seconds
Started Jun 28 07:10:16 PM PDT 24
Finished Jun 28 07:10:28 PM PDT 24
Peak memory 201616 kb
Host smart-aa738f03-e616-4b4d-9a30-1c6fba93d064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707280890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1707280890
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1835763624
Short name T170
Test name
Test status
Simulation time 563703331281 ps
CPU time 62 seconds
Started Jun 28 07:10:16 PM PDT 24
Finished Jun 28 07:11:27 PM PDT 24
Peak memory 201920 kb
Host smart-3e3413f7-1a96-4ab1-8955-787d4a45bb45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835763624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1835763624
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3277123711
Short name T327
Test name
Test status
Simulation time 365084149894 ps
CPU time 821.16 seconds
Started Jun 28 07:10:17 PM PDT 24
Finished Jun 28 07:24:08 PM PDT 24
Peak memory 201876 kb
Host smart-19136cd5-0cff-4c62-a77a-52f770e05fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277123711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3277123711
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2065169023
Short name T42
Test name
Test status
Simulation time 158455732684 ps
CPU time 106.52 seconds
Started Jun 28 07:10:18 PM PDT 24
Finished Jun 28 07:12:16 PM PDT 24
Peak memory 201944 kb
Host smart-e3f19577-6d5b-45eb-961d-6f7a9fadbaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065169023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2065169023
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2328128537
Short name T546
Test name
Test status
Simulation time 328216207040 ps
CPU time 723.18 seconds
Started Jun 28 07:10:20 PM PDT 24
Finished Jun 28 07:22:34 PM PDT 24
Peak memory 201856 kb
Host smart-d81150ce-5c20-43d3-9af1-8228e92bae83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328128537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2328128537
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3796757808
Short name T352
Test name
Test status
Simulation time 163197987734 ps
CPU time 383.4 seconds
Started Jun 28 07:09:53 PM PDT 24
Finished Jun 28 07:16:23 PM PDT 24
Peak memory 201852 kb
Host smart-5c09c613-d4a5-4c64-9366-800ba2a08cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796757808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3796757808
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.736399118
Short name T197
Test name
Test status
Simulation time 486310213762 ps
CPU time 1111.38 seconds
Started Jun 28 07:10:17 PM PDT 24
Finished Jun 28 07:28:58 PM PDT 24
Peak memory 201844 kb
Host smart-7a7ad560-b4dc-4134-997d-befe982c0489
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=736399118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.736399118
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2617209314
Short name T278
Test name
Test status
Simulation time 180681516914 ps
CPU time 109.41 seconds
Started Jun 28 07:10:20 PM PDT 24
Finished Jun 28 07:12:19 PM PDT 24
Peak memory 201884 kb
Host smart-892c3a8c-834e-4107-9866-44d21c328aef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617209314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2617209314
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.479785177
Short name T669
Test name
Test status
Simulation time 206834349069 ps
CPU time 112.84 seconds
Started Jun 28 07:10:17 PM PDT 24
Finished Jun 28 07:12:19 PM PDT 24
Peak memory 201860 kb
Host smart-31066ac2-2fec-4d49-87ab-62126ab55793
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479785177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.479785177
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3171484258
Short name T457
Test name
Test status
Simulation time 102413998572 ps
CPU time 339.38 seconds
Started Jun 28 07:10:17 PM PDT 24
Finished Jun 28 07:16:06 PM PDT 24
Peak memory 202208 kb
Host smart-bfaccce6-2fa3-4f11-b065-3b673d86e718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171484258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3171484258
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3286482775
Short name T29
Test name
Test status
Simulation time 46234056899 ps
CPU time 93.8 seconds
Started Jun 28 07:10:19 PM PDT 24
Finished Jun 28 07:12:04 PM PDT 24
Peak memory 201680 kb
Host smart-fa0fc41e-391b-4817-9ba0-96efd17ae63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286482775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3286482775
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1822371771
Short name T375
Test name
Test status
Simulation time 3935030073 ps
CPU time 2.78 seconds
Started Jun 28 07:10:20 PM PDT 24
Finished Jun 28 07:10:34 PM PDT 24
Peak memory 201688 kb
Host smart-15dad430-970e-4053-8182-9b124f086e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822371771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1822371771
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2115250135
Short name T700
Test name
Test status
Simulation time 5572970886 ps
CPU time 14.05 seconds
Started Jun 28 07:09:55 PM PDT 24
Finished Jun 28 07:10:15 PM PDT 24
Peak memory 201680 kb
Host smart-dfe09645-83c0-4560-8b30-a215321f7b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115250135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2115250135
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2707111410
Short name T269
Test name
Test status
Simulation time 186843867667 ps
CPU time 114.72 seconds
Started Jun 28 07:10:17 PM PDT 24
Finished Jun 28 07:12:21 PM PDT 24
Peak memory 201844 kb
Host smart-31e8e04a-003a-4502-85d4-96e3a4432267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707111410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2707111410
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3596871815
Short name T752
Test name
Test status
Simulation time 33792837733 ps
CPU time 72.28 seconds
Started Jun 28 07:10:18 PM PDT 24
Finished Jun 28 07:11:42 PM PDT 24
Peak memory 202368 kb
Host smart-1ec906b1-4ca4-4ed8-be36-dce77d9f475d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596871815 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3596871815
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2358492478
Short name T389
Test name
Test status
Simulation time 295580001 ps
CPU time 1.24 seconds
Started Jun 28 07:10:35 PM PDT 24
Finished Jun 28 07:10:47 PM PDT 24
Peak memory 201620 kb
Host smart-3508f9d6-3590-4049-add0-75afee32c479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358492478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2358492478
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3013926818
Short name T173
Test name
Test status
Simulation time 168874151789 ps
CPU time 83.74 seconds
Started Jun 28 07:10:34 PM PDT 24
Finished Jun 28 07:12:07 PM PDT 24
Peak memory 201792 kb
Host smart-c1e55706-4b5f-48ca-a558-04bbf8123bc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013926818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3013926818
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.4229678502
Short name T1
Test name
Test status
Simulation time 169800455765 ps
CPU time 376.85 seconds
Started Jun 28 07:10:36 PM PDT 24
Finished Jun 28 07:17:03 PM PDT 24
Peak memory 201876 kb
Host smart-3bb1c676-70f2-49f3-98d6-fd0a09b1d60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229678502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.4229678502
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3087092313
Short name T690
Test name
Test status
Simulation time 489113632384 ps
CPU time 542.94 seconds
Started Jun 28 07:10:19 PM PDT 24
Finished Jun 28 07:19:33 PM PDT 24
Peak memory 201952 kb
Host smart-8d5261e7-55cd-4f59-89a4-753b50f5ff1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087092313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3087092313
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1708248707
Short name T385
Test name
Test status
Simulation time 332048564884 ps
CPU time 358.18 seconds
Started Jun 28 07:10:19 PM PDT 24
Finished Jun 28 07:16:28 PM PDT 24
Peak memory 201864 kb
Host smart-d6be9e93-6c63-4a32-be1f-79be28eebb1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708248707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1708248707
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.618658487
Short name T156
Test name
Test status
Simulation time 495584245409 ps
CPU time 574.26 seconds
Started Jun 28 07:10:16 PM PDT 24
Finished Jun 28 07:20:00 PM PDT 24
Peak memory 201896 kb
Host smart-04c409fa-3ea6-4e04-8454-98a8adc72b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618658487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.618658487
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.124224036
Short name T541
Test name
Test status
Simulation time 329776265338 ps
CPU time 185.04 seconds
Started Jun 28 07:10:19 PM PDT 24
Finished Jun 28 07:13:35 PM PDT 24
Peak memory 201868 kb
Host smart-1f6becf4-0a7a-4e25-b7c5-7f820816fb0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=124224036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.124224036
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2740078344
Short name T281
Test name
Test status
Simulation time 343453286488 ps
CPU time 204.33 seconds
Started Jun 28 07:10:33 PM PDT 24
Finished Jun 28 07:14:07 PM PDT 24
Peak memory 201884 kb
Host smart-74913681-6a4e-462d-b249-5b4982e50130
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740078344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2740078344
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.756064942
Short name T492
Test name
Test status
Simulation time 211617627444 ps
CPU time 126.52 seconds
Started Jun 28 07:10:34 PM PDT 24
Finished Jun 28 07:12:50 PM PDT 24
Peak memory 201784 kb
Host smart-d420aee8-d5dc-44a3-abb6-4057a497648c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756064942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.756064942
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3898748120
Short name T221
Test name
Test status
Simulation time 142545805688 ps
CPU time 676.57 seconds
Started Jun 28 07:10:36 PM PDT 24
Finished Jun 28 07:22:03 PM PDT 24
Peak memory 202260 kb
Host smart-530a1c1c-f5fd-4abf-8896-4ff3f8dfdde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898748120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3898748120
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2586471559
Short name T549
Test name
Test status
Simulation time 38975748290 ps
CPU time 44.43 seconds
Started Jun 28 07:10:34 PM PDT 24
Finished Jun 28 07:11:27 PM PDT 24
Peak memory 201704 kb
Host smart-c082e92e-e7e0-4fa8-bd78-68417305cf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586471559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2586471559
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1800341752
Short name T582
Test name
Test status
Simulation time 4493462878 ps
CPU time 11.41 seconds
Started Jun 28 07:10:35 PM PDT 24
Finished Jun 28 07:10:56 PM PDT 24
Peak memory 201684 kb
Host smart-3b8338bc-6652-472f-8d1f-91c162ebb568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800341752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1800341752
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1712828158
Short name T446
Test name
Test status
Simulation time 5734882579 ps
CPU time 14.03 seconds
Started Jun 28 07:10:16 PM PDT 24
Finished Jun 28 07:10:38 PM PDT 24
Peak memory 201676 kb
Host smart-60cb2740-66b8-4f65-b359-a5154d7e2cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712828158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1712828158
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3708869750
Short name T693
Test name
Test status
Simulation time 34846582568 ps
CPU time 76.75 seconds
Started Jun 28 07:10:35 PM PDT 24
Finished Jun 28 07:12:03 PM PDT 24
Peak memory 201600 kb
Host smart-5cb2f7f5-a439-42d8-a9a2-9c5704f4d1ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708869750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3708869750
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2705492883
Short name T467
Test name
Test status
Simulation time 66838458106 ps
CPU time 176.29 seconds
Started Jun 28 07:10:33 PM PDT 24
Finished Jun 28 07:13:39 PM PDT 24
Peak memory 210724 kb
Host smart-4dafe844-7975-432a-a7f7-8cb542776517
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705492883 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2705492883
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.826359543
Short name T597
Test name
Test status
Simulation time 307801954 ps
CPU time 0.81 seconds
Started Jun 28 07:10:52 PM PDT 24
Finished Jun 28 07:11:01 PM PDT 24
Peak memory 201632 kb
Host smart-bb11e0d4-71ed-4dc1-b1ab-cbbba1f079ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826359543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.826359543
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.657468155
Short name T280
Test name
Test status
Simulation time 517398137490 ps
CPU time 1119.39 seconds
Started Jun 28 07:10:33 PM PDT 24
Finished Jun 28 07:29:21 PM PDT 24
Peak memory 201876 kb
Host smart-e27f7d29-bb89-42e6-8d6c-42fc74ecfe57
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657468155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.657468155
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3756305084
Short name T704
Test name
Test status
Simulation time 372706366418 ps
CPU time 787.04 seconds
Started Jun 28 07:10:32 PM PDT 24
Finished Jun 28 07:23:47 PM PDT 24
Peak memory 201892 kb
Host smart-276e12f9-e942-49f8-86c5-c9e387af5852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756305084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3756305084
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1525112250
Short name T463
Test name
Test status
Simulation time 164270041550 ps
CPU time 251.47 seconds
Started Jun 28 07:10:32 PM PDT 24
Finished Jun 28 07:14:52 PM PDT 24
Peak memory 201880 kb
Host smart-96017e2c-8d8a-428c-8143-689f79da9a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525112250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1525112250
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2347158261
Short name T713
Test name
Test status
Simulation time 496093879773 ps
CPU time 310.89 seconds
Started Jun 28 07:10:34 PM PDT 24
Finished Jun 28 07:15:54 PM PDT 24
Peak memory 201868 kb
Host smart-b604d220-d7c8-4fac-aa3e-67542ea0012a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347158261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2347158261
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2855655118
Short name T429
Test name
Test status
Simulation time 166535690285 ps
CPU time 95.45 seconds
Started Jun 28 07:10:37 PM PDT 24
Finished Jun 28 07:12:24 PM PDT 24
Peak memory 201928 kb
Host smart-22abf0e7-9020-4675-b135-0714be206c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855655118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2855655118
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3043399737
Short name T573
Test name
Test status
Simulation time 332249488945 ps
CPU time 376.07 seconds
Started Jun 28 07:10:34 PM PDT 24
Finished Jun 28 07:16:59 PM PDT 24
Peak memory 201800 kb
Host smart-a848d652-6fd2-4a21-8763-9e259f4eba8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043399737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3043399737
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2200994474
Short name T256
Test name
Test status
Simulation time 523408020638 ps
CPU time 1092.86 seconds
Started Jun 28 07:10:34 PM PDT 24
Finished Jun 28 07:28:56 PM PDT 24
Peak memory 201952 kb
Host smart-beac4d22-67d6-4b3f-8713-0107b4ed3e42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200994474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2200994474
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2500815364
Short name T419
Test name
Test status
Simulation time 404547888512 ps
CPU time 742.63 seconds
Started Jun 28 07:10:34 PM PDT 24
Finished Jun 28 07:23:05 PM PDT 24
Peak memory 201832 kb
Host smart-92bf6d84-db7e-44ee-b1bc-60545f3015c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500815364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2500815364
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1444686572
Short name T802
Test name
Test status
Simulation time 77105530129 ps
CPU time 306.78 seconds
Started Jun 28 07:10:33 PM PDT 24
Finished Jun 28 07:15:49 PM PDT 24
Peak memory 202204 kb
Host smart-8433ff63-0398-4930-9f7d-f5938cebcc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444686572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1444686572
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3388451153
Short name T744
Test name
Test status
Simulation time 26571829137 ps
CPU time 38.88 seconds
Started Jun 28 07:10:35 PM PDT 24
Finished Jun 28 07:11:23 PM PDT 24
Peak memory 201684 kb
Host smart-1f8a7ecd-7f51-4972-bf73-a93cf309ad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388451153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3388451153
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1597831705
Short name T458
Test name
Test status
Simulation time 4055259636 ps
CPU time 5.15 seconds
Started Jun 28 07:10:36 PM PDT 24
Finished Jun 28 07:10:52 PM PDT 24
Peak memory 201684 kb
Host smart-217e61c0-4905-442e-b9d3-d1153bf2f271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597831705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1597831705
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1764577228
Short name T620
Test name
Test status
Simulation time 5815153962 ps
CPU time 13.57 seconds
Started Jun 28 07:10:37 PM PDT 24
Finished Jun 28 07:11:02 PM PDT 24
Peak memory 201676 kb
Host smart-526124ec-cf20-4f7e-a7c6-d70092fcf6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764577228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1764577228
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2077952906
Short name T778
Test name
Test status
Simulation time 266699695258 ps
CPU time 588.34 seconds
Started Jun 28 07:10:52 PM PDT 24
Finished Jun 28 07:20:48 PM PDT 24
Peak memory 210368 kb
Host smart-e0688579-5084-4049-a805-a87ba01eb6da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077952906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2077952906
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3148388899
Short name T526
Test name
Test status
Simulation time 411349627 ps
CPU time 1.11 seconds
Started Jun 28 07:10:53 PM PDT 24
Finished Jun 28 07:11:01 PM PDT 24
Peak memory 201628 kb
Host smart-0decfde9-548f-4580-8abc-3460d14b58fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148388899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3148388899
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3943696042
Short name T777
Test name
Test status
Simulation time 371042657204 ps
CPU time 878.06 seconds
Started Jun 28 07:10:53 PM PDT 24
Finished Jun 28 07:25:39 PM PDT 24
Peak memory 201864 kb
Host smart-e8b38ae6-3191-4e2a-b417-d4ff4a4daf95
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943696042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3943696042
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3819201580
Short name T243
Test name
Test status
Simulation time 167166017765 ps
CPU time 91.41 seconds
Started Jun 28 07:10:53 PM PDT 24
Finished Jun 28 07:12:32 PM PDT 24
Peak memory 201952 kb
Host smart-c273fd31-888c-47e1-ab32-d376a86be0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819201580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3819201580
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.4131093977
Short name T592
Test name
Test status
Simulation time 316774252059 ps
CPU time 168.03 seconds
Started Jun 28 07:10:54 PM PDT 24
Finished Jun 28 07:13:49 PM PDT 24
Peak memory 201856 kb
Host smart-3bbe6baf-3d77-46d6-b7a0-3ec511bf7675
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131093977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.4131093977
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1147477956
Short name T241
Test name
Test status
Simulation time 168158069010 ps
CPU time 191.21 seconds
Started Jun 28 07:10:54 PM PDT 24
Finished Jun 28 07:14:12 PM PDT 24
Peak memory 201944 kb
Host smart-711030e8-3699-4f0a-8a29-921d0893b4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147477956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1147477956
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.4044038578
Short name T162
Test name
Test status
Simulation time 341926351613 ps
CPU time 211.94 seconds
Started Jun 28 07:10:53 PM PDT 24
Finished Jun 28 07:14:32 PM PDT 24
Peak memory 201904 kb
Host smart-32becc98-203d-4102-a471-52b9c2edd99c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044038578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.4044038578
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.605061473
Short name T646
Test name
Test status
Simulation time 346236364093 ps
CPU time 588.96 seconds
Started Jun 28 07:10:52 PM PDT 24
Finished Jun 28 07:20:49 PM PDT 24
Peak memory 201948 kb
Host smart-fbb123e9-c640-4e51-b167-42a8a48de957
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605061473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.605061473
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2745892114
Short name T720
Test name
Test status
Simulation time 197930957948 ps
CPU time 109.53 seconds
Started Jun 28 07:10:53 PM PDT 24
Finished Jun 28 07:12:50 PM PDT 24
Peak memory 201908 kb
Host smart-6bcbd44d-1851-4f61-a881-f03dc57d1368
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745892114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2745892114
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3660253247
Short name T185
Test name
Test status
Simulation time 99042867922 ps
CPU time 267.02 seconds
Started Jun 28 07:10:52 PM PDT 24
Finished Jun 28 07:15:27 PM PDT 24
Peak memory 202204 kb
Host smart-e62b97dd-a1f8-4fa9-b2d5-e7a38ea64ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660253247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3660253247
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.833353682
Short name T644
Test name
Test status
Simulation time 35135907489 ps
CPU time 41.34 seconds
Started Jun 28 07:10:53 PM PDT 24
Finished Jun 28 07:11:41 PM PDT 24
Peak memory 201652 kb
Host smart-b4e854a6-b877-40fb-ad79-bd47b4346751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833353682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.833353682
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3149780101
Short name T438
Test name
Test status
Simulation time 3148613704 ps
CPU time 3.87 seconds
Started Jun 28 07:10:54 PM PDT 24
Finished Jun 28 07:11:05 PM PDT 24
Peak memory 201668 kb
Host smart-6de1cac6-f190-46c2-998d-3afb5a1b935d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149780101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3149780101
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1366064274
Short name T516
Test name
Test status
Simulation time 5937011695 ps
CPU time 12.96 seconds
Started Jun 28 07:10:54 PM PDT 24
Finished Jun 28 07:11:14 PM PDT 24
Peak memory 201680 kb
Host smart-a15d82d1-5f7d-42dc-b8ed-040770840b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366064274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1366064274
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1406822801
Short name T134
Test name
Test status
Simulation time 330778439669 ps
CPU time 124.37 seconds
Started Jun 28 07:10:51 PM PDT 24
Finished Jun 28 07:13:04 PM PDT 24
Peak memory 201860 kb
Host smart-4acdd48c-7afa-4be6-85e2-e9962f114f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406822801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1406822801
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2570950295
Short name T769
Test name
Test status
Simulation time 62815332324 ps
CPU time 147.71 seconds
Started Jun 28 07:10:53 PM PDT 24
Finished Jun 28 07:13:28 PM PDT 24
Peak memory 210260 kb
Host smart-ca0f673c-de47-4cdf-97ec-f200594faa49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570950295 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2570950295
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.62177731
Short name T695
Test name
Test status
Simulation time 401859485 ps
CPU time 0.91 seconds
Started Jun 28 07:11:13 PM PDT 24
Finished Jun 28 07:11:19 PM PDT 24
Peak memory 201652 kb
Host smart-1fd92731-0752-46b7-ab48-57dbdfa1e6c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62177731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.62177731
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2525052824
Short name T337
Test name
Test status
Simulation time 174186357863 ps
CPU time 12.25 seconds
Started Jun 28 07:11:12 PM PDT 24
Finished Jun 28 07:11:28 PM PDT 24
Peak memory 201856 kb
Host smart-efa09ee7-ad67-4639-9068-e145c57f0526
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525052824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2525052824
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.4216805197
Short name T341
Test name
Test status
Simulation time 186798881954 ps
CPU time 220.52 seconds
Started Jun 28 07:11:13 PM PDT 24
Finished Jun 28 07:14:59 PM PDT 24
Peak memory 201804 kb
Host smart-311b639b-e74e-4dcc-ba44-e57c196d6997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216805197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.4216805197
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.577489453
Short name T157
Test name
Test status
Simulation time 488222606514 ps
CPU time 293.71 seconds
Started Jun 28 07:11:13 PM PDT 24
Finished Jun 28 07:16:12 PM PDT 24
Peak memory 202044 kb
Host smart-c5a0073c-967c-403c-8ac0-9bc8d4ae3a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577489453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.577489453
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1737673854
Short name T430
Test name
Test status
Simulation time 490284428981 ps
CPU time 511.7 seconds
Started Jun 28 07:11:11 PM PDT 24
Finished Jun 28 07:19:46 PM PDT 24
Peak memory 201820 kb
Host smart-08e05a3d-ce8a-4fef-b344-be064a1c0090
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737673854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1737673854
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3221918455
Short name T275
Test name
Test status
Simulation time 165705770609 ps
CPU time 57.68 seconds
Started Jun 28 07:11:11 PM PDT 24
Finished Jun 28 07:12:12 PM PDT 24
Peak memory 201904 kb
Host smart-560b3c61-338a-4d35-863d-ff4ffb3ddaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221918455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3221918455
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2325329491
Short name T553
Test name
Test status
Simulation time 332356034166 ps
CPU time 811.85 seconds
Started Jun 28 07:11:13 PM PDT 24
Finished Jun 28 07:24:49 PM PDT 24
Peak memory 201860 kb
Host smart-eee3b4af-a509-469a-b556-683d8578ea75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325329491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2325329491
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.491779717
Short name T178
Test name
Test status
Simulation time 380554387227 ps
CPU time 104.54 seconds
Started Jun 28 07:11:12 PM PDT 24
Finished Jun 28 07:13:00 PM PDT 24
Peak memory 201884 kb
Host smart-0dc79620-50f5-4dc9-b6e8-06a46a5a3258
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491779717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.491779717
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3360587527
Short name T12
Test name
Test status
Simulation time 204134832953 ps
CPU time 459.02 seconds
Started Jun 28 07:11:12 PM PDT 24
Finished Jun 28 07:18:55 PM PDT 24
Peak memory 201856 kb
Host smart-3c8b5d62-169d-40eb-9205-dd8ae2f9b963
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360587527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3360587527
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2696318875
Short name T483
Test name
Test status
Simulation time 113730184076 ps
CPU time 516.45 seconds
Started Jun 28 07:11:15 PM PDT 24
Finished Jun 28 07:19:56 PM PDT 24
Peak memory 202196 kb
Host smart-1eb14b53-98d7-46dd-9656-8bb1105ac580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696318875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2696318875
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.45332895
Short name T625
Test name
Test status
Simulation time 42222091702 ps
CPU time 18.63 seconds
Started Jun 28 07:11:13 PM PDT 24
Finished Jun 28 07:11:36 PM PDT 24
Peak memory 201684 kb
Host smart-c4094db8-1167-4160-b324-9d17c8637a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45332895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.45332895
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.743156792
Short name T171
Test name
Test status
Simulation time 4017012327 ps
CPU time 9.81 seconds
Started Jun 28 07:11:12 PM PDT 24
Finished Jun 28 07:11:26 PM PDT 24
Peak memory 201672 kb
Host smart-acf8923b-c7b8-49fe-939f-588a8b211c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743156792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.743156792
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1249704554
Short name T383
Test name
Test status
Simulation time 6069277481 ps
CPU time 4.7 seconds
Started Jun 28 07:11:14 PM PDT 24
Finished Jun 28 07:11:23 PM PDT 24
Peak memory 201680 kb
Host smart-78b41939-78ff-4eb9-a250-acba285de19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249704554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1249704554
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.743950112
Short name T521
Test name
Test status
Simulation time 185829904307 ps
CPU time 82.98 seconds
Started Jun 28 07:11:12 PM PDT 24
Finished Jun 28 07:12:39 PM PDT 24
Peak memory 201872 kb
Host smart-4d63b3c9-5f9c-4a13-85c4-9ba59fd5a053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743950112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
743950112
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3918981947
Short name T730
Test name
Test status
Simulation time 392478152 ps
CPU time 0.89 seconds
Started Jun 28 07:11:30 PM PDT 24
Finished Jun 28 07:11:34 PM PDT 24
Peak memory 201632 kb
Host smart-6b4245b3-0bea-43fc-995c-665e79bf8203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918981947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3918981947
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1195910100
Short name T562
Test name
Test status
Simulation time 346765654305 ps
CPU time 378.56 seconds
Started Jun 28 07:11:31 PM PDT 24
Finished Jun 28 07:17:53 PM PDT 24
Peak memory 201872 kb
Host smart-0644872d-b3cd-4163-ba5f-967543249e50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195910100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1195910100
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1110948375
Short name T299
Test name
Test status
Simulation time 507513756898 ps
CPU time 867.7 seconds
Started Jun 28 07:11:34 PM PDT 24
Finished Jun 28 07:26:05 PM PDT 24
Peak memory 201864 kb
Host smart-905525c8-b147-400b-b5c9-190293dd1ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110948375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1110948375
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2043332467
Short name T590
Test name
Test status
Simulation time 162515101305 ps
CPU time 104.77 seconds
Started Jun 28 07:11:31 PM PDT 24
Finished Jun 28 07:13:20 PM PDT 24
Peak memory 201936 kb
Host smart-0f5b9ef5-22f4-47aa-b34e-5be1fbf2eac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043332467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2043332467
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2669385226
Short name T703
Test name
Test status
Simulation time 483168214981 ps
CPU time 304.34 seconds
Started Jun 28 07:11:32 PM PDT 24
Finished Jun 28 07:16:40 PM PDT 24
Peak memory 201856 kb
Host smart-f480ad2b-d081-482a-9b23-40f63b5e72e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669385226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2669385226
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.299850008
Short name T80
Test name
Test status
Simulation time 322421940034 ps
CPU time 778.58 seconds
Started Jun 28 07:11:12 PM PDT 24
Finished Jun 28 07:24:15 PM PDT 24
Peak memory 201940 kb
Host smart-e00252b9-2749-4a06-90fc-9e93a2f4b6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299850008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.299850008
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1872307006
Short name T514
Test name
Test status
Simulation time 163999105402 ps
CPU time 96.32 seconds
Started Jun 28 07:11:14 PM PDT 24
Finished Jun 28 07:12:54 PM PDT 24
Peak memory 201900 kb
Host smart-12ffd6ae-0182-45fc-888d-75c3b1ea3bae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872307006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1872307006
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1349312258
Short name T756
Test name
Test status
Simulation time 614259574124 ps
CPU time 773.19 seconds
Started Jun 28 07:11:31 PM PDT 24
Finished Jun 28 07:24:27 PM PDT 24
Peak memory 201888 kb
Host smart-e01bb078-4ece-4d18-ba95-14b2c79260d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349312258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1349312258
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1618394383
Short name T485
Test name
Test status
Simulation time 394888866992 ps
CPU time 446.88 seconds
Started Jun 28 07:11:32 PM PDT 24
Finished Jun 28 07:19:03 PM PDT 24
Peak memory 201980 kb
Host smart-65b6c376-fed6-4309-a125-3f5f12e37dda
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618394383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1618394383
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3769505971
Short name T229
Test name
Test status
Simulation time 119071576443 ps
CPU time 675.85 seconds
Started Jun 28 07:11:32 PM PDT 24
Finished Jun 28 07:22:52 PM PDT 24
Peak memory 202136 kb
Host smart-4cf94370-4a1f-4eae-8f27-df0b1f20ca9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769505971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3769505971
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2600956995
Short name T454
Test name
Test status
Simulation time 39697468596 ps
CPU time 87.85 seconds
Started Jun 28 07:11:30 PM PDT 24
Finished Jun 28 07:13:00 PM PDT 24
Peak memory 201680 kb
Host smart-6daa442f-3248-4a35-b225-2b1e5d1ef3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600956995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2600956995
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2013081254
Short name T411
Test name
Test status
Simulation time 4817215599 ps
CPU time 6.47 seconds
Started Jun 28 07:11:32 PM PDT 24
Finished Jun 28 07:11:42 PM PDT 24
Peak memory 201688 kb
Host smart-ed3453b9-436a-42e7-98f2-c58198811498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013081254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2013081254
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.868535266
Short name T684
Test name
Test status
Simulation time 5976933980 ps
CPU time 4.34 seconds
Started Jun 28 07:11:14 PM PDT 24
Finished Jun 28 07:11:22 PM PDT 24
Peak memory 201676 kb
Host smart-161eb866-1afc-4ccf-a931-69875bedb664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868535266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.868535266
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1884715771
Short name T211
Test name
Test status
Simulation time 49881996718 ps
CPU time 59.66 seconds
Started Jun 28 07:11:31 PM PDT 24
Finished Jun 28 07:12:34 PM PDT 24
Peak memory 201676 kb
Host smart-a0f53142-594f-4abb-8076-57c84d56d01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884715771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1884715771
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1640699489
Short name T656
Test name
Test status
Simulation time 117189619118 ps
CPU time 300.06 seconds
Started Jun 28 07:11:31 PM PDT 24
Finished Jun 28 07:16:35 PM PDT 24
Peak memory 210504 kb
Host smart-5d7f2d3e-721c-4c5d-83a9-3a855caa8313
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640699489 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1640699489
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.121304777
Short name T718
Test name
Test status
Simulation time 457307323 ps
CPU time 1.12 seconds
Started Jun 28 07:00:07 PM PDT 24
Finished Jun 28 07:00:13 PM PDT 24
Peak memory 201632 kb
Host smart-715f5e08-2f8d-4d7c-9560-ff6c4908aac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121304777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.121304777
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3335344815
Short name T740
Test name
Test status
Simulation time 159746739157 ps
CPU time 333.39 seconds
Started Jun 28 07:00:07 PM PDT 24
Finished Jun 28 07:05:46 PM PDT 24
Peak memory 201928 kb
Host smart-69f4de43-c613-49e9-a014-5c15f770ebc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335344815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3335344815
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3229200279
Short name T247
Test name
Test status
Simulation time 161695403345 ps
CPU time 98.76 seconds
Started Jun 28 07:00:05 PM PDT 24
Finished Jun 28 07:01:48 PM PDT 24
Peak memory 201840 kb
Host smart-b1b981c6-640f-4434-9f4f-00a615c6c938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229200279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3229200279
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2176348312
Short name T764
Test name
Test status
Simulation time 163796964715 ps
CPU time 107.78 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:01:59 PM PDT 24
Peak memory 201876 kb
Host smart-b8505006-dc16-41fd-80e2-9c159b9180a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176348312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2176348312
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2674587847
Short name T629
Test name
Test status
Simulation time 327101834594 ps
CPU time 383.36 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:06:33 PM PDT 24
Peak memory 201932 kb
Host smart-ffcbf87f-9ae0-4d4f-9339-07dd1ab0781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674587847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2674587847
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.85151057
Short name T611
Test name
Test status
Simulation time 499585201724 ps
CPU time 247.84 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:04:18 PM PDT 24
Peak memory 201848 kb
Host smart-6c69366c-caf7-4b9c-89b7-ffc0f683c23c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=85151057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.85151057
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2372122788
Short name T702
Test name
Test status
Simulation time 535189332262 ps
CPU time 1156.02 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:19:27 PM PDT 24
Peak memory 201892 kb
Host smart-132092db-c7c2-44da-8349-49183d88421e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372122788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2372122788
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1108200449
Short name T615
Test name
Test status
Simulation time 204616038810 ps
CPU time 452.26 seconds
Started Jun 28 07:00:07 PM PDT 24
Finished Jun 28 07:07:45 PM PDT 24
Peak memory 201920 kb
Host smart-74286650-8d1b-456e-a5cc-82a1be5a0700
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108200449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1108200449
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.359180142
Short name T407
Test name
Test status
Simulation time 31544097723 ps
CPU time 71.38 seconds
Started Jun 28 07:00:05 PM PDT 24
Finished Jun 28 07:01:20 PM PDT 24
Peak memory 201704 kb
Host smart-2135ce6a-05ac-49ed-bfd3-884fa7dbd86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359180142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.359180142
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.375566185
Short name T610
Test name
Test status
Simulation time 3796224021 ps
CPU time 6.01 seconds
Started Jun 28 07:00:07 PM PDT 24
Finished Jun 28 07:00:20 PM PDT 24
Peak memory 201700 kb
Host smart-75fd63d4-16fb-46d1-9a2a-49138d131b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375566185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.375566185
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3130617021
Short name T75
Test name
Test status
Simulation time 8400862907 ps
CPU time 2.21 seconds
Started Jun 28 07:00:04 PM PDT 24
Finished Jun 28 07:00:10 PM PDT 24
Peak memory 218384 kb
Host smart-24bcae1b-6c94-4808-badc-df05b9e95bd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130617021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3130617021
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3559801512
Short name T398
Test name
Test status
Simulation time 6089702211 ps
CPU time 15.49 seconds
Started Jun 28 07:00:05 PM PDT 24
Finished Jun 28 07:00:24 PM PDT 24
Peak memory 201668 kb
Host smart-077a0f7e-83f8-4d4e-be8d-4ffb53b0ad81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559801512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3559801512
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3080793444
Short name T231
Test name
Test status
Simulation time 170033542473 ps
CPU time 46.76 seconds
Started Jun 28 07:00:04 PM PDT 24
Finished Jun 28 07:00:54 PM PDT 24
Peak memory 201844 kb
Host smart-fdc70d38-897b-45e0-9e2f-d55f7bc2ff9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080793444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3080793444
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.827557193
Short name T780
Test name
Test status
Simulation time 314586505 ps
CPU time 0.97 seconds
Started Jun 28 07:12:04 PM PDT 24
Finished Jun 28 07:12:09 PM PDT 24
Peak memory 201628 kb
Host smart-8be55f12-6e2b-4821-aee5-548dd6ab3de7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827557193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.827557193
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2916082576
Short name T318
Test name
Test status
Simulation time 324671958004 ps
CPU time 77.2 seconds
Started Jun 28 07:12:04 PM PDT 24
Finished Jun 28 07:13:26 PM PDT 24
Peak memory 201884 kb
Host smart-7f3f650e-7cd3-46dc-addb-d444fc1b2075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916082576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2916082576
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1629885513
Short name T630
Test name
Test status
Simulation time 495820343630 ps
CPU time 1136.63 seconds
Started Jun 28 07:12:06 PM PDT 24
Finished Jun 28 07:31:07 PM PDT 24
Peak memory 201856 kb
Host smart-ea98d18d-20d4-405b-a678-427b9996e922
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629885513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1629885513
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2906757162
Short name T319
Test name
Test status
Simulation time 495377625968 ps
CPU time 200.36 seconds
Started Jun 28 07:12:05 PM PDT 24
Finished Jun 28 07:15:30 PM PDT 24
Peak memory 201936 kb
Host smart-71804504-8a93-4f48-b0ea-2e841b9bf045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906757162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2906757162
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2075946444
Short name T199
Test name
Test status
Simulation time 501334796983 ps
CPU time 1039.21 seconds
Started Jun 28 07:12:04 PM PDT 24
Finished Jun 28 07:29:28 PM PDT 24
Peak memory 201836 kb
Host smart-c3f9db7d-04d1-4a8b-bb1d-da8e9574b6c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075946444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2075946444
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2401481967
Short name T781
Test name
Test status
Simulation time 166077202950 ps
CPU time 62.4 seconds
Started Jun 28 07:12:03 PM PDT 24
Finished Jun 28 07:13:09 PM PDT 24
Peak memory 201888 kb
Host smart-580c1e33-ed90-46f1-b133-7e667493307c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401481967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2401481967
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4248713405
Short name T187
Test name
Test status
Simulation time 403487366905 ps
CPU time 794.86 seconds
Started Jun 28 07:12:04 PM PDT 24
Finished Jun 28 07:25:22 PM PDT 24
Peak memory 201852 kb
Host smart-5627b235-84e7-4e84-a1d7-f1a6fa119b64
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248713405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4248713405
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.108741778
Short name T722
Test name
Test status
Simulation time 80625993090 ps
CPU time 289.29 seconds
Started Jun 28 07:12:05 PM PDT 24
Finished Jun 28 07:16:59 PM PDT 24
Peak memory 202204 kb
Host smart-989e5e57-a92d-4e81-9d71-fd1c7f88d52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108741778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.108741778
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.301201368
Short name T434
Test name
Test status
Simulation time 34458496469 ps
CPU time 75.39 seconds
Started Jun 28 07:12:04 PM PDT 24
Finished Jun 28 07:13:23 PM PDT 24
Peak memory 201668 kb
Host smart-9b78369b-9985-408e-97cf-f01d12d1eac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301201368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.301201368
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.4177668753
Short name T475
Test name
Test status
Simulation time 4691590704 ps
CPU time 1.86 seconds
Started Jun 28 07:12:04 PM PDT 24
Finished Jun 28 07:12:10 PM PDT 24
Peak memory 201680 kb
Host smart-b00d2f4b-51c0-47fe-86fa-4e611a6f9ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177668753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.4177668753
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.346585202
Short name T527
Test name
Test status
Simulation time 5819029523 ps
CPU time 4.63 seconds
Started Jun 28 07:12:05 PM PDT 24
Finished Jun 28 07:12:14 PM PDT 24
Peak memory 201700 kb
Host smart-986082e5-e1c8-469f-b619-13f9d69dc527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346585202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.346585202
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.763534287
Short name T164
Test name
Test status
Simulation time 353389833974 ps
CPU time 821.46 seconds
Started Jun 28 07:12:05 PM PDT 24
Finished Jun 28 07:25:50 PM PDT 24
Peak memory 201900 kb
Host smart-3600e6f5-bd70-4bb7-afe0-e073e6247b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763534287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
763534287
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.4031373696
Short name T624
Test name
Test status
Simulation time 379251016 ps
CPU time 0.85 seconds
Started Jun 28 07:13:26 PM PDT 24
Finished Jun 28 07:13:33 PM PDT 24
Peak memory 201624 kb
Host smart-4c694dab-3f5c-4b13-b141-a4b6ca44767b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031373696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.4031373696
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2295832769
Short name T649
Test name
Test status
Simulation time 532404254354 ps
CPU time 373.6 seconds
Started Jun 28 07:13:26 PM PDT 24
Finished Jun 28 07:19:47 PM PDT 24
Peak memory 201984 kb
Host smart-f860e8be-03aa-4777-aa2d-db59a604135c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295832769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2295832769
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.124009177
Short name T306
Test name
Test status
Simulation time 285606161868 ps
CPU time 155.02 seconds
Started Jun 28 07:13:26 PM PDT 24
Finished Jun 28 07:16:08 PM PDT 24
Peak memory 201888 kb
Host smart-acf38276-50c2-42b9-b6a5-0034ea6c0fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124009177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.124009177
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.314342595
Short name T252
Test name
Test status
Simulation time 330515171630 ps
CPU time 817.71 seconds
Started Jun 28 07:13:27 PM PDT 24
Finished Jun 28 07:27:12 PM PDT 24
Peak memory 201848 kb
Host smart-39e43f4a-a19d-4065-a7cf-2912b25142f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=314342595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.314342595
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2173144244
Short name T151
Test name
Test status
Simulation time 329114348495 ps
CPU time 74.61 seconds
Started Jun 28 07:12:05 PM PDT 24
Finished Jun 28 07:13:24 PM PDT 24
Peak memory 201884 kb
Host smart-4fe34da0-3254-46a8-af0d-09cc506a440c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173144244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2173144244
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2714889100
Short name T674
Test name
Test status
Simulation time 158575432982 ps
CPU time 88.25 seconds
Started Jun 28 07:12:04 PM PDT 24
Finished Jun 28 07:13:37 PM PDT 24
Peak memory 201876 kb
Host smart-a70e32a4-de69-41bb-bb5a-9aa435c4c22f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714889100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2714889100
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3395833680
Short name T499
Test name
Test status
Simulation time 199565071899 ps
CPU time 42.49 seconds
Started Jun 28 07:13:26 PM PDT 24
Finished Jun 28 07:14:16 PM PDT 24
Peak memory 201844 kb
Host smart-321cabdb-a92d-49f5-a71c-d52b64cd4ff5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395833680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3395833680
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.622798912
Short name T503
Test name
Test status
Simulation time 117000162455 ps
CPU time 503.02 seconds
Started Jun 28 07:13:29 PM PDT 24
Finished Jun 28 07:21:59 PM PDT 24
Peak memory 202212 kb
Host smart-e9e79e75-88e0-4024-b2d9-3395ac877aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622798912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.622798912
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1144345024
Short name T195
Test name
Test status
Simulation time 33171073998 ps
CPU time 66.57 seconds
Started Jun 28 07:13:28 PM PDT 24
Finished Jun 28 07:14:42 PM PDT 24
Peak memory 201688 kb
Host smart-4925728f-c015-432c-ad61-6318f9fa6a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144345024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1144345024
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.4233132426
Short name T509
Test name
Test status
Simulation time 3116455856 ps
CPU time 2.4 seconds
Started Jun 28 07:13:29 PM PDT 24
Finished Jun 28 07:13:38 PM PDT 24
Peak memory 201656 kb
Host smart-b4e8e99b-d539-4eb0-8f52-8c9ffee63d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233132426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.4233132426
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2029892790
Short name T392
Test name
Test status
Simulation time 5653912710 ps
CPU time 13.19 seconds
Started Jun 28 07:12:05 PM PDT 24
Finished Jun 28 07:12:22 PM PDT 24
Peak memory 201600 kb
Host smart-2a9657a2-2485-4fd5-b663-622f9d01bc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029892790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2029892790
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1616362835
Short name T595
Test name
Test status
Simulation time 305693402 ps
CPU time 1.34 seconds
Started Jun 28 07:13:28 PM PDT 24
Finished Jun 28 07:13:36 PM PDT 24
Peak memory 201640 kb
Host smart-18df4260-4a5e-4151-b440-9655b4c16904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616362835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1616362835
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.15250987
Short name T253
Test name
Test status
Simulation time 167762142160 ps
CPU time 107.22 seconds
Started Jun 28 07:13:28 PM PDT 24
Finished Jun 28 07:15:22 PM PDT 24
Peak memory 201864 kb
Host smart-c6cf6f00-09ad-425b-ad1d-8d2fd4142171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15250987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.15250987
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.953318639
Short name T783
Test name
Test status
Simulation time 168052660059 ps
CPU time 92.32 seconds
Started Jun 28 07:13:22 PM PDT 24
Finished Jun 28 07:14:57 PM PDT 24
Peak memory 201872 kb
Host smart-0d5c730f-01fb-45db-95d5-48a9ff69e6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953318639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.953318639
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2382061884
Short name T638
Test name
Test status
Simulation time 162130684423 ps
CPU time 212.41 seconds
Started Jun 28 07:13:21 PM PDT 24
Finished Jun 28 07:16:56 PM PDT 24
Peak memory 201856 kb
Host smart-ec703c67-672b-46bc-a0ca-3eb1cc86dbc8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382061884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2382061884
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1217931641
Short name T312
Test name
Test status
Simulation time 327415155022 ps
CPU time 373.18 seconds
Started Jun 28 07:13:27 PM PDT 24
Finished Jun 28 07:19:48 PM PDT 24
Peak memory 201888 kb
Host smart-70cf6026-527b-45bb-a339-3d4decc70de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217931641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1217931641
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.589769114
Short name T450
Test name
Test status
Simulation time 165249133091 ps
CPU time 353.48 seconds
Started Jun 28 07:13:27 PM PDT 24
Finished Jun 28 07:19:28 PM PDT 24
Peak memory 201856 kb
Host smart-15ef5198-9e6d-4f16-abf7-904f815211ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=589769114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.589769114
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.531812861
Short name T140
Test name
Test status
Simulation time 510702038881 ps
CPU time 160.52 seconds
Started Jun 28 07:13:27 PM PDT 24
Finished Jun 28 07:16:15 PM PDT 24
Peak memory 201860 kb
Host smart-020ed959-0b1c-46df-bad2-6fcd9473733c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531812861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.531812861
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1032950961
Short name T145
Test name
Test status
Simulation time 191081838795 ps
CPU time 437.38 seconds
Started Jun 28 07:13:27 PM PDT 24
Finished Jun 28 07:20:52 PM PDT 24
Peak memory 201860 kb
Host smart-ea8f93f7-c9b9-42c3-9b5b-17d3a3f16245
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032950961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1032950961
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3667341915
Short name T598
Test name
Test status
Simulation time 94640215774 ps
CPU time 340.52 seconds
Started Jun 28 07:13:28 PM PDT 24
Finished Jun 28 07:19:16 PM PDT 24
Peak memory 202192 kb
Host smart-a0ad2082-9a62-4f53-aef8-f41af894446d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667341915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3667341915
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3554428039
Short name T468
Test name
Test status
Simulation time 36329679550 ps
CPU time 13.96 seconds
Started Jun 28 07:13:28 PM PDT 24
Finished Jun 28 07:13:50 PM PDT 24
Peak memory 201700 kb
Host smart-6d0046e3-c1ac-4bab-bae5-31642a0e6a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554428039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3554428039
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2248243897
Short name T507
Test name
Test status
Simulation time 4006291626 ps
CPU time 2.91 seconds
Started Jun 28 07:13:29 PM PDT 24
Finished Jun 28 07:13:39 PM PDT 24
Peak memory 201684 kb
Host smart-0b7d133d-00cd-463a-8a41-8f158ea853b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248243897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2248243897
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3775456474
Short name T391
Test name
Test status
Simulation time 5649767632 ps
CPU time 13.06 seconds
Started Jun 28 07:13:27 PM PDT 24
Finished Jun 28 07:13:48 PM PDT 24
Peak memory 201664 kb
Host smart-db5bcdb5-5684-4498-8242-904b1544d7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775456474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3775456474
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.499462992
Short name T708
Test name
Test status
Simulation time 275365562519 ps
CPU time 526.22 seconds
Started Jun 28 07:13:25 PM PDT 24
Finished Jun 28 07:22:18 PM PDT 24
Peak memory 202244 kb
Host smart-9236fb51-457c-4f54-bf7e-af4cf62071d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499462992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
499462992
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2722059645
Short name T14
Test name
Test status
Simulation time 58839213752 ps
CPU time 121.35 seconds
Started Jun 28 07:13:27 PM PDT 24
Finished Jun 28 07:15:36 PM PDT 24
Peak memory 210268 kb
Host smart-01aed4c5-8aa1-4b8a-9360-1a510f807b01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722059645 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2722059645
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1081211778
Short name T513
Test name
Test status
Simulation time 498969595 ps
CPU time 0.83 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:13:59 PM PDT 24
Peak memory 201620 kb
Host smart-ede0d5d5-ed5d-4306-8444-62acc54ebac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081211778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1081211778
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1397334912
Short name T759
Test name
Test status
Simulation time 203943976954 ps
CPU time 95.74 seconds
Started Jun 28 07:13:27 PM PDT 24
Finished Jun 28 07:15:10 PM PDT 24
Peak memory 201872 kb
Host smart-35aed180-1d46-475f-944a-2c01c4d1fcb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397334912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1397334912
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2345839774
Short name T237
Test name
Test status
Simulation time 167658371197 ps
CPU time 361.12 seconds
Started Jun 28 07:14:00 PM PDT 24
Finished Jun 28 07:20:06 PM PDT 24
Peak memory 201892 kb
Host smart-e043c113-abb7-4c04-aaa4-0726d2e34730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345839774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2345839774
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3281853157
Short name T614
Test name
Test status
Simulation time 160218776052 ps
CPU time 343.52 seconds
Started Jun 28 07:13:27 PM PDT 24
Finished Jun 28 07:19:18 PM PDT 24
Peak memory 201900 kb
Host smart-be106353-bede-4695-ae3b-d5044f00fd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281853157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3281853157
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3710222411
Short name T534
Test name
Test status
Simulation time 169568644525 ps
CPU time 42.94 seconds
Started Jun 28 07:13:28 PM PDT 24
Finished Jun 28 07:14:18 PM PDT 24
Peak memory 201848 kb
Host smart-4a438c79-2bf5-4087-a811-7dd4eda4f061
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710222411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3710222411
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2186506564
Short name T425
Test name
Test status
Simulation time 326258255529 ps
CPU time 183.2 seconds
Started Jun 28 07:13:28 PM PDT 24
Finished Jun 28 07:16:39 PM PDT 24
Peak memory 201904 kb
Host smart-27ac096b-a4c7-4fdf-a869-d86b860fbc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186506564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2186506564
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1844573484
Short name T803
Test name
Test status
Simulation time 325187882532 ps
CPU time 723.58 seconds
Started Jun 28 07:13:28 PM PDT 24
Finished Jun 28 07:25:38 PM PDT 24
Peak memory 201856 kb
Host smart-f653d11b-d3b9-4bf8-a12e-af0caa54ad6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844573484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1844573484
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.815657610
Short name T345
Test name
Test status
Simulation time 179604409462 ps
CPU time 382.33 seconds
Started Jun 28 07:13:27 PM PDT 24
Finished Jun 28 07:19:57 PM PDT 24
Peak memory 201896 kb
Host smart-e4f607c9-a589-4912-bded-29945799303e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815657610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.815657610
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3140869144
Short name T460
Test name
Test status
Simulation time 431804247857 ps
CPU time 1016.63 seconds
Started Jun 28 07:13:25 PM PDT 24
Finished Jun 28 07:30:29 PM PDT 24
Peak memory 201848 kb
Host smart-687191d6-3431-466c-a7b4-04e21b7cd985
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140869144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3140869144
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.76841800
Short name T223
Test name
Test status
Simulation time 116006729413 ps
CPU time 453.02 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:21:31 PM PDT 24
Peak memory 202216 kb
Host smart-2cf64756-b49b-4600-a798-1fc680d36357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76841800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.76841800
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1605091814
Short name T390
Test name
Test status
Simulation time 23545682159 ps
CPU time 11.94 seconds
Started Jun 28 07:13:55 PM PDT 24
Finished Jun 28 07:14:08 PM PDT 24
Peak memory 201676 kb
Host smart-328ded2a-8618-4668-98f5-46e799065e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605091814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1605091814
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2263151212
Short name T706
Test name
Test status
Simulation time 5119871225 ps
CPU time 3.44 seconds
Started Jun 28 07:13:55 PM PDT 24
Finished Jun 28 07:13:59 PM PDT 24
Peak memory 201680 kb
Host smart-5b7b9dc6-4969-4ec7-a614-2d15193a6cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263151212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2263151212
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3022395248
Short name T498
Test name
Test status
Simulation time 5810594872 ps
CPU time 13.1 seconds
Started Jun 28 07:13:27 PM PDT 24
Finished Jun 28 07:13:47 PM PDT 24
Peak memory 201684 kb
Host smart-46dddd49-9d74-452d-9f9e-72d00fb7b069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022395248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3022395248
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.292921702
Short name T680
Test name
Test status
Simulation time 268846647538 ps
CPU time 892.47 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:28:50 PM PDT 24
Peak memory 202180 kb
Host smart-e8191cd4-05d4-4d4d-950f-60abc517f623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292921702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
292921702
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3892083696
Short name T17
Test name
Test status
Simulation time 142579716736 ps
CPU time 159.61 seconds
Started Jun 28 07:13:54 PM PDT 24
Finished Jun 28 07:16:35 PM PDT 24
Peak memory 210124 kb
Host smart-834cdd4b-6060-4544-b31e-37e70b83ce67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892083696 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3892083696
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.756633748
Short name T544
Test name
Test status
Simulation time 413947410 ps
CPU time 1.57 seconds
Started Jun 28 07:13:59 PM PDT 24
Finished Jun 28 07:14:04 PM PDT 24
Peak memory 201628 kb
Host smart-f0a31b29-9c4d-4ff4-969a-312802c0fe4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756633748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.756633748
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1611688200
Short name T523
Test name
Test status
Simulation time 264964824208 ps
CPU time 408.95 seconds
Started Jun 28 07:13:57 PM PDT 24
Finished Jun 28 07:20:48 PM PDT 24
Peak memory 201868 kb
Host smart-20e0e46a-8806-4a9e-83b4-0de9571b6c01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611688200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1611688200
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2044103062
Short name T161
Test name
Test status
Simulation time 322164363355 ps
CPU time 122.67 seconds
Started Jun 28 07:13:57 PM PDT 24
Finished Jun 28 07:16:02 PM PDT 24
Peak memory 201812 kb
Host smart-69497803-76ee-469a-ad69-8ba7eb5d9ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044103062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2044103062
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.88554161
Short name T325
Test name
Test status
Simulation time 493312061379 ps
CPU time 520.27 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:22:38 PM PDT 24
Peak memory 201932 kb
Host smart-feb65802-8de4-4af7-aae1-2ce3d4f227a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88554161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.88554161
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.249963868
Short name T568
Test name
Test status
Simulation time 330646298193 ps
CPU time 764.75 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:26:43 PM PDT 24
Peak memory 201856 kb
Host smart-5904783e-135d-47f5-a3b8-5667526483c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=249963868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.249963868
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1348899083
Short name T214
Test name
Test status
Simulation time 161076940541 ps
CPU time 180.38 seconds
Started Jun 28 07:13:54 PM PDT 24
Finished Jun 28 07:16:56 PM PDT 24
Peak memory 201932 kb
Host smart-1a89a036-f1f6-4f2d-806d-e117241519a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348899083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1348899083
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1330374448
Short name T422
Test name
Test status
Simulation time 322443736261 ps
CPU time 198.04 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:17:17 PM PDT 24
Peak memory 201856 kb
Host smart-689c7fe1-0080-49f9-ad83-95ae0921e324
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330374448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1330374448
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2076686551
Short name T602
Test name
Test status
Simulation time 558439631153 ps
CPU time 352.57 seconds
Started Jun 28 07:13:57 PM PDT 24
Finished Jun 28 07:19:53 PM PDT 24
Peak memory 201896 kb
Host smart-8529d5b2-12ce-48a0-9656-6eb7516c0dff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076686551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2076686551
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1394896248
Short name T131
Test name
Test status
Simulation time 198410472404 ps
CPU time 54.71 seconds
Started Jun 28 07:13:58 PM PDT 24
Finished Jun 28 07:14:56 PM PDT 24
Peak memory 201860 kb
Host smart-db37ea1d-87f9-45c0-8b91-8d6583f954ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394896248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1394896248
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1875630263
Short name T373
Test name
Test status
Simulation time 23423833307 ps
CPU time 51.76 seconds
Started Jun 28 07:14:02 PM PDT 24
Finished Jun 28 07:14:59 PM PDT 24
Peak memory 201608 kb
Host smart-1ef448da-df74-48bf-b7b6-ea9ef420ab9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875630263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1875630263
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3839370374
Short name T511
Test name
Test status
Simulation time 3652218601 ps
CPU time 7.96 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:14:06 PM PDT 24
Peak memory 201672 kb
Host smart-82a2c395-d5ba-41d0-aac6-89a68eb28565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839370374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3839370374
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.361000450
Short name T486
Test name
Test status
Simulation time 5804302389 ps
CPU time 14.9 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:14:13 PM PDT 24
Peak memory 201684 kb
Host smart-b02bd7e7-e3da-40df-b69a-bf37f9d4be41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361000450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.361000450
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3600433849
Short name T174
Test name
Test status
Simulation time 456536287681 ps
CPU time 603 seconds
Started Jun 28 07:13:57 PM PDT 24
Finished Jun 28 07:24:03 PM PDT 24
Peak memory 212472 kb
Host smart-aa72d1df-6ad7-4784-aec2-7e8ea7eda2c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600433849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3600433849
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3260137971
Short name T212
Test name
Test status
Simulation time 432483776 ps
CPU time 0.8 seconds
Started Jun 28 07:14:01 PM PDT 24
Finished Jun 28 07:14:06 PM PDT 24
Peak memory 201644 kb
Host smart-030df13f-471c-46aa-a530-ac91fd56cee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260137971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3260137971
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3695011371
Short name T83
Test name
Test status
Simulation time 339446968398 ps
CPU time 238.36 seconds
Started Jun 28 07:14:03 PM PDT 24
Finished Jun 28 07:18:08 PM PDT 24
Peak memory 201768 kb
Host smart-820b4388-ab55-421f-aba7-5a3dd74c0095
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695011371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3695011371
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2348289510
Short name T209
Test name
Test status
Simulation time 333191279075 ps
CPU time 134.08 seconds
Started Jun 28 07:13:59 PM PDT 24
Finished Jun 28 07:16:16 PM PDT 24
Peak memory 201936 kb
Host smart-9d60ee15-be47-4fc4-aeb9-1f887f653fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348289510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2348289510
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2916566772
Short name T520
Test name
Test status
Simulation time 327108847957 ps
CPU time 774.45 seconds
Started Jun 28 07:13:58 PM PDT 24
Finished Jun 28 07:26:56 PM PDT 24
Peak memory 201856 kb
Host smart-6e56d010-307e-4da2-8b32-73fb21b643cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916566772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2916566772
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.571385080
Short name T267
Test name
Test status
Simulation time 509346658585 ps
CPU time 1065.86 seconds
Started Jun 28 07:14:02 PM PDT 24
Finished Jun 28 07:31:53 PM PDT 24
Peak memory 201956 kb
Host smart-557753a8-1f71-4c37-94f8-ab4167e8ea7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571385080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.571385080
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3438541066
Short name T639
Test name
Test status
Simulation time 165583597559 ps
CPU time 406.42 seconds
Started Jun 28 07:13:59 PM PDT 24
Finished Jun 28 07:20:48 PM PDT 24
Peak memory 201852 kb
Host smart-f865b2a1-de1e-4bdf-9dc6-26bd594ec06e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438541066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3438541066
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.59959556
Short name T126
Test name
Test status
Simulation time 484880950441 ps
CPU time 1139.07 seconds
Started Jun 28 07:13:58 PM PDT 24
Finished Jun 28 07:33:01 PM PDT 24
Peak memory 201888 kb
Host smart-3997c7fc-988d-4256-b811-b06753ebe5d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59959556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_w
akeup.59959556
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3964986915
Short name T382
Test name
Test status
Simulation time 207218993929 ps
CPU time 207.89 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:17:26 PM PDT 24
Peak memory 201916 kb
Host smart-67c1cb53-d818-4794-8e8a-fa9e31fbd0e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964986915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3964986915
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.4236931168
Short name T226
Test name
Test status
Simulation time 72410362216 ps
CPU time 272.65 seconds
Started Jun 28 07:14:03 PM PDT 24
Finished Jun 28 07:18:42 PM PDT 24
Peak memory 202268 kb
Host smart-59144203-6814-484e-b160-4d8f9e96969b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236931168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.4236931168
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1441057712
Short name T589
Test name
Test status
Simulation time 43800531744 ps
CPU time 83.66 seconds
Started Jun 28 07:14:00 PM PDT 24
Finished Jun 28 07:15:27 PM PDT 24
Peak memory 201696 kb
Host smart-1d56fa58-e9be-40d9-87a8-50acf694c08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441057712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1441057712
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3855352334
Short name T572
Test name
Test status
Simulation time 5283959620 ps
CPU time 4.34 seconds
Started Jun 28 07:13:59 PM PDT 24
Finished Jun 28 07:14:08 PM PDT 24
Peak memory 201696 kb
Host smart-7427cbc6-7045-4d9a-8087-5a459f1ff475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855352334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3855352334
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3114199462
Short name T710
Test name
Test status
Simulation time 5780234757 ps
CPU time 7.17 seconds
Started Jun 28 07:13:59 PM PDT 24
Finished Jun 28 07:14:09 PM PDT 24
Peak memory 201676 kb
Host smart-23da4ef9-0fad-485a-a051-f8a03bdd5c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114199462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3114199462
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3750531389
Short name T735
Test name
Test status
Simulation time 476792382495 ps
CPU time 607.36 seconds
Started Jun 28 07:14:02 PM PDT 24
Finished Jun 28 07:24:14 PM PDT 24
Peak memory 202180 kb
Host smart-894bb9c3-4beb-46c0-acfe-4dfd03609351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750531389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3750531389
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2237344468
Short name T141
Test name
Test status
Simulation time 48497243734 ps
CPU time 125.14 seconds
Started Jun 28 07:14:04 PM PDT 24
Finished Jun 28 07:16:15 PM PDT 24
Peak memory 211668 kb
Host smart-7f79f357-f98d-4a4d-9ef1-dd96175af351
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237344468 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2237344468
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3623125701
Short name T775
Test name
Test status
Simulation time 490038193 ps
CPU time 1.67 seconds
Started Jun 28 07:13:58 PM PDT 24
Finished Jun 28 07:14:02 PM PDT 24
Peak memory 201632 kb
Host smart-8778fcc9-3fa1-4059-8c1e-bec08026f74a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623125701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3623125701
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3323745349
Short name T238
Test name
Test status
Simulation time 182290204311 ps
CPU time 22.07 seconds
Started Jun 28 07:13:58 PM PDT 24
Finished Jun 28 07:14:24 PM PDT 24
Peak memory 201868 kb
Host smart-83ced122-169d-468e-b84a-05111ed034c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323745349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3323745349
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3155880873
Short name T335
Test name
Test status
Simulation time 567493565850 ps
CPU time 369.08 seconds
Started Jun 28 07:14:00 PM PDT 24
Finished Jun 28 07:20:14 PM PDT 24
Peak memory 201876 kb
Host smart-33beb5a3-3260-497e-a41e-ce5d4c2855ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155880873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3155880873
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2760170197
Short name T321
Test name
Test status
Simulation time 490857941107 ps
CPU time 1123.87 seconds
Started Jun 28 07:14:04 PM PDT 24
Finished Jun 28 07:32:54 PM PDT 24
Peak memory 201868 kb
Host smart-26c29fe3-3729-4076-9267-df52a3d1a7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760170197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2760170197
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1667518147
Short name T750
Test name
Test status
Simulation time 334044742288 ps
CPU time 384.4 seconds
Started Jun 28 07:14:03 PM PDT 24
Finished Jun 28 07:20:33 PM PDT 24
Peak memory 201864 kb
Host smart-9b1aad78-3868-43a7-bed4-dbb53dac9e0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667518147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1667518147
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.292997473
Short name T799
Test name
Test status
Simulation time 325949042498 ps
CPU time 108.76 seconds
Started Jun 28 07:14:04 PM PDT 24
Finished Jun 28 07:15:59 PM PDT 24
Peak memory 201932 kb
Host smart-622cdf12-4fb6-4bf7-8456-163a2d89f4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292997473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.292997473
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2342666159
Short name T585
Test name
Test status
Simulation time 488495975852 ps
CPU time 303.95 seconds
Started Jun 28 07:14:02 PM PDT 24
Finished Jun 28 07:19:11 PM PDT 24
Peak memory 201852 kb
Host smart-8d91e3fa-c658-43f1-b3ba-d7bf839c7364
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342666159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2342666159
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.190113789
Short name T250
Test name
Test status
Simulation time 573393625297 ps
CPU time 1334.6 seconds
Started Jun 28 07:13:59 PM PDT 24
Finished Jun 28 07:36:18 PM PDT 24
Peak memory 201884 kb
Host smart-62d129ba-3f46-4304-b345-c0f82a6b198a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190113789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.190113789
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2692273028
Short name T633
Test name
Test status
Simulation time 204127216451 ps
CPU time 276.07 seconds
Started Jun 28 07:14:04 PM PDT 24
Finished Jun 28 07:18:46 PM PDT 24
Peak memory 201816 kb
Host smart-cea56f19-e3e4-4b8b-aadb-33d5d1aaaf32
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692273028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2692273028
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.497727051
Short name T48
Test name
Test status
Simulation time 117920072038 ps
CPU time 626.95 seconds
Started Jun 28 07:13:59 PM PDT 24
Finished Jun 28 07:24:29 PM PDT 24
Peak memory 202244 kb
Host smart-7e6b5e2c-0b6b-4dcb-80a3-db8c57217105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497727051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.497727051
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4125725965
Short name T478
Test name
Test status
Simulation time 25092523991 ps
CPU time 15.72 seconds
Started Jun 28 07:14:03 PM PDT 24
Finished Jun 28 07:14:25 PM PDT 24
Peak memory 201592 kb
Host smart-7d7c0006-bc1e-4646-ae3b-969ef4c0cb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125725965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4125725965
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2197815968
Short name T741
Test name
Test status
Simulation time 5398049631 ps
CPU time 5.13 seconds
Started Jun 28 07:14:01 PM PDT 24
Finished Jun 28 07:14:10 PM PDT 24
Peak memory 201672 kb
Host smart-6ed28a0a-e297-4c33-adad-55697f9d8b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197815968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2197815968
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3564183794
Short name T712
Test name
Test status
Simulation time 5984723832 ps
CPU time 5.79 seconds
Started Jun 28 07:14:03 PM PDT 24
Finished Jun 28 07:14:15 PM PDT 24
Peak memory 201500 kb
Host smart-01ae0124-d63a-4532-a87f-01f2e4fea43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564183794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3564183794
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3347104387
Short name T760
Test name
Test status
Simulation time 221960152185 ps
CPU time 485.21 seconds
Started Jun 28 07:13:58 PM PDT 24
Finished Jun 28 07:22:06 PM PDT 24
Peak memory 201928 kb
Host smart-d2909063-2a8c-4a4a-a605-3a99b78ee861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347104387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3347104387
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.321227423
Short name T36
Test name
Test status
Simulation time 312411056260 ps
CPU time 67.19 seconds
Started Jun 28 07:14:03 PM PDT 24
Finished Jun 28 07:15:16 PM PDT 24
Peak memory 210148 kb
Host smart-1027ad40-36b2-4249-90c3-80d1a1d6d6ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321227423 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.321227423
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1777318690
Short name T146
Test name
Test status
Simulation time 348367825 ps
CPU time 1.45 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:14:00 PM PDT 24
Peak memory 201632 kb
Host smart-97644f9b-ea6a-4121-bce1-cae26eca9354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777318690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1777318690
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.118676097
Short name T671
Test name
Test status
Simulation time 164971152167 ps
CPU time 97.37 seconds
Started Jun 28 07:13:54 PM PDT 24
Finished Jun 28 07:15:33 PM PDT 24
Peak memory 201936 kb
Host smart-2e003959-e0f4-464e-bef3-2377b8bbaf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118676097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.118676097
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4022011373
Short name T560
Test name
Test status
Simulation time 171128094539 ps
CPU time 372.58 seconds
Started Jun 28 07:13:55 PM PDT 24
Finished Jun 28 07:20:08 PM PDT 24
Peak memory 202016 kb
Host smart-bc21d2d3-e14f-4599-a876-d599ce3f4c7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022011373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.4022011373
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.424864673
Short name T232
Test name
Test status
Simulation time 163724613895 ps
CPU time 377.77 seconds
Started Jun 28 07:13:57 PM PDT 24
Finished Jun 28 07:20:17 PM PDT 24
Peak memory 201880 kb
Host smart-d6760dbe-d3a6-4853-87e2-b6513a329c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424864673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.424864673
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1140359368
Short name T416
Test name
Test status
Simulation time 318228842228 ps
CPU time 707.22 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:25:46 PM PDT 24
Peak memory 201840 kb
Host smart-46d5c4a4-fabf-46c8-ae05-fe6f0fde9fe9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140359368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1140359368
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.971596500
Short name T652
Test name
Test status
Simulation time 391323565440 ps
CPU time 937.2 seconds
Started Jun 28 07:13:55 PM PDT 24
Finished Jun 28 07:29:34 PM PDT 24
Peak memory 201864 kb
Host smart-a3e374b7-51ff-4bfe-b9b9-e4862a225495
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971596500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.971596500
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1039103950
Short name T797
Test name
Test status
Simulation time 147639377306 ps
CPU time 594.54 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:23:53 PM PDT 24
Peak memory 202208 kb
Host smart-438d0ba8-87ad-4eeb-9e71-0663cf65b9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039103950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1039103950
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3535897719
Short name T745
Test name
Test status
Simulation time 30498723040 ps
CPU time 18.56 seconds
Started Jun 28 07:13:57 PM PDT 24
Finished Jun 28 07:14:18 PM PDT 24
Peak memory 201608 kb
Host smart-b373b4f9-d3ed-47e2-8648-1a0577148ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535897719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3535897719
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2232587036
Short name T512
Test name
Test status
Simulation time 5496382906 ps
CPU time 4.01 seconds
Started Jun 28 07:13:56 PM PDT 24
Finished Jun 28 07:14:03 PM PDT 24
Peak memory 201676 kb
Host smart-6dda419a-9445-49c2-a94c-544b8f288eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232587036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2232587036
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2024871062
Short name T655
Test name
Test status
Simulation time 5805236147 ps
CPU time 14.26 seconds
Started Jun 28 07:13:57 PM PDT 24
Finished Jun 28 07:14:13 PM PDT 24
Peak memory 201680 kb
Host smart-e334ea83-d3a6-4366-975f-96f20ac7079c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024871062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2024871062
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.591016790
Short name T632
Test name
Test status
Simulation time 434943320211 ps
CPU time 1243.96 seconds
Started Jun 28 07:14:00 PM PDT 24
Finished Jun 28 07:34:48 PM PDT 24
Peak memory 210376 kb
Host smart-be98f477-935d-427a-8093-f3e369dc23c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591016790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
591016790
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3513994792
Short name T13
Test name
Test status
Simulation time 70535587986 ps
CPU time 218.51 seconds
Started Jun 28 07:14:00 PM PDT 24
Finished Jun 28 07:17:42 PM PDT 24
Peak memory 210512 kb
Host smart-6d95ae56-4b0a-45a1-b3db-6e2df74016af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513994792 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3513994792
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1288931382
Short name T68
Test name
Test status
Simulation time 449752794 ps
CPU time 1.68 seconds
Started Jun 28 07:14:18 PM PDT 24
Finished Jun 28 07:14:25 PM PDT 24
Peak memory 201628 kb
Host smart-569a1253-70f6-4e9f-804d-8701949e97d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288931382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1288931382
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3216022650
Short name T285
Test name
Test status
Simulation time 532547599210 ps
CPU time 835.35 seconds
Started Jun 28 07:14:19 PM PDT 24
Finished Jun 28 07:28:19 PM PDT 24
Peak memory 201880 kb
Host smart-faddc47c-3e60-4040-b1a6-a8ee4fecf18e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216022650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3216022650
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.496892878
Short name T354
Test name
Test status
Simulation time 358450316885 ps
CPU time 202.57 seconds
Started Jun 28 07:14:17 PM PDT 24
Finished Jun 28 07:17:44 PM PDT 24
Peak memory 201884 kb
Host smart-ad81474d-36e0-4a84-89d1-39678e849b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496892878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.496892878
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3673534703
Short name T324
Test name
Test status
Simulation time 165256699328 ps
CPU time 34.26 seconds
Started Jun 28 07:14:23 PM PDT 24
Finished Jun 28 07:15:04 PM PDT 24
Peak memory 201884 kb
Host smart-1b261a11-330a-4559-899f-3b565e03d080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673534703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3673534703
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3737422888
Short name T569
Test name
Test status
Simulation time 325235981255 ps
CPU time 396.82 seconds
Started Jun 28 07:14:20 PM PDT 24
Finished Jun 28 07:21:02 PM PDT 24
Peak memory 201852 kb
Host smart-acde2bde-050d-4209-8aa6-7b42a3da5f57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737422888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3737422888
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3740537367
Short name T233
Test name
Test status
Simulation time 162180921487 ps
CPU time 387.49 seconds
Started Jun 28 07:14:20 PM PDT 24
Finished Jun 28 07:20:52 PM PDT 24
Peak memory 201956 kb
Host smart-507bf51f-e626-40e3-8a69-970b2aa8a192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740537367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3740537367
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1013529488
Short name T571
Test name
Test status
Simulation time 499324185582 ps
CPU time 290.59 seconds
Started Jun 28 07:14:19 PM PDT 24
Finished Jun 28 07:19:14 PM PDT 24
Peak memory 201848 kb
Host smart-2e7d8a6a-ce9c-44ff-83f1-ee012bfda318
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013529488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1013529488
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2679245965
Short name T536
Test name
Test status
Simulation time 348670410698 ps
CPU time 408.43 seconds
Started Jun 28 07:14:18 PM PDT 24
Finished Jun 28 07:21:12 PM PDT 24
Peak memory 201872 kb
Host smart-c3a5c089-d6ba-40b9-b966-20336127b38a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679245965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2679245965
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1312439451
Short name T755
Test name
Test status
Simulation time 201893257947 ps
CPU time 224.35 seconds
Started Jun 28 07:14:19 PM PDT 24
Finished Jun 28 07:18:08 PM PDT 24
Peak memory 201888 kb
Host smart-577969df-1418-4a06-9146-f7da69b47b90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312439451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1312439451
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3155434377
Short name T368
Test name
Test status
Simulation time 143607055468 ps
CPU time 767.86 seconds
Started Jun 28 07:14:23 PM PDT 24
Finished Jun 28 07:27:17 PM PDT 24
Peak memory 202260 kb
Host smart-cb3722bd-e135-4f4c-8cd3-1c18366d29c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155434377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3155434377
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.913201715
Short name T184
Test name
Test status
Simulation time 29617935004 ps
CPU time 5.87 seconds
Started Jun 28 07:14:19 PM PDT 24
Finished Jun 28 07:14:29 PM PDT 24
Peak memory 201596 kb
Host smart-88ab25eb-a84f-41d7-b5e7-41481c936076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913201715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.913201715
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1062566564
Short name T437
Test name
Test status
Simulation time 2941080224 ps
CPU time 7.75 seconds
Started Jun 28 07:14:18 PM PDT 24
Finished Jun 28 07:14:30 PM PDT 24
Peak memory 201708 kb
Host smart-7b0c08bf-6a37-48b7-98cb-a4d3d6f88b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062566564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1062566564
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1568917757
Short name T670
Test name
Test status
Simulation time 5761887989 ps
CPU time 4.18 seconds
Started Jun 28 07:14:18 PM PDT 24
Finished Jun 28 07:14:27 PM PDT 24
Peak memory 201676 kb
Host smart-c4747000-f39a-474b-9cde-9343c9963377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568917757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1568917757
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2971117669
Short name T421
Test name
Test status
Simulation time 190331299359 ps
CPU time 462.46 seconds
Started Jun 28 07:14:19 PM PDT 24
Finished Jun 28 07:22:06 PM PDT 24
Peak memory 202168 kb
Host smart-f601fcfd-4a32-4fe9-87da-9d58ed59e82c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971117669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2971117669
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1802863583
Short name T751
Test name
Test status
Simulation time 16489445698 ps
CPU time 29.09 seconds
Started Jun 28 07:14:18 PM PDT 24
Finished Jun 28 07:14:52 PM PDT 24
Peak memory 210276 kb
Host smart-5002abec-3799-493d-9dd0-e3dced276ff4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802863583 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1802863583
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2993343956
Short name T493
Test name
Test status
Simulation time 545467924 ps
CPU time 0.91 seconds
Started Jun 28 07:14:39 PM PDT 24
Finished Jun 28 07:15:06 PM PDT 24
Peak memory 201648 kb
Host smart-852e35fd-167d-4814-9808-41ee05aa54c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993343956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2993343956
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1279084804
Short name T7
Test name
Test status
Simulation time 357079617110 ps
CPU time 216.13 seconds
Started Jun 28 07:14:44 PM PDT 24
Finished Jun 28 07:18:51 PM PDT 24
Peak memory 201868 kb
Host smart-76d6adb5-4ac4-48b2-a993-349179fe8785
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279084804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1279084804
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3368273216
Short name T518
Test name
Test status
Simulation time 499836826469 ps
CPU time 1192.88 seconds
Started Jun 28 07:14:19 PM PDT 24
Finished Jun 28 07:34:17 PM PDT 24
Peak memory 201828 kb
Host smart-2bc43456-c97f-4a55-9a28-f6f3fb974b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368273216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3368273216
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1941675750
Short name T455
Test name
Test status
Simulation time 167488194058 ps
CPU time 95.64 seconds
Started Jun 28 07:14:19 PM PDT 24
Finished Jun 28 07:15:59 PM PDT 24
Peak memory 201864 kb
Host smart-dd9fb70c-79e5-4aab-bbb3-f8835db3199a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941675750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1941675750
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2323092766
Short name T640
Test name
Test status
Simulation time 166234670752 ps
CPU time 364.85 seconds
Started Jun 28 07:14:21 PM PDT 24
Finished Jun 28 07:20:31 PM PDT 24
Peak memory 201932 kb
Host smart-365b79ea-41b9-4777-afbd-90f424cd4890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323092766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2323092766
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.809584119
Short name T8
Test name
Test status
Simulation time 328589636414 ps
CPU time 230.27 seconds
Started Jun 28 07:14:20 PM PDT 24
Finished Jun 28 07:18:16 PM PDT 24
Peak memory 201856 kb
Host smart-f9819f00-111e-4e85-98f0-0432e6e75abd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=809584119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.809584119
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.4242284740
Short name T298
Test name
Test status
Simulation time 332907232931 ps
CPU time 174.43 seconds
Started Jun 28 07:14:39 PM PDT 24
Finished Jun 28 07:17:59 PM PDT 24
Peak memory 201948 kb
Host smart-1c321982-eb1c-4560-af63-445755eedb12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242284740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.4242284740
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3856750905
Short name T449
Test name
Test status
Simulation time 400840170656 ps
CPU time 93.93 seconds
Started Jun 28 07:14:42 PM PDT 24
Finished Jun 28 07:16:46 PM PDT 24
Peak memory 201812 kb
Host smart-d796c88e-0287-4d83-974b-3fc823bab012
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856750905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3856750905
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2045984111
Short name T726
Test name
Test status
Simulation time 126882378433 ps
CPU time 408.34 seconds
Started Jun 28 07:14:40 PM PDT 24
Finished Jun 28 07:21:53 PM PDT 24
Peak memory 202328 kb
Host smart-d88be8c0-a8e3-41ee-834c-7022f27a6109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045984111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2045984111
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3054059486
Short name T374
Test name
Test status
Simulation time 41143519619 ps
CPU time 24.12 seconds
Started Jun 28 07:14:40 PM PDT 24
Finished Jun 28 07:15:33 PM PDT 24
Peak memory 201628 kb
Host smart-dfc6db83-703c-4c72-8ee2-d8c9dd99294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054059486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3054059486
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1101391302
Short name T10
Test name
Test status
Simulation time 5370600229 ps
CPU time 4.13 seconds
Started Jun 28 07:14:40 PM PDT 24
Finished Jun 28 07:15:09 PM PDT 24
Peak memory 201668 kb
Host smart-918bc63f-8692-44c6-a48a-5b8c5392e127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101391302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1101391302
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.169450208
Short name T800
Test name
Test status
Simulation time 6026865983 ps
CPU time 14.31 seconds
Started Jun 28 07:14:17 PM PDT 24
Finished Jun 28 07:14:36 PM PDT 24
Peak memory 201684 kb
Host smart-8f22f5dc-f48b-412c-95b8-c53e47644d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169450208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.169450208
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3134826336
Short name T563
Test name
Test status
Simulation time 534040155071 ps
CPU time 1120.48 seconds
Started Jun 28 07:14:39 PM PDT 24
Finished Jun 28 07:33:45 PM PDT 24
Peak memory 210444 kb
Host smart-e7058f59-2f21-435a-a517-f5962fd80c9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134826336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3134826336
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1932665404
Short name T790
Test name
Test status
Simulation time 144573795464 ps
CPU time 97.67 seconds
Started Jun 28 07:14:39 PM PDT 24
Finished Jun 28 07:16:42 PM PDT 24
Peak memory 218132 kb
Host smart-6afb0337-5617-47d0-8f6d-19b677fdaea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932665404 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1932665404
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.4069297362
Short name T522
Test name
Test status
Simulation time 459515746 ps
CPU time 1.69 seconds
Started Jun 28 07:00:08 PM PDT 24
Finished Jun 28 07:00:16 PM PDT 24
Peak memory 201596 kb
Host smart-2da3867f-a342-4cf6-af96-2c805fd2e092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069297362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.4069297362
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3559298132
Short name T129
Test name
Test status
Simulation time 371608745180 ps
CPU time 473.54 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:08:04 PM PDT 24
Peak memory 201860 kb
Host smart-44f1357d-4523-4451-ac35-92065645393a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559298132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3559298132
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2445808227
Short name T653
Test name
Test status
Simulation time 164387963189 ps
CPU time 361.34 seconds
Started Jun 28 07:00:05 PM PDT 24
Finished Jun 28 07:06:11 PM PDT 24
Peak memory 201896 kb
Host smart-adf1971d-a84e-4c56-863d-0280700343d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445808227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2445808227
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.355747225
Short name T148
Test name
Test status
Simulation time 165820835737 ps
CPU time 114.28 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:02:05 PM PDT 24
Peak memory 201888 kb
Host smart-c1210fea-f156-4663-9729-3b5032d5ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355747225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.355747225
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2227288981
Short name T782
Test name
Test status
Simulation time 159525276928 ps
CPU time 367.91 seconds
Started Jun 28 07:00:04 PM PDT 24
Finished Jun 28 07:06:16 PM PDT 24
Peak memory 201912 kb
Host smart-8229433e-ed24-4b63-a318-cb787384b9b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227288981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2227288981
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2493331216
Short name T167
Test name
Test status
Simulation time 331274275934 ps
CPU time 46.85 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:00:59 PM PDT 24
Peak memory 201940 kb
Host smart-900ef986-5856-4797-84e7-721882e13c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493331216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2493331216
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.449369513
Short name T663
Test name
Test status
Simulation time 332295747730 ps
CPU time 767.44 seconds
Started Jun 28 07:00:05 PM PDT 24
Finished Jun 28 07:12:56 PM PDT 24
Peak memory 201912 kb
Host smart-0d89231c-9585-407e-9e86-2d4df4208385
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=449369513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.449369513
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.464342882
Short name T204
Test name
Test status
Simulation time 519213859581 ps
CPU time 140.53 seconds
Started Jun 28 07:00:08 PM PDT 24
Finished Jun 28 07:02:34 PM PDT 24
Peak memory 201888 kb
Host smart-6f95c2ba-fb32-4855-a360-d35e938dc435
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464342882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.464342882
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2149999483
Short name T152
Test name
Test status
Simulation time 201506678481 ps
CPU time 25.71 seconds
Started Jun 28 07:00:08 PM PDT 24
Finished Jun 28 07:00:41 PM PDT 24
Peak memory 201928 kb
Host smart-d50370cd-5941-46cd-ad87-c530538fd978
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149999483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2149999483
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2046209267
Short name T418
Test name
Test status
Simulation time 46081401199 ps
CPU time 98.37 seconds
Started Jun 28 07:00:05 PM PDT 24
Finished Jun 28 07:01:48 PM PDT 24
Peak memory 201684 kb
Host smart-8514bf96-80ad-4a53-851c-6c27676bbca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046209267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2046209267
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3541578654
Short name T721
Test name
Test status
Simulation time 4408834958 ps
CPU time 6.35 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:00:18 PM PDT 24
Peak memory 201708 kb
Host smart-66b7d8fa-a62f-4333-846e-b24d7ddf18e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541578654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3541578654
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3245134032
Short name T496
Test name
Test status
Simulation time 6230824901 ps
CPU time 1.86 seconds
Started Jun 28 07:00:05 PM PDT 24
Finished Jun 28 07:00:15 PM PDT 24
Peak memory 201668 kb
Host smart-8cc8fdfb-f0b2-4723-8a44-30cda12f9dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245134032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3245134032
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1840521229
Short name T15
Test name
Test status
Simulation time 114206764439 ps
CPU time 40.52 seconds
Started Jun 28 07:00:05 PM PDT 24
Finished Jun 28 07:00:49 PM PDT 24
Peak memory 210260 kb
Host smart-4c27f6e6-4d14-4eb8-8e84-340932cd6039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840521229 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1840521229
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2093743863
Short name T762
Test name
Test status
Simulation time 308410955 ps
CPU time 0.95 seconds
Started Jun 28 07:00:17 PM PDT 24
Finished Jun 28 07:00:23 PM PDT 24
Peak memory 201620 kb
Host smart-75b73b76-b3c6-4cde-b4cc-39349d075e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093743863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2093743863
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2842526059
Short name T334
Test name
Test status
Simulation time 160418536622 ps
CPU time 157.31 seconds
Started Jun 28 07:00:19 PM PDT 24
Finished Jun 28 07:03:00 PM PDT 24
Peak memory 201864 kb
Host smart-bdaa5e1c-ce2a-46a8-9b91-bd2989c29f66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842526059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2842526059
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2185482341
Short name T725
Test name
Test status
Simulation time 373625802753 ps
CPU time 782.35 seconds
Started Jun 28 07:00:18 PM PDT 24
Finished Jun 28 07:13:25 PM PDT 24
Peak memory 201892 kb
Host smart-108a57c4-1c40-405d-8231-b019958364d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185482341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2185482341
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.37771417
Short name T515
Test name
Test status
Simulation time 330939690693 ps
CPU time 105.78 seconds
Started Jun 28 07:00:08 PM PDT 24
Finished Jun 28 07:02:00 PM PDT 24
Peak memory 201908 kb
Host smart-a3cafcbd-bfec-4112-b96f-d89a0b9ee881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37771417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.37771417
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3625923715
Short name T758
Test name
Test status
Simulation time 488350390580 ps
CPU time 1008.74 seconds
Started Jun 28 07:00:06 PM PDT 24
Finished Jun 28 07:17:00 PM PDT 24
Peak memory 201880 kb
Host smart-ef208409-9d9e-4e9f-b6cf-0512f382159f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625923715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3625923715
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.398383727
Short name T770
Test name
Test status
Simulation time 327941799044 ps
CPU time 204.53 seconds
Started Jun 28 07:00:07 PM PDT 24
Finished Jun 28 07:03:37 PM PDT 24
Peak memory 201856 kb
Host smart-0a03f9fb-aa13-4d8f-bf03-72f849d46c77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=398383727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.398383727
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2648698965
Short name T444
Test name
Test status
Simulation time 200112834456 ps
CPU time 204.84 seconds
Started Jun 28 07:00:15 PM PDT 24
Finished Jun 28 07:03:46 PM PDT 24
Peak memory 201860 kb
Host smart-276fbf68-639f-415d-ad4a-b3f5df9b97bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648698965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2648698965
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3753147896
Short name T77
Test name
Test status
Simulation time 117222148774 ps
CPU time 464.13 seconds
Started Jun 28 07:00:16 PM PDT 24
Finished Jun 28 07:08:06 PM PDT 24
Peak memory 202200 kb
Host smart-741712ac-7f87-4def-934c-fe149b5b732e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753147896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3753147896
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3364241517
Short name T500
Test name
Test status
Simulation time 31544353778 ps
CPU time 18.06 seconds
Started Jun 28 07:00:19 PM PDT 24
Finished Jun 28 07:00:42 PM PDT 24
Peak memory 201692 kb
Host smart-e71b7442-d96f-42c6-8d15-4ab84d4e873e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364241517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3364241517
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3175262394
Short name T376
Test name
Test status
Simulation time 4150869651 ps
CPU time 10.51 seconds
Started Jun 28 07:00:19 PM PDT 24
Finished Jun 28 07:00:34 PM PDT 24
Peak memory 201700 kb
Host smart-0a8b2c24-ed51-428a-93d9-fdc50c0f8370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175262394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3175262394
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1481964585
Short name T6
Test name
Test status
Simulation time 5544695117 ps
CPU time 13.94 seconds
Started Jun 28 07:00:08 PM PDT 24
Finished Jun 28 07:00:28 PM PDT 24
Peak memory 201652 kb
Host smart-6da4775b-0ba3-45e4-a88b-7956a2515c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481964585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1481964585
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1261489308
Short name T723
Test name
Test status
Simulation time 158292715265 ps
CPU time 483.02 seconds
Started Jun 28 07:00:19 PM PDT 24
Finished Jun 28 07:08:27 PM PDT 24
Peak memory 211728 kb
Host smart-fd322921-90df-4ca2-bdd4-50c22ec25bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261489308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1261489308
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3637757415
Short name T348
Test name
Test status
Simulation time 206528208940 ps
CPU time 270.54 seconds
Started Jun 28 07:00:16 PM PDT 24
Finished Jun 28 07:04:52 PM PDT 24
Peak memory 211776 kb
Host smart-d84844e2-06a9-4725-bb79-4c17f04b75c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637757415 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3637757415
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.918511824
Short name T69
Test name
Test status
Simulation time 305966929 ps
CPU time 0.99 seconds
Started Jun 28 07:00:37 PM PDT 24
Finished Jun 28 07:00:40 PM PDT 24
Peak memory 201628 kb
Host smart-a7c71738-993c-455e-954d-4cda9f1bb156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918511824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.918511824
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2602594206
Short name T165
Test name
Test status
Simulation time 510614335414 ps
CPU time 226.2 seconds
Started Jun 28 07:00:38 PM PDT 24
Finished Jun 28 07:04:26 PM PDT 24
Peak memory 201808 kb
Host smart-47ca23df-189e-49b1-a95c-3e85b5af3c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602594206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2602594206
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2985775090
Short name T254
Test name
Test status
Simulation time 496138131653 ps
CPU time 278.58 seconds
Started Jun 28 07:00:18 PM PDT 24
Finished Jun 28 07:05:01 PM PDT 24
Peak memory 201960 kb
Host smart-8f71d96c-0bcd-45ca-8e87-827a610950f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985775090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2985775090
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2719808593
Short name T666
Test name
Test status
Simulation time 333934499702 ps
CPU time 825.29 seconds
Started Jun 28 07:00:16 PM PDT 24
Finished Jun 28 07:14:07 PM PDT 24
Peak memory 202016 kb
Host smart-479ce05b-16c7-4c31-ae15-5d7aa8a65468
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719808593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2719808593
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2192938509
Short name T127
Test name
Test status
Simulation time 483905731707 ps
CPU time 1108.83 seconds
Started Jun 28 07:00:17 PM PDT 24
Finished Jun 28 07:18:51 PM PDT 24
Peak memory 201884 kb
Host smart-ec0b8c26-def3-4443-b013-0db6ddd5608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192938509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2192938509
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2836621309
Short name T4
Test name
Test status
Simulation time 489665864017 ps
CPU time 298.47 seconds
Started Jun 28 07:00:17 PM PDT 24
Finished Jun 28 07:05:20 PM PDT 24
Peak memory 201864 kb
Host smart-9946d222-1ab2-4b0c-ba87-cd93c39d2f6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836621309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2836621309
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4048478439
Short name T5
Test name
Test status
Simulation time 201354108424 ps
CPU time 140.33 seconds
Started Jun 28 07:00:24 PM PDT 24
Finished Jun 28 07:02:47 PM PDT 24
Peak memory 201852 kb
Host smart-aa3a428a-b288-41c4-aa20-69c6861e5022
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048478439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4048478439
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.4197070437
Short name T731
Test name
Test status
Simulation time 59092066085 ps
CPU time 348.8 seconds
Started Jun 28 07:00:38 PM PDT 24
Finished Jun 28 07:06:29 PM PDT 24
Peak memory 202192 kb
Host smart-ef802f51-0d1c-4939-92f8-0595a2b25ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197070437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.4197070437
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1839578810
Short name T417
Test name
Test status
Simulation time 33660042030 ps
CPU time 38.1 seconds
Started Jun 28 07:00:37 PM PDT 24
Finished Jun 28 07:01:17 PM PDT 24
Peak memory 201688 kb
Host smart-e64254cb-dd46-4861-bcb9-57dcd0cee757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839578810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1839578810
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2253809411
Short name T634
Test name
Test status
Simulation time 3669350789 ps
CPU time 2.81 seconds
Started Jun 28 07:00:39 PM PDT 24
Finished Jun 28 07:00:44 PM PDT 24
Peak memory 201672 kb
Host smart-5ecb4b86-0ee8-443a-9328-af28d04e7961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253809411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2253809411
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2959532540
Short name T698
Test name
Test status
Simulation time 5642945849 ps
CPU time 13.35 seconds
Started Jun 28 07:00:16 PM PDT 24
Finished Jun 28 07:00:35 PM PDT 24
Peak memory 201592 kb
Host smart-13a01b0b-10b0-48c5-8cf0-c9edaa586c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959532540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2959532540
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2175810042
Short name T32
Test name
Test status
Simulation time 372978068626 ps
CPU time 416.9 seconds
Started Jun 28 07:00:38 PM PDT 24
Finished Jun 28 07:07:36 PM PDT 24
Peak memory 201872 kb
Host smart-6445516f-dcbb-40be-a744-14aca72e93a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175810042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2175810042
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.4071496361
Short name T175
Test name
Test status
Simulation time 8915951661 ps
CPU time 21.93 seconds
Started Jun 28 07:00:39 PM PDT 24
Finished Jun 28 07:01:04 PM PDT 24
Peak memory 210256 kb
Host smart-735ac460-b43a-4778-8bb1-217084f91b30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071496361 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.4071496361
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2276343588
Short name T581
Test name
Test status
Simulation time 373206216 ps
CPU time 0.87 seconds
Started Jun 28 07:00:50 PM PDT 24
Finished Jun 28 07:00:53 PM PDT 24
Peak memory 201616 kb
Host smart-43eaaab9-132c-4a2b-891b-8ec98ca26ff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276343588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2276343588
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2647219971
Short name T245
Test name
Test status
Simulation time 497691699596 ps
CPU time 1114.18 seconds
Started Jun 28 07:00:53 PM PDT 24
Finished Jun 28 07:19:29 PM PDT 24
Peak memory 201864 kb
Host smart-380c156e-5e6b-4ba5-b86b-688817fbf830
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647219971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2647219971
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.907115582
Short name T182
Test name
Test status
Simulation time 483753068045 ps
CPU time 183.23 seconds
Started Jun 28 07:00:37 PM PDT 24
Finished Jun 28 07:03:41 PM PDT 24
Peak memory 201944 kb
Host smart-14121b22-ab88-4e8e-ac45-9ea57593b213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907115582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.907115582
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3976412396
Short name T579
Test name
Test status
Simulation time 158175333079 ps
CPU time 375.97 seconds
Started Jun 28 07:00:53 PM PDT 24
Finished Jun 28 07:07:11 PM PDT 24
Peak memory 201848 kb
Host smart-86270318-8c82-4c56-9fc4-aacd78da87c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976412396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3976412396
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.868825321
Short name T564
Test name
Test status
Simulation time 487162618018 ps
CPU time 298.7 seconds
Started Jun 28 07:00:38 PM PDT 24
Finished Jun 28 07:05:38 PM PDT 24
Peak memory 201892 kb
Host smart-d7958009-7f5f-40f0-8f15-e2d12333d642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868825321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.868825321
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2728622540
Short name T414
Test name
Test status
Simulation time 494159063725 ps
CPU time 1040.55 seconds
Started Jun 28 07:00:38 PM PDT 24
Finished Jun 28 07:18:02 PM PDT 24
Peak memory 201872 kb
Host smart-ad9e0457-5cfb-4445-b9fc-6027998d5915
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728622540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2728622540
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1932220269
Short name T216
Test name
Test status
Simulation time 401327406796 ps
CPU time 849.33 seconds
Started Jun 28 07:00:48 PM PDT 24
Finished Jun 28 07:15:00 PM PDT 24
Peak memory 201876 kb
Host smart-3687cb3c-80de-463d-bcd0-79bf945b0382
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932220269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1932220269
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.983045906
Short name T510
Test name
Test status
Simulation time 198799543630 ps
CPU time 120.36 seconds
Started Jun 28 07:00:49 PM PDT 24
Finished Jun 28 07:02:52 PM PDT 24
Peak memory 201912 kb
Host smart-da2fbb0c-0c29-4a2e-86f9-6a1545ece531
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983045906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.983045906
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2501994917
Short name T82
Test name
Test status
Simulation time 86485833573 ps
CPU time 326.47 seconds
Started Jun 28 07:00:48 PM PDT 24
Finished Jun 28 07:06:16 PM PDT 24
Peak memory 202252 kb
Host smart-1d8ba867-24c1-4ddd-a369-abf7858c649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501994917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2501994917
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1369614218
Short name T727
Test name
Test status
Simulation time 36645477133 ps
CPU time 42.8 seconds
Started Jun 28 07:00:48 PM PDT 24
Finished Jun 28 07:01:33 PM PDT 24
Peak memory 201672 kb
Host smart-752043af-6630-4e2f-b9a0-b8dbd92a72c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369614218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1369614218
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3277971978
Short name T443
Test name
Test status
Simulation time 4566032134 ps
CPU time 3.64 seconds
Started Jun 28 07:00:49 PM PDT 24
Finished Jun 28 07:00:55 PM PDT 24
Peak memory 201676 kb
Host smart-6a97ca33-7458-4374-ae09-7329500f5279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277971978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3277971978
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3930199700
Short name T384
Test name
Test status
Simulation time 5739509373 ps
CPU time 3.92 seconds
Started Jun 28 07:00:38 PM PDT 24
Finished Jun 28 07:00:44 PM PDT 24
Peak memory 201668 kb
Host smart-738e412f-b6b6-43ad-af11-eb1e6cb482aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930199700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3930199700
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.207251336
Short name T369
Test name
Test status
Simulation time 229807486715 ps
CPU time 1169.56 seconds
Started Jun 28 07:00:50 PM PDT 24
Finished Jun 28 07:20:22 PM PDT 24
Peak memory 210392 kb
Host smart-97b2fee1-5870-4708-817c-73aee5eb07ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207251336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.207251336
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.4284578688
Short name T186
Test name
Test status
Simulation time 57457009585 ps
CPU time 135.63 seconds
Started Jun 28 07:00:53 PM PDT 24
Finished Jun 28 07:03:11 PM PDT 24
Peak memory 210260 kb
Host smart-a5124f4d-f396-4267-b633-401b80fbe5cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284578688 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.4284578688
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.620726111
Short name T519
Test name
Test status
Simulation time 465780249 ps
CPU time 1.14 seconds
Started Jun 28 07:01:08 PM PDT 24
Finished Jun 28 07:01:10 PM PDT 24
Peak memory 201592 kb
Host smart-60d7a340-53b8-4c22-9594-7594b9425ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620726111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.620726111
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1374161218
Short name T236
Test name
Test status
Simulation time 365907792593 ps
CPU time 208.17 seconds
Started Jun 28 07:01:05 PM PDT 24
Finished Jun 28 07:04:35 PM PDT 24
Peak memory 201928 kb
Host smart-0deb6931-e71a-48f1-b43f-3907ff2d630d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374161218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1374161218
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.4055210812
Short name T307
Test name
Test status
Simulation time 330274087759 ps
CPU time 88.86 seconds
Started Jun 28 07:01:05 PM PDT 24
Finished Jun 28 07:02:36 PM PDT 24
Peak memory 202024 kb
Host smart-4e9914f8-e70f-4fc7-8e71-b5315c0b81a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055210812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.4055210812
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.194317956
Short name T707
Test name
Test status
Simulation time 324992595951 ps
CPU time 189.27 seconds
Started Jun 28 07:01:06 PM PDT 24
Finished Jun 28 07:04:16 PM PDT 24
Peak memory 201952 kb
Host smart-52f0c73a-ec7c-4099-824e-858bba59f6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194317956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.194317956
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.858344932
Short name T739
Test name
Test status
Simulation time 333192059725 ps
CPU time 695.92 seconds
Started Jun 28 07:01:05 PM PDT 24
Finished Jun 28 07:12:42 PM PDT 24
Peak memory 201872 kb
Host smart-8f0020f8-9bf9-47e3-8dec-4590ee6d1499
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=858344932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.858344932
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2518653736
Short name T473
Test name
Test status
Simulation time 492127636838 ps
CPU time 1180.79 seconds
Started Jun 28 07:01:06 PM PDT 24
Finished Jun 28 07:20:48 PM PDT 24
Peak memory 201920 kb
Host smart-8cea4753-5f0d-41d3-9ef7-364bb00ccb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518653736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2518653736
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1875869032
Short name T675
Test name
Test status
Simulation time 491398381561 ps
CPU time 1035.17 seconds
Started Jun 28 07:01:04 PM PDT 24
Finished Jun 28 07:18:21 PM PDT 24
Peak memory 201912 kb
Host smart-923ef215-bfb3-4129-ac2e-b59c366d1c92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875869032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1875869032
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2381998662
Short name T89
Test name
Test status
Simulation time 397708324490 ps
CPU time 239.36 seconds
Started Jun 28 07:01:05 PM PDT 24
Finished Jun 28 07:05:06 PM PDT 24
Peak memory 201864 kb
Host smart-47922955-c9c7-49a9-acdb-dcb3ec4367a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381998662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2381998662
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3122881634
Short name T784
Test name
Test status
Simulation time 69732660775 ps
CPU time 356.36 seconds
Started Jun 28 07:01:05 PM PDT 24
Finished Jun 28 07:07:03 PM PDT 24
Peak memory 202204 kb
Host smart-80272ffb-e890-4e57-9b10-607083a7aff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122881634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3122881634
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1362299854
Short name T508
Test name
Test status
Simulation time 23575449983 ps
CPU time 25.49 seconds
Started Jun 28 07:01:04 PM PDT 24
Finished Jun 28 07:01:31 PM PDT 24
Peak memory 201684 kb
Host smart-e138b2ac-3d97-4d84-9080-ad4458d18c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362299854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1362299854
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.213568663
Short name T728
Test name
Test status
Simulation time 5106379854 ps
CPU time 6.39 seconds
Started Jun 28 07:01:09 PM PDT 24
Finished Jun 28 07:01:17 PM PDT 24
Peak memory 201692 kb
Host smart-998e0217-b283-4882-8d79-0ff669750700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213568663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.213568663
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3703196523
Short name T440
Test name
Test status
Simulation time 5630852426 ps
CPU time 7.4 seconds
Started Jun 28 07:01:08 PM PDT 24
Finished Jun 28 07:01:17 PM PDT 24
Peak memory 201680 kb
Host smart-834cb52d-0f46-44dd-8220-63b2ff8f7536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703196523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3703196523
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3991006623
Short name T286
Test name
Test status
Simulation time 539330033034 ps
CPU time 1235.51 seconds
Started Jun 28 07:01:05 PM PDT 24
Finished Jun 28 07:21:42 PM PDT 24
Peak memory 201880 kb
Host smart-75c5588e-4b20-4f0f-a141-ea3f647ce2f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991006623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3991006623
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1508727688
Short name T37
Test name
Test status
Simulation time 420708760875 ps
CPU time 605.45 seconds
Started Jun 28 07:01:09 PM PDT 24
Finished Jun 28 07:11:16 PM PDT 24
Peak memory 210500 kb
Host smart-b5bc6b84-79ae-49d6-9c23-7dd67b41221a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508727688 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1508727688
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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