Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6788	1			T1	9		T3	8		T8	59
testmodes[AdcCtrlTestmodeNormal]	5071	1			T1	3		T2	2		T3	10
testmodes[AdcCtrlTestmodeLowpower]	5092	1			T7	16		T8	51		T9	13
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3894	1			T1	5		T3	4		T8	22
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1608	1			T1	3		T3	3		T8	18
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1172	1			T8	19		T12	1		T26	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1586	1			T1	3		T3	3		T8	24
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1910	1			T2	1		T3	7		T5	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1235	1			T8	15		T9	1		T11	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1190	1			T8	13		T9	1		T12	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1211	1			T8	21		T54	21		T136	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2446	1			T7	15		T8	17		T9	11