Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21298

1

T1

12

T2

14

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3896

1

T2

1

T5

27

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19340

1

T1

12

T2

1

T3

18

auto[1]

5854

1

T2

14

T9

5

T11

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	247	1			T127	18		T164	1		T90	40
values[1]	674	1			T9	29		T127	26		T222	22
values[2]	931	1			T6	14		T28	10		T52	37
values[3]	756	1			T5	22		T11	15		T13	4
values[4]	664	1			T4	18		T28	26		T53	1
values[5]	714	1			T2	14		T6	6		T126	1
values[6]	546	1			T2	1		T30	1		T55	20
values[7]	687	1			T5	27		T6	1		T9	5
values[8]	3074	1			T10	9		T14	7		T29	14
values[9]	885	1			T12	3		T28	11		T30	2
minimum	16016	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	713	1			T127	13		T62	29		T222	22
values[1]	834	1			T6	14		T52	37		T136	31
values[2]	741	1			T5	22		T11	15		T13	4
values[3]	732	1			T4	18		T28	26		T126	1
values[4]	707	1			T2	14		T6	6		T129	1
values[5]	564	1			T2	1		T9	5		T30	1
values[6]	3017	1			T5	27		T6	1		T11	1
values[7]	778	1			T10	9		T14	7		T30	1
values[8]	765	1			T12	3		T28	11		T30	1
values[9]	149	1			T127	18		T90	40		T223	14
minimum	16194	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T148	11		T16	6		T38	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T127	13		T62	16		T222	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	1		T52	21		T136	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T155	1		T185	6		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	13		T11	1		T53	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	2		T26	14		T28	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	10		T126	1		T47	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T28	12		T53	1		T32	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	1		T6	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T62	12		T35	3		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	3		T30	1		T55	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	1		T137	18		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T6	1		T29	1		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	13		T11	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T10	1		T14	4		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	1		T129	1		T55	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T164	1		T36	2		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T12	2		T28	6		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T127	18		T223	14		T225	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T90	21		T226	12		T227	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15953	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T228	1		T229	2		T230	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T16	4		T38	4		T231	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T62	13		T222	10		T185	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	13		T52	16		T136	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T155	11		T185	6		T232	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	9		T11	14		T43	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	2		T26	18		T28	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	8		T186	12		T231	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T28	14		T32	14		T137	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	13		T6	5		T135	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T62	14		T131	1		T140	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T9	2		T55	11		T37	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T137	10		T170	5		T101	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T29	13		T133	26		T233	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	14		T135	14		T136	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	8		T14	3		T224	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T55	11		T186	9		T234	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T170	13		T232	5		T187	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	1		T28	5		T48	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T235	10		T236	2		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T90	19		T238	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	17		T12	3		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T229	1		T230	11		T239	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T127	18		T164	1		T232	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T90	21		T226	12		T240	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	12		T127	13		T16	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T127	13		T222	12		T185	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	1		T52	21		T136	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T28	5		T62	16		T185	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	13		T11	1		T53	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	2		T26	14		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	10		T43	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T28	12		T53	1		T32	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	1		T6	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T35	3		T131	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T30	1		T55	9		T47	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	1		T62	12		T137	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	1		T9	3		T62	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	13		T11	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T10	1		T14	4		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T126	1		T129	1		T55	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T36	2		T83	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T12	2		T28	6		T30	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T232	5		T241	4		T242	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T90	19		T243	2		T244	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T9	17		T16	4		T38	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T222	10		T185	11		T154	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	13		T52	16		T136	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T28	5		T62	13		T185	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	9		T11	14		T46	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	2		T26	18		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	8		T43	10		T186	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T28	14		T32	14		T137	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	13		T6	5		T135	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T131	1		T140	8		T141	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T55	11		T245	14		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T62	14		T137	10		T170	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T9	2		T62	10		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	14		T135	14		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T10	8		T14	3		T29	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T55	11		T186	9		T234	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T146	10		T170	13		T141	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	1		T28	5		T48	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T148	1		T16	6		T38	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T127	1		T62	14		T222	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	14		T52	17		T136	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T155	12		T185	7		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	10		T11	15		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T13	4		T26	19		T28	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	9		T126	1		T47	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T28	15		T53	1		T32	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	14		T6	6		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T62	15		T35	2		T131	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T9	3		T30	1		T55	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	1		T137	11		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T6	1		T29	14		T133	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	15		T11	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T10	9		T14	4		T224	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T30	1		T129	1		T55	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T164	1		T36	2		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	2		T28	6		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T127	1		T223	1		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T90	20		T226	1		T227	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16063	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T228	1		T229	2		T230	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T148	10		T16	4		T38	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T127	12		T62	15		T222	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T52	20		T136	16		T246	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T185	5		T232	22		T18	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T5	12		T53	9		T46	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T26	13		T28	4		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	9		T47	6		T186	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T28	11		T32	10		T157	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T145	13		T245	16		T247	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T62	11		T35	1		T147	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T9	2		T55	8		T47	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T137	17		T170	8		T248	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T51	34		T136	15		T125	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	12		T136	9		T131	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	3		T146	9		T249	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T55	2		T186	10		T49	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T170	2		T232	9		T250	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T12	1		T28	5		T145	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T127	17		T223	13		T225	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T90	20		T226	11		T251	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T9	11		T127	12		T252	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T229	1		T230	13		T253	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T127	1		T164	1		T232	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T90	20		T226	1		T240	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	18		T127	1		T16	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T127	1		T222	11		T185	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	14		T52	17		T136	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T28	6		T62	14		T185	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	10		T11	15		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T13	4		T26	19		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	9		T43	11		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T28	15		T53	1		T32	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	14		T6	6		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T35	2		T131	2		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T30	1		T55	12		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	1		T62	15		T137	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	1		T9	3		T62	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	15		T11	1		T135	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T10	9		T14	4		T29	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T126	1		T129	1		T55	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T36	2		T83	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	2		T28	6		T30	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T127	17		T232	9		T223	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T90	20		T226	11		T240	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	11		T127	12		T16	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T127	12		T222	11		T185	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T52	20		T136	16		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T28	4		T62	15		T185	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	12		T53	9		T46	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T26	13		T46	2		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	9		T186	13		T199	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T28	11		T32	10		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T145	13		T247	21		T146	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T35	1		T147	8		T254	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T55	8		T47	5		T246	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T62	11		T137	17		T170	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	2		T62	15		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	12		T136	9		T131	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T14	3		T51	34		T136	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T55	2		T186	10		T49	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T146	9		T170	2		T147	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T12	1		T28	5		T145	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21889

1

T1

12

T3

18

T5

27

auto[ADC_CTRL_FILTER_COND_OUT]

3305

1

T2

15

T4

18

T5

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18763

1

T1

12

T2

1

T3

18

auto[1]

6431

1

T2

14

T5

27

T6

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	395	1			T8	6		T12	6		T54	3
values[0]	22	1			T149	5		T23	4		T252	2
values[1]	797	1			T2	1		T11	15		T55	20
values[2]	2899	1			T11	1		T28	26		T29	14
values[3]	759	1			T9	29		T13	1		T30	1
values[4]	555	1			T4	18		T5	22		T12	3
values[5]	771	1			T5	27		T6	15		T55	14
values[6]	514	1			T6	6		T129	1		T62	26
values[7]	772	1			T10	9		T13	3		T14	7
values[8]	750	1			T9	5		T28	11		T53	10
values[9]	1328	1			T2	14		T28	10		T30	1
minimum	15632	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	984	1			T2	1		T11	15		T136	20
values[1]	2953	1			T11	1		T28	26		T29	14
values[2]	634	1			T4	18		T5	22		T9	29
values[3]	705	1			T135	3		T55	14		T127	18
values[4]	679	1			T6	14		T127	13		T62	26
values[5]	565	1			T5	27		T6	7		T10	9
values[6]	674	1			T13	3		T14	7		T26	32
values[7]	886	1			T9	5		T28	10		T53	10
values[8]	980	1			T2	14		T30	1		T135	15
values[9]	106	1			T138	1		T90	2		T247	14
minimum	16028	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	1		T55	9		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T2	1		T136	10		T185	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1557	1			T11	1		T29	1		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T28	12		T30	2		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	12		T12	2		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	10		T5	13		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T135	1		T170	17		T248	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T55	3		T127	18		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T6	1		T62	16		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T127	13		T163	1		T47	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	13		T6	1		T10	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T6	1		T228	1		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	1		T14	4		T28	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T26	14		T136	17		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T28	5		T129	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	3		T53	10		T128	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T136	16		T130	1		T185	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	1		T30	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T138	1		T90	1		T247	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T17	2		T255	1		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T257	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	14		T55	11		T222	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T136	10		T185	6		T16	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T29	13		T133	26		T233	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T28	14		T62	14		T46	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	17		T12	1		T48	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	8		T5	9		T52	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T135	2		T170	14		T254	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T55	11		T232	5		T258	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	13		T62	10		T48	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T131	1		T259	1		T260	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	14		T10	8		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T6	5		T170	5		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	2		T14	3		T28	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T26	18		T136	14		T43	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T28	5		T155	11		T43	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T9	2		T186	9		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T136	14		T185	11		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	13		T135	14		T62	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T90	1		T247	1		T261	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T17	1		T262	11		T106	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T8	6		T12	6		T54	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T176	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T149	5		T23	1		T252	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	1		T55	9		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T2	1		T185	6		T148	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T11	1		T29	1		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T28	12		T30	1		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T9	12		T139	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	1		T30	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	2		T135	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	10		T5	13		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T5	13		T6	2		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T55	3		T127	31		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T129	1		T62	16		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T6	1		T139	1		T18	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T10	1		T13	1		T14	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T26	14		T136	17		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T28	6		T129	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	3		T53	10		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T28	5		T136	16		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T2	1		T30	1		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15509	1			T1	12		T3	18		T7	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T23	3		T263	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	14		T55	11		T222	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T185	6		T16	4		T90	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T29	13		T133	26		T233	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T28	14		T136	10		T62	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	17		T140	8		T171	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T52	16		T32	14		T101	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	1		T135	2		T48	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T4	8		T5	9		T141	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	14		T6	13		T170	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T55	11		T131	1		T260	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T62	10		T48	9		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T6	5		T18	2		T259	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T10	8		T13	2		T14	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T26	18		T136	14		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T28	5		T155	11		T43	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	2		T43	3		T186	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T28	5		T136	14		T185	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T2	13		T135	14		T62	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3