Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21544

1

T1

12

T2

1

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3650

1

T2

14

T4

18

T5

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18991

1

T1

12

T2

1

T3

18

auto[1]

6203

1

T2

14

T4

18

T5

49

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	229	1			T30	1		T135	3		T163	1
values[0]	75	1			T10	9		T62	29		T46	10
values[1]	612	1			T9	34		T145	9		T130	1
values[2]	688	1			T6	14		T13	3		T30	1
values[3]	748	1			T4	18		T135	15		T55	20
values[4]	806	1			T2	14		T12	3		T13	1
values[5]	3009	1			T6	6		T11	1		T14	7
values[6]	496	1			T6	1		T30	1		T126	1
values[7]	644	1			T28	11		T128	1		T130	1
values[8]	790	1			T2	1		T11	15		T28	26
values[9]	1081	1			T5	49		T28	10		T127	13
minimum	16016	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	658	1			T6	14		T9	5		T30	1
values[1]	640	1			T13	3		T52	37		T129	2
values[2]	867	1			T4	18		T13	1		T26	32
values[3]	2990	1			T2	14		T12	3		T29	14
values[4]	629	1			T6	7		T11	1		T14	7
values[5]	554	1			T126	1		T53	1		T145	14
values[6]	728	1			T11	15		T28	11		T136	30
values[7]	751	1			T2	1		T5	49		T28	36
values[8]	919	1			T30	1		T127	13		T128	1
values[9]	162	1			T135	3		T163	1		T274	14
minimum	16296	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	1		T155	1		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	3		T30	1		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T52	21		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T129	1		T135	1		T127	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T13	1		T187	1		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	10		T26	14		T55	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T12	2		T29	1		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T136	17		T148	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T11	1		T14	4		T136	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T6	2		T30	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T126	1		T185	6		T186	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T53	1		T145	14		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T136	16		T128	1		T62	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T11	1		T28	6		T47	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	1		T5	13		T28	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	13		T28	5		T127	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T128	1		T43	1		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T30	1		T127	13		T222	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T163	1		T274	5		T327	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T135	1		T156	1		T250	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15981	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T9	12		T246	16		T141	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T6	13		T155	11		T146	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	2		T131	1		T146	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	2		T52	16		T131	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T135	14		T48	9		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T187	10		T156	12		T157	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	8		T26	18		T55	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T12	1		T29	13		T133	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	13		T136	14		T84	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T14	3		T136	10		T43	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	5		T55	11		T48	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T185	6		T186	9		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T273	10		T254	11		T278	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T136	14		T62	10		T46	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	14		T28	5		T131	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	9		T28	14		T245	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	14		T28	5		T90	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T43	3		T185	11		T38	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T222	10		T137	11		T170	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T274	9		T327	12		T190	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T135	2		T156	8		T284	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	8		T12	3		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T9	17		T141	17		T293	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T163	1		T275	1		T328	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T30	1		T135	1		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T10	1		T62	16		T46	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T145	9		T130	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	15		T131	1		T246	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	1		T13	1		T52	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	1		T129	1		T127	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T49	3		T187	1		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	10		T135	1		T55	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	2		T13	1		T53	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	1		T26	14		T136	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T11	1		T14	4		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T6	1		T126	1		T55	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T126	1		T136	10		T185	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	1		T30	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T128	1		T62	16		T46	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T28	6		T130	1		T47	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T2	1		T28	12		T136	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	1		T127	18		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T5	13		T128	1		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T5	13		T28	5		T127	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T275	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T135	2		T156	8		T284	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T10	8		T62	13		T46	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T155	11		T48	4		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	19		T131	1		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	13		T13	2		T52	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T17	1		T254	10		T279	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T187	10		T156	12		T157	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	8		T135	14		T55	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	1		T62	14		T232	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	13		T26	18		T136	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T14	3		T29	13		T133	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	5		T55	11		T48	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T136	10		T185	6		T90	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T101	14		T273	10		T254	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T62	10		T46	3		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T28	5		T40	1		T224	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T28	14		T136	14		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	14		T131	11		T171	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	9		T43	3		T185	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	14		T28	5		T222	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	14		T155	12		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	3		T30	1		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	3		T52	17		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T129	1		T135	15		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	1		T187	11		T156	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T4	9		T26	19		T55	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T12	2		T29	14		T133	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	14		T136	15		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	1		T14	4		T136	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T6	7		T30	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T126	1		T185	7		T186	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T53	1		T145	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T136	15		T128	1		T62	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	15		T28	6		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	1		T5	10		T28	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	15		T28	6		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T128	1		T43	4		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T30	1		T127	1		T222	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T163	1		T274	10		T327	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T135	3		T156	9		T250	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16081	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T9	18		T246	1		T141	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T146	9		T170	8		T232	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T9	2		T246	5		T146	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T52	20		T35	1		T49	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T127	12		T250	16		T150	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T280	5		T157	13		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	9		T26	13		T55	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T12	1		T51	34		T53	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T136	16		T148	14		T247	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T14	3		T136	9		T16	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T55	2		T186	13		T249	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T185	5		T186	10		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T145	13		T148	9		T147	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T136	15		T62	15		T46	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T28	5		T47	5		T131	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	12		T28	11		T47	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	12		T28	4		T127	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T185	10		T38	3		T223	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T127	12		T222	11		T137	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T274	4		T327	10		T257	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T250	15		T284	13		T288	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T145	8		T62	15		T46	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T9	11		T246	15		T253	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T163	1		T275	11		T328	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T30	1		T135	3		T156	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T10	9		T62	14		T46	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T145	1		T130	1		T155	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	21		T131	2		T246	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	14		T13	3		T52	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T30	1		T129	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T49	2		T187	11		T156	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	9		T135	15		T55	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	2		T13	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	14		T26	19		T136	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T11	1		T14	4		T29	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	6		T126	1		T55	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T126	1		T136	11		T185	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T6	1		T30	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T128	1		T62	11		T46	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T28	6		T130	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	1		T28	15		T136	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	15		T127	1		T131	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	10		T128	1		T43	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T5	15		T28	6		T127	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T328	15		T329	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T223	11		T284	13		T288	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T62	15		T46	2		T232	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T145	8		T146	9		T170	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	13		T246	20		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T52	20		T35	1		T281	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T127	12		T254	8		T250	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	1		T199	4		T280	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T4	9		T55	8		T267	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T53	9		T62	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T26	13		T136	16		T148	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T14	3		T51	34		T125	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T55	2		T186	13		T249	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T136	9		T185	5		T258	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T145	13		T148	9		T147	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T62	15		T46	5		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T28	5		T47	5		T170	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T28	11		T136	15		T47	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T127	17		T131	12		T270	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	12		T185	10		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T5	12		T28	4		T127	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13