Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21518

1

T1

12

T3

18

T4

18

auto[ADC_CTRL_FILTER_COND_OUT]

3676

1

T2

15

T5

27

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18997

1

T1

12

T3

18

T4

18

auto[1]

6197

1

T2

15

T5

49

T6

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	317	1			T10	9		T12	3		T126	1
values[0]	47	1			T126	1		T259	20		T315	1
values[1]	632	1			T53	1		T128	1		T130	1
values[2]	2924	1			T4	18		T29	14		T133	29
values[3]	551	1			T2	1		T6	1		T127	13
values[4]	673	1			T6	14		T11	15		T28	11
values[5]	509	1			T2	14		T11	1		T28	26
values[6]	967	1			T5	27		T6	6		T136	61
values[7]	743	1			T5	22		T13	3		T135	15
values[8]	960	1			T9	5		T26	32		T30	1
values[9]	855	1			T9	29		T13	1		T14	7
minimum	16016	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	628	1			T53	11		T130	1		T62	26
values[1]	2932	1			T4	18		T6	1		T29	14
values[2]	666	1			T2	1		T127	13		T163	1
values[3]	579	1			T2	14		T6	14		T11	15
values[4]	583	1			T11	1		T28	26		T30	1
values[5]	906	1			T5	27		T6	6		T136	61
values[6]	718	1			T5	22		T13	3		T135	15
values[7]	1011	1			T9	34		T26	32		T30	1
values[8]	806	1			T10	9		T12	3		T13	1
values[9]	186	1			T136	20		T231	12		T274	14
minimum	16179	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T47	7		T132	1		T100	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T53	11		T130	1		T62	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T4	10		T29	1		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	1		T135	1		T35	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T127	13		T163	1		T185	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	1		T40	3		T84	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T28	6		T46	3		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T6	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	1		T55	9		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T28	12		T30	1		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T6	1		T136	16		T145	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	13		T136	17		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	13		T13	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T148	25		T138	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T26	14		T129	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T9	15		T30	1		T127	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T10	1		T12	2		T28	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	1		T14	4		T52	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T231	1		T187	1		T292	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T136	10		T274	5		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15945	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T126	1		T146	1		T259	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T100	14		T241	4		T331	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T62	10		T245	14		T101	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T4	8		T29	13		T133	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T135	2		T186	9		T90	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T185	6		T170	13		T258	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T40	1		T84	11		T101	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T28	5		T46	7		T48	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	13		T6	13		T11	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T55	11		T155	11		T222	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T28	14		T170	5		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	5		T136	14		T131	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	14		T136	14		T48	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	9		T13	2		T135	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T154	2		T224	6		T231	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T26	18		T137	1		T16	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	19		T62	14		T131	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	8		T12	1		T28	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	3		T52	16		T32	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T231	11		T187	8		T302	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T136	10		T274	9		T172	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	3		T32	4		T43	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T171	10		T332	7		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T10	1		T12	2		T126	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T136	10		T62	16		T146	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T315	1		T333	18		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T126	1		T259	20		T177	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T128	1		T43	1		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T53	1		T130	1		T62	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T4	10		T29	1		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T53	10		T135	1		T35	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T127	13		T163	1		T148	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	1		T6	1		T186	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	6		T46	3		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	1		T11	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	1		T55	9		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	1		T28	12		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T6	1		T136	16		T145	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	13		T136	17		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	13		T13	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T148	25		T138	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T26	14		T129	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	3		T30	1		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	5		T127	18		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	12		T13	1		T14	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T10	8		T12	1		T90	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T136	10		T62	13		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T43	10		T241	4		T284	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T62	10		T245	14		T231	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T4	8		T29	13		T133	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T135	2		T90	19		T17	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T170	13		T258	13		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T186	9		T84	11		T101	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T28	5		T46	7		T48	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	13		T11	14		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T55	11		T39	1		T293	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T2	13		T28	14		T185	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T6	5		T136	14		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	14		T136	14		T48	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T5	9		T13	2		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T154	2		T17	1		T231	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T26	18		T137	1		T16	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	2		T131	1		T224	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T28	5		T137	10		T231	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T9	17		T14	3		T52	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T47	1		T132	1		T100	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T53	2		T130	1		T62	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T4	9		T29	14		T133	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	1		T135	3		T35	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T127	1		T163	1		T185	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	1		T40	4		T84	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T28	6		T46	8		T48	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	14		T6	14		T11	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	1		T55	12		T155	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T28	15		T30	1		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T6	6		T136	15		T145	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	15		T136	15		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	10		T13	3		T135	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T148	2		T138	1		T154	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T26	19		T129	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	21		T30	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T10	9		T12	2		T28	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T13	1		T14	4		T52	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T231	12		T187	9		T292	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T136	11		T274	10		T172	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T126	1		T146	1		T259	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T47	6		T100	12		T290	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T53	9		T62	15		T245	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1211	1			T4	9		T51	34		T125	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T35	1		T186	10		T90	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T127	12		T185	5		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T254	15		T230	13		T250	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T28	5		T46	2		T186	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T185	10		T199	4		T223	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T55	8		T222	11		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T28	11		T246	15		T170	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T136	15		T145	21		T131	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	12		T136	16		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	12		T37	6		T146	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T148	23		T49	1		T147	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T26	13		T16	4		T232	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	13		T127	12		T62	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T28	4		T127	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	3		T52	20		T32	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T302	17		T319	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T136	9		T274	4		T334	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T284	13		T310	12		T243	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T259	19		T225	15		T327	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T10	9		T12	2		T126	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T136	11		T62	14		T146	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T315	1		T333	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T126	1		T259	1		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T128	1		T43	11		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T53	1		T130	1		T62	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T4	9		T29	14		T133	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T53	1		T135	3		T35	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T127	1		T163	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	1		T6	1		T186	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T28	6		T46	8		T48	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	14		T11	15		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	1		T55	12		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	14		T28	15		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T6	6		T136	15		T145	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	15		T136	15		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	10		T13	3		T135	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T148	2		T138	1		T154	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T26	19		T129	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	3		T30	1		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T28	6		T127	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T9	18		T13	1		T14	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T12	1		T147	15		T254	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T136	9		T62	15		T146	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T333	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T259	19		T177	2		T335	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T284	13		T331	8		T310	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T62	15		T245	16		T229	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T4	9		T51	34		T125	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T53	9		T35	1		T90	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T127	12		T148	10		T246	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T186	10		T254	15		T250	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T28	5		T46	2		T185	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T199	4		T230	13		T226	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T55	8		T39	1		T265	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T28	11		T185	10		T246	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T136	15		T145	21		T222	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	12		T136	16		T170	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	12		T37	6		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T148	23		T49	1		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T26	13		T16	4		T232	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T9	2		T50	1		T149	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T28	4		T127	17		T137	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T9	11		T14	3		T52	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13