Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19192

1

T1

12

T3

18

T5

27

auto[ADC_CTRL_FILTER_COND_OUT]

6002

1

T2

15

T4

18

T5

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19240

1

T1

12

T2

1

T3

18

auto[1]

5954

1

T2

14

T4

18

T5

49

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	200	1			T246	2		T83	1		T100	27
values[0]	55	1			T234	32		T325	10		T326	13
values[1]	657	1			T9	29		T126	1		T145	9
values[2]	665	1			T28	36		T131	26		T132	1
values[3]	671	1			T2	1		T6	15		T129	1
values[4]	680	1			T26	32		T30	2		T136	30
values[5]	748	1			T5	22		T9	5		T10	9
values[6]	736	1			T5	27		T6	6		T126	1
values[7]	803	1			T2	14		T11	1		T12	3
values[8]	642	1			T4	18		T13	3		T43	11
values[9]	3321	1			T11	15		T13	1		T14	7
minimum	16016	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	561	1			T9	29		T126	1		T145	9
values[1]	2980	1			T2	1		T28	36		T29	14
values[2]	639	1			T6	15		T26	32		T30	1
values[3]	695	1			T30	2		T129	1		T136	30
values[4]	718	1			T5	22		T10	9		T28	11
values[5]	760	1			T5	27		T6	6		T9	5
values[6]	778	1			T11	1		T12	3		T135	15
values[7]	552	1			T2	14		T4	18		T13	3
values[8]	1032	1			T11	15		T13	1		T55	34
values[9]	121	1			T83	1		T234	16		T253	8
minimum	16358	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T126	1		T145	9		T62	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	12		T130	1		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T28	5		T130	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1696	1			T2	1		T28	12		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	1		T30	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	1		T26	14		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T136	16		T163	1		T309	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T30	2		T129	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	1		T28	6		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	13		T127	18		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	13		T46	3		T47	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	1		T9	3		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T135	1		T222	12		T38	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	1		T12	2		T136	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	1		T14	4		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	1		T4	10		T53	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T47	7		T186	11		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T11	1		T13	1		T55	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T83	1		T261	1		T336	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T234	8		T253	8		T226	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15946	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T40	3		T231	1		T234	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T62	13		T155	11		T17	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	17		T43	3		T137	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T28	5		T131	1		T84	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1060	1			T28	14		T29	13		T133	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T6	13		T230	11		T242	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T26	18		T131	1		T185	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T136	14		T146	10		T170	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T62	10		T46	3		T48	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	8		T28	5		T135	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	9		T17	1		T273	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	14		T46	7		T48	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T6	5		T9	2		T52	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T135	14		T222	10		T38	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	1		T136	10		T185	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T13	2		T14	3		T48	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	13		T4	8		T43	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T186	9		T154	2		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	14		T55	22		T90	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T261	11		T336	9		T321	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T234	8		T337	9		T338	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	3		T32	4		T43	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T40	1		T231	7		T234	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T83	1		T100	13		T292	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T246	2		T150	22		T284	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T326	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T234	17		T325	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T126	1		T145	9		T62	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	12		T130	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T28	5		T131	1		T84	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T28	12		T131	13		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	1		T129	1		T145	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	1		T6	1		T62	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T30	1		T136	16		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T26	14		T30	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	1		T28	6		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	13		T9	3		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	13		T136	17		T46	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	1		T126	1		T52	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T135	1		T222	12		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	1		T11	1		T12	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	1		T139	2		T247	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	10		T43	1		T247	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T14	4		T47	7		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1698	1			T11	1		T13	1		T29	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T100	14		T339	6		T173	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T284	1		T300	2		T340	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T234	15		T325	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T62	13		T155	11		T156	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	17		T43	3		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T28	5		T131	1		T84	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T28	14		T131	11		T137	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T6	13		T34	2		T230	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T62	14		T131	1		T185	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T136	14		T146	10		T101	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T26	18		T62	10		T46	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	8		T28	5		T135	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	9		T9	2		T48	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	14		T136	14		T46	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	5		T52	16		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T135	14		T222	10		T38	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	13		T12	1		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	2		T247	2		T101	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T4	8		T43	10		T247	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T14	3		T48	13		T186	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1090	1			T11	14		T29	13		T133	26
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T126	1		T145	1		T62	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	18		T130	1		T43	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T28	6		T130	1		T131	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1422	1			T2	1		T28	15		T29	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	14		T30	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	1		T26	19		T131	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T136	15		T163	1		T309	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T30	2		T129	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	9		T28	6		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	10		T127	1		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T5	15		T46	8		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	6		T9	3		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T135	15		T222	11		T38	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	1		T12	2		T136	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T13	3		T14	4		T48	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	14		T4	9		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T47	1		T186	10		T154	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	15		T13	1		T55	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T83	1		T261	12		T336	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T234	9		T253	1		T226	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16070	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	4		T231	8		T234	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T145	8		T62	15		T17	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T9	11		T137	17		T148	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T28	4		T158	2		T282	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1334	1			T28	11		T51	34		T125	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T145	13		T280	5		T230	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T26	13		T185	5		T16	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T136	15		T148	9		T146	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T62	15		T46	5		T246	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T28	5		T136	16		T32	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	12		T127	17		T246	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	12		T46	2		T47	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	2		T52	20		T127	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T222	11		T38	3		T247	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	1		T136	9		T127	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	3		T255	8		T248	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	9		T53	9		T247	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T47	6		T186	10		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T55	10		T35	1		T246	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T257	6		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T234	7		T253	7		T226	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T249	12		T147	4		T341	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T234	16		T320	6		T342	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T83	1		T100	15		T292	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T246	1		T150	1		T284	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T326	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T234	16		T325	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T126	1		T145	1		T62	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T9	18		T130	1		T43	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T28	6		T131	2		T84	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T28	15		T131	12		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	14		T129	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T6	1		T62	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T30	1		T136	15		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T26	19		T30	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T10	9		T28	6		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	10		T9	3		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	15		T136	15		T46	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	6		T126	1		T52	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T135	15		T222	11		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	14		T11	1		T12	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	3		T139	2		T247	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	9		T43	11		T247	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T14	4		T47	1		T48	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1451	1			T11	15		T13	1		T29	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T100	12		T173	5		T343	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T246	1		T150	21		T253	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T326	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T234	16		T325	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T145	8		T62	15		T249	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	11		T148	10		T199	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T28	4		T17	3		T229	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T28	11		T131	12		T137	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T145	13		T280	5		T230	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T62	11		T185	5		T148	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T136	15		T148	9		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T26	13		T62	15		T46	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T28	5		T32	10		T49	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	12		T9	2		T246	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	12		T136	16		T46	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T52	20		T127	29		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T222	11		T38	3		T264	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	1		T136	9		T127	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T247	9		T248	4		T341	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	9		T247	12		T170	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T14	3		T47	6		T186	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1337	1			T51	34		T53	9		T125	22

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13