Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21821

1

T1

12

T2

14

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3373

1

T2

1

T4

18

T5

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18775

1

T1

12

T2

15

T3

18

auto[1]

6419

1

T5

27

T8

6

T10

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	517	1			T8	6		T12	6		T54	3
values[0]	41	1			T222	22		T149	5		T329	14
values[1]	758	1			T2	1		T11	15		T55	20
values[2]	2916	1			T11	1		T28	26		T29	14
values[3]	725	1			T4	18		T12	3		T13	1
values[4]	620	1			T5	22		T9	29		T135	3
values[5]	710	1			T6	15		T55	14		T127	31
values[6]	550	1			T5	27		T6	6		T126	1
values[7]	778	1			T10	9		T13	3		T14	7
values[8]	796	1			T9	5		T28	11		T129	1
values[9]	1151	1			T2	14		T28	10		T30	1
minimum	15632	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	710	1			T2	1		T11	15		T136	20
values[1]	2966	1			T11	1		T28	26		T29	14
values[2]	681	1			T4	18		T9	29		T12	3
values[3]	663	1			T5	22		T135	3		T55	14
values[4]	703	1			T6	15		T127	31		T62	26
values[5]	537	1			T5	27		T6	6		T126	1
values[6]	724	1			T10	9		T13	3		T14	7
values[7]	855	1			T9	5		T28	10		T53	10
values[8]	1036	1			T2	14		T30	1		T135	15
values[9]	58	1			T90	2		T247	14		T17	3
minimum	16261	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	1		T55	9		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	1		T136	10		T148	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T28	12		T29	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	1		T126	1		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	2		T52	21		T48	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	10		T9	12		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T138	1		T241	1		T248	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	13		T135	1		T55	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T6	2		T62	16		T47	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T127	31		T163	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	13		T126	1		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	1		T228	1		T39	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	1		T13	1		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T26	14		T136	17		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T128	1		T155	1		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T9	3		T28	5		T53	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	1		T30	1		T136	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T135	1		T130	1		T62	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T90	1		T247	13		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T261	1		T200	6		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15966	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T222	12		T185	6		T146	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	14		T55	11		T131	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T136	10		T16	4		T245	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T28	14		T29	13		T133	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T46	7		T38	4		T247	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	1		T52	16		T48	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	8		T9	17		T32	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T241	4		T254	12		T344	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	9		T135	2		T55	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	13		T62	10		T17	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T48	9		T131	1		T259	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	14		T34	11		T187	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T6	5		T39	1		T170	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	8		T13	2		T14	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T26	18		T136	14		T137	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T155	11		T43	10		T154	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	2		T28	5		T46	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	13		T136	14		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T135	14		T62	13		T185	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T90	1		T247	1		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T261	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	3		T32	4		T43	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T222	10		T185	6		T146	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	432	1			T8	6		T12	6		T54	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T130	1		T255	1		T254	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T149	5		T329	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T222	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	1		T55	9		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	1		T185	6		T148	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T28	12		T29	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	1		T53	1		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	2		T52	21		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	10		T13	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T48	1		T132	1		T186	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	13		T9	12		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T6	2		T47	7		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T55	3		T127	31		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	13		T126	1		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	1		T43	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T10	1		T13	1		T14	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T26	14		T136	17		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T28	6		T155	1		T43	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	3		T129	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T2	1		T30	1		T136	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T28	5		T53	10		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15509	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T90	1		T247	1		T17	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T254	11		T272	7		T345	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T329	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T222	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	14		T55	11		T37	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T185	6		T16	4		T245	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T28	14		T29	13		T133	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T136	10		T46	7		T38	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	1		T52	16		T48	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	8		T32	14		T101	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T48	4		T186	12		T241	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	9		T9	17		T135	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	13		T231	7		T34	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T55	11		T131	1		T260	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	14		T62	10		T17	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T6	5		T48	9		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	8		T13	2		T14	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T26	18		T136	14		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T28	5		T155	11		T43	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	2		T46	3		T186	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	13		T136	14		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T28	5		T135	14		T62	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	15		T55	12		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	1		T136	11		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T28	15		T29	14		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	1		T126	1		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	2		T52	17		T48	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	9		T9	18		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T138	1		T241	5		T248	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	10		T135	3		T55	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	15		T62	11		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T127	2		T163	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	15		T126	1		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	6		T228	1		T39	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T10	9		T13	3		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T26	19		T136	15		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T128	1		T155	12		T43	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T9	3		T28	6		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	14		T30	1		T136	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T135	15		T130	1		T62	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T90	2		T247	2		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T261	8		T200	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16093	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T222	11		T185	7		T146	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T55	8		T131	12		T246	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T136	9		T148	10		T16	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T28	11		T51	34		T125	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T145	8		T46	2		T38	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T52	20		T186	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	9		T9	11		T32	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T248	4		T254	11		T266	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	12		T55	2		T170	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T62	15		T47	6		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T127	29		T270	24		T259	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T5	12		T148	9		T249	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T39	1		T170	8		T150	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	3		T28	5		T100	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T26	13		T136	16		T264	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T148	14		T255	8		T199	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	2		T28	4		T53	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T136	15		T137	17		T258	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T62	15		T185	10		T249	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T247	12		T17	1		T253	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T200	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T157	9		T149	4		T337	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T222	11		T185	5		T146	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	427	1			T8	6		T12	6		T54	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T130	1		T255	1		T254	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T149	1		T329	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T222	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T11	15		T55	12		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	1		T185	7		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T28	15		T29	14		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	1		T53	1		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	2		T52	17		T48	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	9		T13	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T48	5		T132	1		T186	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	10		T9	18		T135	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	15		T47	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T55	12		T127	2		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	15		T126	1		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	6		T43	1		T48	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	9		T13	3		T14	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T26	19		T136	15		T137	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T28	6		T155	12		T43	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	3		T129	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T2	14		T30	1		T136	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T28	6		T53	1		T135	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15632	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T247	12		T17	1		T258	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T254	15		T272	2		T200	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T149	4		T329	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T222	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T55	8		T37	6		T170	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T185	5		T148	10		T16	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T28	11		T51	34		T125	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T136	9		T46	2		T38	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	1		T52	20		T274	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	9		T32	10		T145	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T186	13		T248	4		T266	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	12		T9	11		T170	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T47	6		T147	4		T254	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T55	2		T127	29		T270	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	12		T62	15		T148	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	1		T170	8		T150	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	3		T100	12		T290	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T26	13		T136	16		T267	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T28	5		T148	14		T255	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	2		T46	5		T186	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T136	15		T137	17		T151	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T28	4		T53	9		T62	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13