Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21648

1

T1

12

T3

18

T4

18

auto[ADC_CTRL_FILTER_COND_OUT]

3546

1

T2

15

T5

49

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19242

1

T1

12

T2

15

T3

18

auto[1]

5952

1

T5

27

T6

1

T10

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	343	1			T28	10		T126	1		T43	4
values[0]	82	1			T5	27		T46	10		T147	9
values[1]	725	1			T4	18		T9	5		T53	11
values[2]	806	1			T2	1		T6	14		T9	29
values[3]	639	1			T11	15		T14	7		T30	1
values[4]	730	1			T11	1		T55	14		T127	13
values[5]	2906	1			T13	1		T29	14		T133	29
values[6]	663	1			T6	6		T30	1		T127	13
values[7]	600	1			T2	14		T5	22		T28	11
values[8]	733	1			T12	3		T26	32		T30	1
values[9]	951	1			T6	1		T28	26		T129	1
minimum	16016	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	756	1			T4	18		T5	27		T9	34
values[1]	748	1			T2	1		T6	14		T13	3
values[2]	711	1			T11	15		T14	7		T30	1
values[3]	2941	1			T11	1		T29	14		T133	29
values[4]	616	1			T6	6		T13	1		T135	15
values[5]	690	1			T30	1		T55	20		T127	13
values[6]	767	1			T2	14		T5	22		T26	32
values[7]	620	1			T12	3		T28	26		T30	1
values[8]	884	1			T6	1		T28	10		T129	1
values[9]	176	1			T126	1		T164	1		T131	24
minimum	16285	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	10		T9	12		T10	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	13		T9	3		T53	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T135	1		T32	11		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	1		T6	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	1		T14	4		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T136	16		T101	1		T270	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1564	1			T29	1		T133	3		T51	36
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	1		T130	1		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	1		T145	9		T249	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T135	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T137	18		T138	1		T38	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T30	1		T55	9		T127	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T28	6		T129	1		T136	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	1		T5	13		T26	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	2		T28	12		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T126	1		T130	1		T62	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T28	5		T129	1		T127	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T6	1		T136	17		T145	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T126	1		T164	1		T246	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T131	13		T249	13		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15971	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T46	3		T139	1		T170	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	8		T9	17		T10	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	14		T9	2		T231	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T135	2		T32	14		T62	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	13		T13	2		T52	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	14		T14	3		T55	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T136	14		T101	14		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T29	13		T133	26		T233	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T255	13		T234	15		T171	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	5		T140	8		T272	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T135	14		T247	1		T170	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T137	10		T38	4		T273	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T55	11		T43	10		T48	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T28	5		T136	10		T62	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	13		T5	9		T26	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	1		T28	14		T185	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T62	13		T186	9		T245	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T28	5		T43	3		T46	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T136	14		T155	11		T48	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T274	9		T31	1		T346	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T131	11		T141	4		T232	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	3		T32	4		T43	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T46	7		T170	5		T282	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T28	5		T126	1		T43	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T232	12		T255	1		T230	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T147	9		T235	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T5	13		T46	3		T292	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T4	10		T35	3		T186	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	3		T53	11		T148	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T9	12		T10	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	1		T6	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	1		T14	4		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T136	16		T139	1		T270	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T55	3		T127	13		T16	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	1		T101	1		T276	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T29	1		T133	3		T51	36
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	1		T135	1		T55	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	1		T137	18		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T30	1		T127	13		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T28	6		T129	1		T36	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	1		T5	13		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	2		T30	1		T136	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T26	14		T126	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T28	12		T129	1		T127	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T6	1		T136	17		T145	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T28	5		T43	3		T274	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T232	14		T230	11		T213	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T235	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T5	14		T46	7		T282	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	8		T186	12		T156	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T9	2		T170	5		T231	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T9	17		T10	8		T135	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	13		T13	2		T52	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	14		T14	3		T32	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T136	14		T254	10		T276	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T55	11		T16	4		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T101	14		T234	15		T171	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T29	13		T133	26		T233	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T135	14		T55	11		T247	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	5		T137	10		T38	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T170	14		T17	1		T264	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T28	5		T90	1		T273	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	13		T5	9		T43	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	1		T136	10		T62	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T26	18		T245	14		T84	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T28	14		T46	3		T185	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T136	14		T62	13		T155	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T4	9		T9	18		T10	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	15		T9	3		T53	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T135	3		T32	15		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	1		T6	14		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	15		T14	4		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T136	15		T101	15		T270	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T29	14		T133	29		T51	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	1		T130	1		T255	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	6		T145	1		T249	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	1		T135	15		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T137	11		T138	1		T38	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T30	1		T55	12		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T28	6		T129	1		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	14		T5	10		T26	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	2		T28	15		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T126	1		T130	1		T62	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T28	6		T129	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	1		T136	15		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T126	1		T164	1		T246	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T131	12		T249	1		T141	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16097	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T46	8		T139	1		T170	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	9		T9	11		T35	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	12		T9	2		T53	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T32	10		T62	15		T47	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T52	20		T17	3		T50	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T14	3		T55	2		T127	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T136	15		T270	24		T254	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T51	34		T125	22		T144	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T280	5		T149	7		T234	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T145	8		T249	7		T281	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T247	12		T170	16		T199	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T137	17		T38	3		T266	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T55	8		T127	12		T148	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T28	5		T136	9		T62	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	12		T26	13		T90	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T12	1		T28	11		T47	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T62	15		T186	10		T245	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T28	4		T127	17		T46	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T136	16		T145	13		T37	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T246	1		T274	4		T151	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T131	12		T249	12		T232	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T147	8		T300	12		T283	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T46	2		T170	8		T151	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T28	6		T126	1		T43	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T232	15		T255	1		T230	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T147	1		T235	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T5	15		T46	8		T292	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T4	9		T35	2		T186	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	3		T53	2		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	18		T10	9		T135	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	1		T6	14		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	15		T14	4		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T136	15		T139	1		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T55	12		T127	1		T16	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	1		T101	15		T276	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T29	14		T133	29		T51	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	1		T135	15		T55	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	6		T137	11		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T30	1		T127	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T28	6		T129	1		T36	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	14		T5	10		T43	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	2		T30	1		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T26	19		T126	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T28	15		T129	1		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	1		T136	15		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T28	4		T246	1		T274	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T232	11		T230	13		T213	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T147	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T5	12		T46	2		T282	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	9		T35	1		T186	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	2		T53	9		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	11		T62	15		T232	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T52	20		T17	3		T50	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	3		T32	10		T47	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T136	15		T270	24		T254	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T55	2		T127	12		T16	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T234	16		T271	11		T282	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T51	34		T125	22		T144	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T55	8		T247	12		T280	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T137	17		T38	3		T266	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T127	12		T170	16		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T28	5		T248	4		T253	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	12		T148	14		T90	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	1		T136	9		T62	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	13		T245	16		T146	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T28	11		T127	17		T46	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T136	16		T145	13		T62	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13