Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T11	15		T55	12		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	1		T136	11		T185	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T11	1		T29	14		T133	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T28	15		T30	2		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	18		T12	2		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	9		T5	10		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T135	3		T170	15		T248	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T55	12		T127	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	14		T62	11		T48	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T127	1		T163	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	15		T6	1		T10	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	6		T228	1		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	3		T14	4		T28	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T26	19		T136	15		T43	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T28	6		T129	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	3		T53	1		T128	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T136	15		T130	1		T185	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T2	14		T30	1		T135	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T138	1		T90	2		T247	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T17	2		T255	1		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T257	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T55	8		T222	11		T131	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T136	9		T185	5		T148	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T51	34		T125	22		T144	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T28	11		T62	11		T46	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	11		T12	1		T186	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	9		T5	12		T52	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T170	16		T248	4		T254	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T55	2		T127	17		T232	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T62	15		T17	3		T147	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T127	12		T47	6		T250	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	12		T148	9		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T170	8		T18	3		T19	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	3		T28	5		T100	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T26	13		T136	16		T264	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T28	4		T46	5		T148	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	2		T53	9		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T136	15		T185	10		T137	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T62	15		T265	1		T230	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T247	12		T151	2		T253	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T17	1		T200	5		T105	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T257	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T8	6		T12	6		T54	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T176	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T149	1		T23	4		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	15		T55	12		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	1		T185	7		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T11	1		T29	14		T133	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T28	15		T30	1		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	18		T139	1		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	1		T30	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	2		T135	3		T48	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	9		T5	10		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	15		T6	15		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T55	12		T127	2		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T129	1		T62	11		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T6	6		T139	1		T18	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T10	9		T13	3		T14	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T26	19		T136	15		T137	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T28	6		T129	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	3		T53	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T28	6		T136	15		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T2	14		T30	1		T135	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15632	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T253	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T149	4		T252	1		T263	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T55	8		T222	11		T37	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T185	5		T148	10		T16	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T51	34		T125	22		T144	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T28	11		T136	9		T145	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	11		T199	13		T266	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T52	20		T32	10		T145	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	1		T186	13		T248	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T4	9		T5	12		T232	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	12		T170	16		T147	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T55	2		T127	29		T47	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T62	15		T148	9		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T18	3		T250	1		T20	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	3		T100	12		T267	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T26	13		T136	16		T170	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T28	5		T46	5		T148	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	2		T53	9		T186	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T28	4		T136	15		T185	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T62	15		T35	1		T17	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13