Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21644

1

T1

12

T3

18

T4

18

auto[ADC_CTRL_FILTER_COND_OUT]

3550

1

T2

15

T5

49

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19221

1

T1

12

T2

15

T3

18

auto[1]

5973

1

T5

27

T6

1

T10

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T268	1		T269	27		-	-
values[0]	131	1			T5	27		T46	10		T147	9
values[1]	693	1			T4	18		T9	5		T53	11
values[2]	782	1			T2	1		T6	14		T9	29
values[3]	667	1			T11	1		T30	1		T136	30
values[4]	652	1			T11	15		T14	7		T55	14
values[5]	2971	1			T29	14		T133	29		T51	36
values[6]	629	1			T6	6		T13	1		T28	11
values[7]	623	1			T2	14		T5	22		T129	1
values[8]	716	1			T12	3		T26	32		T126	1
values[9]	1286	1			T6	1		T28	36		T30	1
minimum	16016	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1013	1			T4	18		T5	27		T6	14
values[1]	751	1			T2	1		T13	3		T52	37
values[2]	700	1			T11	15		T14	7		T30	1
values[3]	2944	1			T11	1		T29	14		T133	29
values[4]	642	1			T6	6		T13	1		T135	15
values[5]	650	1			T30	1		T55	20		T127	13
values[6]	817	1			T2	14		T5	22		T26	32
values[7]	594	1			T12	3		T28	26		T30	1
values[8]	906	1			T6	1		T28	10		T126	1
values[9]	160	1			T164	1		T131	24		T246	2
minimum	16017	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T4	10		T9	12		T10	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T5	13		T6	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T135	1		T32	11		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	1		T13	1		T52	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	1		T14	4		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T136	16		T231	1		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1591	1			T29	1		T133	3		T51	36
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	1		T130	1		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	1		T145	9		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	1		T135	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T137	18		T138	1		T38	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T30	1		T55	9		T127	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T28	6		T129	1		T136	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T5	13		T26	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	2		T28	12		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T126	1		T130	1		T62	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T28	5		T126	1		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T6	1		T136	17		T145	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T164	1		T246	2		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T131	13		T141	1		T255	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T1	12		T3	18		T7	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	8		T9	17		T10	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	14		T6	13		T9	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T135	2		T32	14		T62	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	2		T52	16		T48	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	14		T14	3		T55	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T136	14		T231	11		T101	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T29	13		T133	26		T233	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T255	13		T234	15		T271	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	5		T140	8		T272	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T135	14		T247	1		T170	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T137	10		T38	4		T273	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T55	11		T43	10		T48	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T28	5		T136	10		T62	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	13		T5	9		T26	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	1		T28	14		T185	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T62	13		T186	9		T245	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T28	5		T43	3		T46	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T136	14		T155	11		T48	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T17	1		T274	9		T31	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T131	11		T141	4		T243	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T268	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T269	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T147	9		T235	1		T275	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T5	13		T46	3		T242	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	10		T35	3		T186	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	3		T53	11		T246	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	12		T10	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	1		T6	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T30	1		T32	11		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	1		T136	16		T270	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	1		T14	4		T55	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T101	1		T276	14		T256	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1602	1			T29	1		T133	3		T51	36
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T135	1		T55	9		T130	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	1		T28	6		T145	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T30	1		T127	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T129	1		T36	2		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	1		T5	13		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	2		T136	10		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T26	14		T126	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T28	17		T30	1		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	392	1			T6	1		T136	17		T145	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T269	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T235	6		T275	10		T277	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T5	14		T46	7		T242	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	8		T186	12		T156	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T9	2		T170	5		T17	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T9	17		T10	8		T135	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	13		T13	2		T52	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T32	14		T185	6		T247	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T136	14		T254	10		T278	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	14		T14	3		T55	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T101	14		T276	11		T279	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T29	13		T133	26		T233	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T135	14		T55	11		T247	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T6	5		T28	5		T272	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T43	10		T170	14		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T137	10		T90	1		T273	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	13		T5	9		T48	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	1		T136	10		T62	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T26	18		T245	14		T84	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T28	19		T43	3		T46	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T136	14		T62	13		T155	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T4	9		T9	18		T10	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	15		T6	14		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T135	3		T32	15		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	1		T13	3		T52	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	15		T14	4		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T136	15		T231	12		T101	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T29	14		T133	29		T51	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	1		T130	1		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	6		T145	1		T140	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	1		T135	15		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T137	11		T138	1		T38	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	1		T55	12		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T28	6		T129	1		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	14		T5	10		T26	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	2		T28	15		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T126	1		T130	1		T62	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T28	6		T126	1		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	1		T136	15		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T164	1		T246	1		T17	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T131	12		T141	5		T255	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16017	1			T1	12		T3	18		T7	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	9		T9	11		T35	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	12		T9	2		T53	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T32	10		T62	15		T185	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T52	20		T17	3		T50	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T14	3		T55	2		T127	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T136	15		T270	24		T254	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T51	34		T125	22		T144	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T280	5		T149	7		T234	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T145	8		T281	15		T272	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T247	12		T170	16		T199	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T137	17		T38	3		T248	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T55	8		T127	12		T264	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T28	5		T136	9		T62	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	12		T26	13		T148	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	1		T28	11		T47	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T62	15		T186	10		T245	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T28	4		T127	17		T46	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T136	16		T145	13		T37	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T246	1		T274	4		T151	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T131	12		T243	1		T269	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T268	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T269	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T147	1		T235	7		T275	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T5	15		T46	8		T242	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	9		T35	2		T186	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	3		T53	2		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	18		T10	9		T135	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T2	1		T6	14		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T30	1		T32	15		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	1		T136	15		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T11	15		T14	4		T55	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T101	15		T276	20		T256	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T29	14		T133	29		T51	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T135	15		T55	12		T130	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	6		T28	6		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	1		T30	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T129	1		T36	2		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	14		T5	10		T48	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	2		T136	11		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T26	19		T126	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T28	21		T30	1		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T6	1		T136	15		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T269	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T147	8		T277	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T5	12		T46	2		T242	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	9		T35	1		T186	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	2		T53	9		T246	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	11		T62	15		T232	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T52	20		T148	10		T50	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T32	10		T47	5		T185	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T136	15		T270	24		T254	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	3		T55	2		T127	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T276	5		T282	12		T283	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T51	34		T125	22		T144	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T55	8		T247	12		T280	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T28	5		T145	8		T272	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T127	12		T170	16		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T137	17		T248	4		T266	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	12		T148	14		T90	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	1		T136	9		T62	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T26	13		T245	16		T146	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T28	15		T127	17		T46	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T136	16		T145	13		T62	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13