Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21666

1

T1

12

T2

1

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3528

1

T2

14

T4

18

T5

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19019

1

T1

12

T2

1

T3

18

auto[1]

6175

1

T2

14

T4

18

T5

49

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T237	3		-	-		-	-
values[0]	125	1			T62	29		T155	12		T46	10
values[1]	568	1			T9	34		T10	9		T145	9
values[2]	738	1			T6	14		T13	3		T30	1
values[3]	683	1			T4	18		T135	15		T55	20
values[4]	751	1			T2	14		T12	3		T13	1
values[5]	3078	1			T6	6		T11	1		T14	7
values[6]	472	1			T6	1		T30	1		T126	1
values[7]	621	1			T28	11		T128	1		T130	1
values[8]	823	1			T2	1		T5	27		T11	15
values[9]	1316	1			T5	22		T28	10		T30	1
minimum	16016	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	887	1			T6	14		T9	34		T30	1
values[1]	595	1			T13	3		T52	37		T129	2
values[2]	908	1			T4	18		T13	1		T26	32
values[3]	3022	1			T2	14		T12	3		T14	7
values[4]	594	1			T6	7		T11	1		T30	1
values[5]	569	1			T126	1		T53	1		T130	1
values[6]	664	1			T11	15		T28	11		T136	30
values[7]	818	1			T2	1		T5	27		T28	36
values[8]	853	1			T5	22		T30	1		T127	13
values[9]	225	1			T135	3		T163	1		T274	14
minimum	16059	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	1		T145	9		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T9	15		T30	1		T62	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	1		T52	21		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T129	1		T128	1		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	1		T135	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	10		T26	14		T55	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1623	1			T12	2		T14	4		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	1		T136	17		T148	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T136	10		T32	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	2		T30	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T126	1		T185	6		T148	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T53	1		T130	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	1		T136	16		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T28	6		T47	6		T131	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T2	1		T28	12		T47	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	13		T28	5		T127	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	13		T128	1		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T30	1		T127	13		T222	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T163	1		T274	5		T273	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T135	1		T250	16		T284	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15905	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T141	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	13		T155	11		T46	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	19		T62	13		T131	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T13	2		T52	16		T234	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	9		T17	1		T234	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T135	14		T131	1		T187	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	8		T26	18		T55	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T12	1		T14	3		T29	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	13		T136	14		T247	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T136	10		T32	14		T55	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	5		T48	13		T186	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T185	6		T186	9		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T90	1		T101	14		T273	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	14		T136	14		T62	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T28	5		T131	11		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T28	14		T185	11		T245	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T5	14		T28	5		T255	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T5	9		T43	3		T38	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T222	10		T137	11		T170	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T274	9		T187	8		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T135	2		T284	13		T172	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	8		T12	3		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T141	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T237	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T155	1		T46	3		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T62	16		T253	8		T285	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T10	1		T145	9		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	15		T131	1		T246	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	1		T13	1		T52	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T30	1		T129	1		T127	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T135	1		T140	1		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	10		T55	9		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	2		T13	1		T53	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	1		T26	14		T136	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T11	1		T14	4		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	1		T126	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T126	1		T136	10		T185	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	1		T30	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T128	1		T62	16		T46	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T28	6		T130	1		T47	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T2	1		T11	1		T28	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	13		T127	18		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	401	1			T5	13		T128	1		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T28	5		T30	1		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T237	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T155	11		T46	7		T141	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T62	13		T285	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T10	8		T48	4		T170	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	19		T131	1		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	13		T13	2		T52	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T17	1		T231	7		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T135	14		T187	10		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	8		T55	11		T48	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T62	14		T232	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	13		T26	18		T136	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T14	3		T29	13		T133	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	5		T48	13		T186	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T136	10		T185	6		T258	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T231	11		T140	8		T101	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T62	10		T46	3		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T28	5		T40	1		T90	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	14		T28	14		T136	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	14		T131	11		T100	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	9		T43	3		T185	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T28	5		T135	2		T222	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	14		T145	1		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T9	21		T30	1		T62	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	3		T52	17		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T129	1		T128	1		T48	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T13	1		T135	15		T131	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T4	9		T26	19		T55	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T12	2		T14	4		T29	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	14		T136	15		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	1		T136	11		T32	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	7		T30	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T126	1		T185	7		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T53	1		T130	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	15		T136	15		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T28	6		T47	1		T131	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	1		T28	15		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	15		T28	6		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	10		T128	1		T43	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T30	1		T127	1		T222	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T163	1		T274	10		T273	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T135	3		T250	1		T284	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16036	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T141	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T145	8		T46	2		T146	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	13		T62	15		T246	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T52	20		T35	1		T281	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T250	16		T150	21		T19	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T199	4		T280	5		T157	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	9		T26	13		T55	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T12	1		T14	3		T51	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T136	16		T148	14		T247	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T136	9		T32	10		T55	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T145	13		T186	13		T147	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T185	5		T148	9		T186	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T249	7		T254	15		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T136	15		T62	15		T46	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T28	5		T47	5		T131	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T28	11		T47	6		T185	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	12		T28	4		T127	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	12		T38	3		T223	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T127	12		T222	11		T137	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T274	4		T286	10		T287	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T250	15		T284	13		T288	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T232	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T237	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T155	12		T46	8		T141	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T62	14		T253	1		T285	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T10	9		T145	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	21		T131	2		T246	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	14		T13	3		T52	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T30	1		T129	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T135	15		T140	1		T187	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	9		T55	12		T48	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	2		T13	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	14		T26	19		T136	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1405	1			T11	1		T14	4		T29	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	6		T126	1		T48	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T126	1		T136	11		T185	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	1		T30	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T128	1		T62	11		T46	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T28	6		T130	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	1		T11	15		T28	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	15		T127	1		T131	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T5	10		T128	1		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T28	6		T30	1		T135	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T46	2		T232	9		T289	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T62	15		T253	7		T285	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T145	8		T170	8		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T9	13		T246	20		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T52	20		T35	1		T146	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T127	12		T254	8		T250	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T199	4		T280	5		T290	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	9		T55	8		T49	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	1		T53	9		T62	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	13		T136	16		T148	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T14	3		T51	34		T125	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T186	13		T249	7		T254	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T136	9		T185	5		T148	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T145	13		T147	23		T149	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T62	15		T46	5		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T28	5		T47	5		T170	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T28	11		T136	15		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	12		T127	17		T131	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T5	12		T47	6		T185	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T28	4		T127	12		T222	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13