Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21670

1

T1

12

T2

15

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3524

1

T6

21

T9

34

T10

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18831

1

T1

12

T2

15

T3

18

auto[1]

6363

1

T4

18

T5

27

T6

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T151	3		T291	11		-	-
values[0]	13	1			T273	11		T292	1		T283	1
values[1]	565	1			T6	14		T9	5		T30	1
values[2]	679	1			T5	49		T129	1		T145	14
values[3]	712	1			T2	1		T14	7		T28	10
values[4]	603	1			T2	14		T30	1		T52	37
values[5]	880	1			T28	11		T62	29		T164	1
values[6]	663	1			T6	6		T13	1		T135	15
values[7]	772	1			T4	18		T26	32		T126	1
values[8]	601	1			T6	1		T30	1		T136	31
values[9]	3676	1			T9	29		T10	9		T11	16
minimum	16016	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	698	1			T5	27		T6	14		T9	5
values[1]	700	1			T2	1		T5	22		T126	1
values[2]	733	1			T2	14		T14	7		T28	10
values[3]	588	1			T30	1		T52	37		T48	14
values[4]	858	1			T28	11		T62	29		T164	1
values[5]	813	1			T6	6		T13	1		T26	32
values[6]	2948	1			T4	18		T6	1		T29	14
values[7]	615	1			T11	15		T30	1		T136	31
values[8]	961	1			T9	29		T10	9		T11	1
values[9]	259	1			T145	9		T43	4		T131	2
minimum	16021	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	13		T30	1		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	1		T9	3		T127	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	1		T5	13		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T126	1		T139	1		T267	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	1		T14	4		T55	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T28	5		T53	10		T185	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T30	1		T148	15		T264	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T52	21		T48	1		T37	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T131	1		T17	2		T293	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T28	6		T62	16		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T13	1		T135	1		T222	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	1		T26	14		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1610	1			T4	10		T29	1		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	1		T126	1		T136	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T130	1		T40	3		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	1		T30	1		T136	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T11	1		T12	2		T28	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T9	12		T10	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T145	9		T43	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T249	13		T99	1		T232	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15896	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T5	14		T135	2		T17	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	13		T9	2		T131	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	9		T62	10		T185	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T267	12		T258	17		T294	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	13		T14	3		T55	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T28	5		T185	11		T154	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T264	5		T18	2		T290	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T52	16		T48	13		T37	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T131	1		T17	1		T293	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T28	5		T62	13		T48	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T135	14		T222	10		T43	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	5		T26	18		T48	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T4	8		T29	13		T133	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T136	10		T46	3		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T40	1		T146	10		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	14		T136	14		T32	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	1		T28	14		T55	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T9	17		T10	8		T13	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T43	3		T131	1		T90	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T232	14		T261	11		T295	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	3		T32	4		T43	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T291	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T151	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T273	1		T292	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T30	1		T129	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	1		T9	3		T127	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	26		T129	1		T145	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T130	2		T224	1		T296	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T2	1		T14	4		T55	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T28	5		T126	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	1		T30	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T52	21		T53	10		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T148	15		T247	13		T293	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T28	6		T62	16		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	1		T135	1		T35	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	1		T127	13		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T4	10		T222	12		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T26	14		T126	1		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T130	1		T40	3		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	1		T30	1		T136	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1779	1			T11	1		T12	2		T28	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T9	12		T10	1		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T291	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T273	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T135	2		T101	5		T254	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	13		T9	2		T131	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	23		T17	6		T231	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T224	6		T267	12		T258	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	3		T55	11		T62	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T28	5		T154	2		T254	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	13		T131	1		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T52	16		T48	13		T185	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T247	1		T293	13		T273	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T28	5		T62	13		T37	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T135	14		T232	19		T274	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	5		T48	9		T297	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	8		T222	10		T43	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T26	18		T136	10		T46	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T40	1		T140	8		T255	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T136	14		T32	14		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T12	1		T28	14		T29	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T9	17		T10	8		T11	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	15		T30	1		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T6	14		T9	3		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	1		T5	10		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T126	1		T139	1		T267	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	14		T14	4		T55	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T28	6		T53	1		T185	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T30	1		T148	1		T264	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T52	17		T48	14		T37	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T131	2		T17	2		T293	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T28	6		T62	14		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T13	1		T135	15		T222	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	6		T26	19		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T4	9		T29	14		T133	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	1		T126	1		T136	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T130	1		T40	4		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	15		T30	1		T136	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T11	1		T12	2		T28	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T9	18		T10	9		T13	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T145	1		T43	4		T131	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T249	1		T99	1		T232	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16019	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T5	12		T17	3		T199	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	2		T127	17		T131	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	12		T145	13		T62	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T267	8		T258	18		T266	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	3		T55	2		T62	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T28	4		T53	9		T185	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T148	14		T264	11		T18	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T52	20		T37	6		T254	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T17	1		T293	7		T147	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T28	5		T62	15		T47	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T222	11		T35	1		T247	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T26	13		T127	12		T147	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T4	9		T51	34		T125	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T136	9		T127	12		T46	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T146	9		T276	5		T151	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T136	16		T32	10		T246	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	1		T28	11		T55	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	11		T136	15		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T145	8		T90	20		T100	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T249	12		T232	11		T149	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T298	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T291	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T151	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T273	11		T292	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T30	1		T129	1		T135	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	14		T9	3		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	25		T129	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T130	2		T224	7		T296	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	1		T14	4		T55	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T28	6		T126	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	14		T30	1		T131	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T52	17		T53	1		T48	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T148	1		T247	2		T293	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T28	6		T62	14		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	1		T135	15		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	6		T127	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	9		T222	11		T43	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T26	19		T126	1		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T130	1		T40	4		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	1		T30	1		T136	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1565	1			T11	1		T12	2		T28	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	412	1			T9	18		T10	9		T11	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T291	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T151	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T199	13		T254	8		T19	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T9	2		T127	17		T131	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	24		T145	13		T148	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T267	8		T258	18		T149	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T14	3		T55	2		T62	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T28	4		T254	11		T266	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T39	1		T17	1		T264	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T52	20		T53	9		T185	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T148	14		T247	12		T293	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T28	5		T62	15		T47	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T35	1		T232	20		T274	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T127	12		T284	13		T299	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	9		T222	11		T247	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T26	13		T136	9		T46	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T151	4		T253	11		T300	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T136	16		T32	10		T127	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T12	1		T28	11		T51	34
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T9	11		T136	15		T148	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13