Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21291

1

T1

12

T2

14

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3903

1

T2

1

T5

27

T6

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19273

1

T1

12

T2

1

T3

18

auto[1]

5921

1

T2

14

T9

5

T11

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	41	1			T48	5		T284	27		T20	3
values[0]	13	1			T127	13		-	-		-	-
values[1]	684	1			T9	29		T127	13		T222	22
values[2]	961	1			T6	14		T28	10		T52	37
values[3]	671	1			T5	22		T11	15		T13	4
values[4]	731	1			T4	18		T26	32		T28	26
values[5]	708	1			T2	14		T6	6		T126	1
values[6]	521	1			T2	1		T30	1		T55	20
values[7]	667	1			T5	27		T6	1		T9	5
values[8]	3137	1			T10	9		T11	1		T14	7
values[9]	1044	1			T12	3		T28	11		T30	2
minimum	16016	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	867	1			T9	29		T127	26		T62	29
values[1]	887	1			T6	14		T28	10		T52	37
values[2]	710	1			T11	15		T13	4		T26	32
values[3]	721	1			T4	18		T5	22		T28	26
values[4]	751	1			T2	14		T6	6		T129	1
values[5]	498	1			T2	1		T30	1		T55	20
values[6]	3019	1			T5	27		T9	5		T11	1
values[7]	843	1			T6	1		T10	9		T14	7
values[8]	764	1			T12	3		T28	11		T30	1
values[9]	100	1			T223	14		T226	12		T225	5
minimum	16034	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T9	12		T127	13		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T127	13		T62	16		T222	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	1		T52	21		T136	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T28	5		T155	1		T185	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	1		T53	10		T130	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T13	2		T26	14		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	10		T5	13		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T28	12		T53	1		T32	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	1		T129	1		T145	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	1		T62	12		T35	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T30	1		T55	9		T47	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T137	18		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1611	1			T9	3		T29	1		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	13		T11	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	1		T10	1		T14	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T30	1		T129	1		T55	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T127	18		T36	2		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T12	2		T28	6		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T223	14		T225	5		T301	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T226	12		T302	12		T303	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T229	2		T239	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	17		T16	4		T38	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T62	13		T222	10		T185	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	13		T52	16		T136	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T28	5		T155	11		T185	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	14		T43	10		T46	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	2		T26	18		T46	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	8		T5	9		T135	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T28	14		T32	14		T137	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	13		T43	3		T245	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	5		T62	14		T131	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T55	11		T37	6		T156	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T137	10		T170	5		T101	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T9	2		T29	13		T133	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	14		T135	14		T136	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	8		T14	3		T224	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T55	11		T186	9		T258	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T170	13		T232	5		T187	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	1		T28	5		T48	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T236	2		T237	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T302	10		T243	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T229	1		T239	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T284	14		T301	1		T304	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T48	1		T20	2		T226	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T127	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	12		T16	6		T38	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T127	13		T222	12		T185	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	1		T52	21		T136	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T28	5		T62	16		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	13		T11	1		T53	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	2		T130	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	10		T129	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T26	14		T28	12		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	1		T126	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	1		T35	3		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T30	1		T55	9		T47	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	1		T62	12		T137	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	1		T9	3		T62	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	13		T135	1		T136	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1633	1			T10	1		T14	4		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	1		T126	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T127	18		T36	2		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T12	2		T28	6		T30	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T284	13		T304	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T48	4		T20	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T9	17		T16	4		T38	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T222	10		T185	17		T154	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	13		T52	16		T136	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T28	5		T62	13		T293	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T5	9		T11	14		T43	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	2		T155	11		T46	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T4	8		T186	12		T231	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T26	18		T28	14		T32	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	13		T135	2		T43	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	5		T131	1		T140	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T55	11		T245	14		T156	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T62	14		T137	10		T170	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	2		T62	10		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	14		T135	14		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T10	8		T14	3		T29	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T55	11		T186	9		T305	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T170	13		T141	4		T232	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	1		T28	5		T90	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	18		T127	1		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T127	1		T62	14		T222	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	14		T52	17		T136	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T28	6		T155	12		T185	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	15		T53	1		T130	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T13	4		T26	19		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	9		T5	10		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T28	15		T53	1		T32	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	14		T129	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	6		T62	15		T35	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T30	1		T55	12		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	1		T137	11		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T9	3		T29	14		T133	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	15		T11	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T10	9		T14	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T30	1		T129	1		T55	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T127	1		T36	2		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	2		T28	6		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T223	1		T225	1		T301	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T226	1		T302	11		T303	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16017	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T229	2		T239	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	11		T127	12		T148	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T127	12		T62	15		T222	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T52	20		T136	16		T246	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T28	4		T185	5		T232	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T53	9		T46	5		T265	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T26	13		T46	2		T148	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	9		T5	12		T47	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T28	11		T32	10		T157	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T145	13		T246	5		T245	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T62	11		T35	1		T147	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T55	8		T47	5		T37	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T137	17		T170	8		T248	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T9	2		T51	34		T136	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	12		T136	9		T131	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	3		T146	9		T249	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T55	2		T186	10		T49	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T127	17		T170	2		T232	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	1		T28	5		T145	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T223	13		T225	4		T236	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T226	11		T302	11		T303	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T229	1		T239	5		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T284	14		T301	1		T304	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T48	5		T20	2		T226	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T127	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	18		T16	6		T38	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T127	1		T222	11		T185	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T6	14		T52	17		T136	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T28	6		T62	14		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	10		T11	15		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	4		T130	1		T155	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	9		T129	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T26	19		T28	15		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	14		T126	1		T135	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	6		T35	2		T131	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T30	1		T55	12		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T62	15		T137	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	1		T9	3		T62	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	15		T135	15		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T10	9		T14	4		T29	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T11	1		T126	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T127	1		T36	2		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T12	2		T28	6		T30	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T284	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T20	1		T226	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T127	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	11		T16	4		T38	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T127	12		T222	11		T185	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T52	20		T136	16		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T28	4		T62	15		T293	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	12		T53	9		T46	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T46	2		T148	9		T264	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	9		T186	13		T199	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T26	13		T28	11		T32	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T145	13		T247	21		T146	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T35	1		T147	8		T254	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T55	8		T47	5		T246	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T62	11		T137	17		T170	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T9	2		T62	15		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	12		T136	9		T131	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T14	3		T51	34		T136	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T55	2		T148	14		T186	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T127	17		T170	2		T232	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T12	1		T28	5		T145	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13