Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21633

1

T1

12

T2

15

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3561

1

T4

18

T6

21

T9

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18771

1

T1

12

T2

15

T3

18

auto[1]

6423

1

T5

27

T6

14

T9

34

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	336	1			T10	9		T12	3		T43	4
values[0]	12	1			T288	12		-	-		-	-
values[1]	523	1			T6	14		T9	5		T30	1
values[2]	727	1			T5	49		T129	1		T145	14
values[3]	691	1			T2	15		T14	7		T28	10
values[4]	664	1			T30	1		T52	37		T53	10
values[5]	820	1			T28	11		T62	29		T164	1
values[6]	820	1			T6	6		T13	1		T26	32
values[7]	637	1			T4	18		T6	1		T126	1
values[8]	581	1			T30	1		T136	31		T32	25
values[9]	3367	1			T9	29		T11	16		T13	3
minimum	16016	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	552	1			T5	27		T6	14		T9	5
values[1]	755	1			T2	1		T5	22		T126	1
values[2]	680	1			T2	14		T14	7		T28	10
values[3]	587	1			T30	1		T52	37		T48	14
values[4]	875	1			T28	11		T62	29		T163	1
values[5]	863	1			T6	6		T13	1		T26	32
values[6]	2898	1			T4	18		T6	1		T29	14
values[7]	666	1			T11	15		T30	1		T136	31
values[8]	957	1			T9	29		T10	9		T11	1
values[9]	211	1			T55	20		T145	9		T43	4
minimum	16150	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T5	13		T130	1		T17	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	1		T9	3		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T2	1		T5	13		T129	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T126	1		T139	1		T267	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	1		T55	3		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	4		T28	5		T53	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T30	1		T131	1		T264	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T52	21		T48	1		T37	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T148	15		T17	2		T293	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T28	6		T62	16		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	1		T135	1		T222	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	1		T26	14		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T29	1		T133	3		T51	36
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	10		T6	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T130	1		T40	3		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	1		T30	1		T136	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T11	1		T12	2		T28	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T9	12		T10	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T55	9		T145	9		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T249	13		T100	13		T232	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15925	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T127	18		T84	1		T288	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T5	14		T17	6		T101	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	13		T9	2		T131	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	9		T62	10		T231	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T267	12		T258	17		T294	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	13		T55	11		T62	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	3		T28	5		T185	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T131	1		T264	5		T18	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T52	16		T48	13		T37	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T17	1		T293	13		T273	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T28	5		T62	13		T186	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T135	14		T222	10		T247	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	5		T26	18		T43	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T29	13		T133	26		T233	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	8		T136	10		T46	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T40	1		T146	10		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	14		T136	14		T32	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	1		T28	14		T186	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	17		T10	8		T13	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T55	11		T43	3		T131	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T100	14		T232	14		T295	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	3		T135	2		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T84	11		T306	8		T173	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	2		T43	1		T131	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T10	1		T249	13		T232	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T288	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T30	1		T129	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	1		T9	3		T127	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	26		T129	1		T145	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T130	1		T224	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T2	2		T55	3		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	4		T28	5		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	1		T131	1		T264	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T52	21		T53	10		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T148	15		T17	2		T293	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T28	6		T62	16		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	1		T135	1		T35	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	1		T26	14		T127	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T222	12		T247	10		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	10		T6	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T130	1		T40	3		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	1		T136	17		T32	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1675	1			T11	1		T28	12		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T9	12		T11	1		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T12	1		T43	3		T131	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T10	8		T232	14		T187	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T135	2		T101	5		T273	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	13		T9	2		T131	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	23		T17	6		T231	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T224	6		T267	12		T258	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	13		T55	11		T62	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T14	3		T28	5		T254	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T131	1		T264	5		T18	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T52	16		T48	13		T185	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T17	1		T293	13		T273	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T28	5		T62	13		T37	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T135	14		T247	1		T170	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	5		T26	18		T48	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T222	10		T247	2		T231	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T4	8		T136	10		T43	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T40	1		T146	10		T140	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T136	14		T32	14		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T28	14		T29	13		T133	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T9	17		T11	14		T13	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T5	15		T130	1		T17	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	14		T9	3		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	1		T5	10		T129	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T126	1		T139	1		T267	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	14		T55	12		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	4		T28	6		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T30	1		T131	2		T264	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T52	17		T48	14		T37	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T148	1		T17	2		T293	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T28	6		T62	14		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T13	1		T135	15		T222	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	6		T26	19		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T29	14		T133	29		T51	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	9		T6	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T130	1		T40	4		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	15		T30	1		T136	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T11	1		T12	2		T28	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T9	18		T10	9		T13	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T55	12		T145	1		T43	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T249	1		T100	15		T232	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T127	1		T84	12		T288	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T5	12		T17	3		T199	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T9	2		T131	12		T199	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	12		T145	13		T62	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T267	8		T258	18		T294	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T55	2		T62	11		T46	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	3		T28	4		T53	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T264	11		T18	3		T253	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T52	20		T37	6		T254	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T148	14		T17	1		T293	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T28	5		T62	15		T47	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T222	11		T35	1		T247	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T26	13		T127	12		T137	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T51	34		T125	22		T144	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	9		T136	9		T127	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T146	9		T276	5		T151	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T136	16		T32	10		T246	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	1		T28	11		T186	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	11		T136	15		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T55	8		T145	8		T90	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T249	12		T100	12		T232	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T254	8		T282	2		T298	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T127	17		T288	11		T173	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	2		T43	4		T131	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T10	9		T249	1		T232	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T288	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T30	1		T129	1		T135	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	14		T9	3		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	25		T129	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T130	1		T224	7		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	15		T55	12		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	4		T28	6		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T30	1		T131	2		T264	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T52	17		T53	1		T48	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T148	1		T17	2		T293	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T28	6		T62	14		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T13	1		T135	15		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	6		T26	19		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T222	11		T247	3		T231	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	9		T6	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T130	1		T40	4		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T30	1		T136	15		T32	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T11	1		T28	15		T29	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T9	18		T11	15		T13	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T12	1		T246	1		T49	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T249	12		T232	11		T149	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T288	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T199	13		T254	8		T19	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T9	2		T127	17		T131	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	24		T145	13		T148	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T267	8		T258	18		T149	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T55	2		T62	26		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T14	3		T28	4		T254	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T264	11		T18	3		T253	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T52	20		T53	9		T185	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T148	14		T17	1		T293	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T28	5		T62	15		T47	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T35	1		T247	12		T170	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T26	13		T127	12		T147	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T222	11		T247	9		T50	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	9		T136	9		T46	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T146	9		T151	4		T300	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T136	16		T32	10		T127	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T28	11		T51	34		T125	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T9	11		T136	15		T148	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13