Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21756

1

T1

12

T2

1

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3438

1

T2

14

T4

18

T5

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18887

1

T1

12

T3

18

T4

18

auto[1]

6307

1

T2

15

T5

49

T6

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T231	12		T301	1		T307	1
values[0]	49	1			T43	11		T308	8		T242	29
values[1]	693	1			T5	22		T28	11		T32	25
values[2]	647	1			T6	6		T30	1		T126	1
values[3]	663	1			T5	27		T9	29		T11	15
values[4]	2959	1			T12	3		T29	14		T133	29
values[5]	589	1			T6	1		T30	1		T130	1
values[6]	685	1			T26	32		T28	10		T126	1
values[7]	635	1			T2	14		T6	14		T14	7
values[8]	673	1			T2	1		T13	3		T53	10
values[9]	1566	1			T4	18		T9	5		T10	9
minimum	16016	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	846	1			T5	22		T28	11		T32	25
values[1]	683	1			T5	27		T6	6		T9	29
values[2]	696	1			T11	15		T13	1		T126	1
values[3]	2980	1			T12	3		T29	14		T133	29
values[4]	531	1			T6	1		T130	1		T155	12
values[5]	610	1			T26	32		T28	36		T30	1
values[6]	671	1			T2	14		T6	14		T14	7
values[7]	811	1			T2	1		T13	3		T53	10
values[8]	1050	1			T4	18		T9	5		T10	9
values[9]	282	1			T136	30		T127	13		T139	1
minimum	16034	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T28	6		T32	11		T43	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	13		T62	12		T37	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	13		T6	1		T9	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T128	1		T132	1		T137	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	1		T13	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T129	1		T136	10		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T29	1		T133	3		T51	36
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T12	2		T43	1		T309	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T130	1		T155	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	1		T137	1		T84	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T28	17		T30	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T26	14		T126	1		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T245	17		T249	13		T17	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	1		T6	1		T14	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T2	1		T13	1		T53	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T145	23		T186	14		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T11	1		T136	17		T62	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T4	10		T9	3		T10	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T136	16		T127	13		T253	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T139	1		T231	1		T274	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T310	18		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T28	5		T32	14		T43	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	9		T62	14		T37	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	14		T6	5		T9	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T137	10		T224	6		T207	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	14		T185	6		T232	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T136	10		T186	9		T38	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T29	13		T133	26		T233	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	1		T43	3		T247	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T155	11		T293	13		T258	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T137	1		T84	11		T297	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T28	19		T135	2		T55	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T26	18		T135	14		T131	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T245	14		T17	1		T140	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	13		T6	13		T14	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	2		T62	10		T46	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T186	12		T34	11		T230	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T136	14		T62	13		T222	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	8		T9	2		T10	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T136	14		T311	8		T105	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T231	11		T274	9		T312	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T301	1		T307	1		T313	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T231	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T43	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T308	1		T242	12		T314	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T28	6		T32	11		T148	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	13		T62	12		T137	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	1		T30	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T128	1		T132	1		T148	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	13		T9	12		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T128	1		T228	1		T186	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T29	1		T133	3		T51	36
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	2		T129	1		T136	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T30	1		T130	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	1		T43	1		T309	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T28	5		T55	3		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T26	14		T126	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T28	12		T135	1		T50	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	1		T6	1		T14	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	1		T13	1		T53	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T55	9		T138	1		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	500	1			T11	1		T136	33		T127	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	420	1			T4	10		T9	3		T10	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T313	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T231	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T43	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T308	7		T242	17		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T28	5		T32	14		T90	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	9		T62	14		T137	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	5		T101	14		T232	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T224	6		T100	14		T273	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	14		T9	17		T11	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T186	9		T38	4		T207	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T29	13		T133	26		T233	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	1		T136	10		T247	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T154	2		T17	1		T293	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T43	3		T84	11		T231	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T28	5		T55	11		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T26	18		T135	14		T131	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T28	14		T135	2		T50	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	13		T6	13		T14	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	2		T46	7		T48	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T55	11		T34	11		T255	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T136	28		T62	23		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T4	8		T9	2		T10	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T28	6		T32	15		T43	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T5	10		T62	15		T37	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	15		T6	6		T9	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T128	1		T132	1		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	15		T13	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T129	1		T136	11		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T29	14		T133	29		T51	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	2		T43	4		T309	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T130	1		T155	12		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	1		T137	2		T84	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T28	21		T30	1		T135	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T26	19		T126	1		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T245	15		T249	1		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	14		T6	14		T14	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	1		T13	3		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T145	2		T186	13		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T11	1		T136	15		T62	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T4	9		T9	3		T10	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T136	15		T127	1		T253	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T139	1		T231	12		T274	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T310	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T28	5		T32	10		T148	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	12		T62	11		T37	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	12		T9	11		T52	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T137	17		T148	10		T246	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T127	17		T185	5		T232	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T136	9		T186	10		T38	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T51	34		T125	22		T144	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	1		T247	12		T157	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T293	7		T258	11		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T150	21		T284	13		T213	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T28	15		T55	2		T281	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T26	13		T16	4		T294	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T245	16		T249	12		T50	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	3		T55	8		T46	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T53	9		T62	15		T46	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T145	21		T186	13		T230	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T136	16		T62	15		T222	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	9		T9	2		T185	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T136	15		T127	12		T253	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T274	4		T149	10		T312	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T310	17		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T301	1		T307	1		T313	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T231	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T43	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T308	8		T242	18		T314	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T28	6		T32	15		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	10		T62	15		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	6		T30	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T128	1		T132	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	15		T9	18		T11	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T128	1		T228	1		T186	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T29	14		T133	29		T51	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	2		T129	1		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T30	1		T130	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T43	4		T309	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T28	6		T55	12		T155	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T26	19		T126	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T28	15		T135	3		T50	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	14		T6	14		T14	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	1		T13	3		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T55	12		T138	1		T34	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	426	1			T11	1		T136	30		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T4	9		T9	3		T10	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T242	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T28	5		T32	10		T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	12		T62	11		T137	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T127	12		T232	11		T18	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T148	10		T100	12		T147	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	12		T9	11		T52	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T186	10		T246	15		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T51	34		T125	22		T144	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T136	9		T247	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T47	5		T246	5		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T157	9		T284	13		T213	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T28	4		T55	2		T249	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T26	13		T16	4		T294	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T28	11		T50	1		T232	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	3		T46	5		T131	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T53	9		T46	2		T245	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T55	8		T255	8		T230	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	416	1			T136	31		T127	12		T62	30
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T4	9		T9	2		T145	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13