Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25194

1

T1

12

T2

15

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21523

1

T1

12

T3

18

T4

18

auto[ADC_CTRL_FILTER_COND_OUT]

3671

1

T2

15

T5

27

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18986

1

T1

12

T3

18

T4

18

auto[1]

6208

1

T2

15

T5

49

T6

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21230

1

T1

12

T2

2

T3

18

auto[1]

3964

1

T2

13

T4

8

T5

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	66	1			T146	20		T140	1		T274	14
values[0]	34	1			T218	5		T259	20		T315	1
values[1]	617	1			T126	1		T53	11		T128	1
values[2]	2933	1			T4	18		T29	14		T133	29
values[3]	591	1			T2	1		T6	1		T127	13
values[4]	671	1			T6	14		T28	11		T30	1
values[5]	488	1			T2	14		T11	16		T28	26
values[6]	939	1			T5	27		T6	6		T136	61
values[7]	824	1			T5	22		T13	3		T135	15
values[8]	893	1			T9	5		T26	32		T30	1
values[9]	1122	1			T9	29		T10	9		T12	3
minimum	16016	1			T1	12		T3	18		T7	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	774	1			T126	1		T53	11		T128	1
values[1]	2912	1			T4	18		T6	1		T29	14
values[2]	678	1			T2	1		T30	1		T127	13
values[3]	566	1			T2	14		T6	14		T11	15
values[4]	606	1			T6	6		T11	1		T28	26
values[5]	943	1			T5	27		T129	1		T136	61
values[6]	679	1			T5	22		T13	3		T135	15
values[7]	1031	1			T9	34		T26	32		T30	1
values[8]	714	1			T10	9		T12	3		T13	1
values[9]	255	1			T136	20		T32	25		T83	1
minimum	16036	1			T1	12		T3	18		T7	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

4279

1

T4

9

T5

24

T9

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T128	1		T43	1		T47	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T126	1		T53	11		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1545	1			T4	10		T29	1		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	1		T135	1		T35	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T127	13		T163	1		T185	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	1		T30	1		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T28	6		T46	3		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	1		T6	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	1		T11	1		T55	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T28	12		T30	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T136	16		T145	23		T131	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	13		T129	1		T136	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	13		T13	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T164	1		T148	10		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T9	3		T26	14		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	12		T30	1		T127	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	1		T12	2		T28	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	1		T14	4		T52	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T83	1		T231	1		T292	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T136	10		T32	11		T274	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T259	20		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T43	10		T100	14		T293	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T62	10		T245	14		T231	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T4	8		T29	13		T133	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T135	2		T186	9		T90	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T185	6		T170	13		T258	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T40	1		T84	11		T101	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T28	5		T46	7		T48	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	13		T6	13		T11	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	5		T55	11		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T28	14		T48	4		T170	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T136	14		T131	11		T247	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	14		T136	14		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	9		T13	2		T135	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T154	2		T224	6		T231	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T9	2		T26	18		T137	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	17		T62	14		T131	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	8		T12	1		T28	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	3		T52	16		T62	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T231	11		T316	9		T302	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T136	10		T32	14		T274	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T317	2		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T146	10		T140	1		T274	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T315	1		T227	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T218	2		T259	20		T177	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T128	1		T43	1		T246	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T126	1		T53	11		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T4	10		T29	1		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T135	1		T90	21		T17	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T127	13		T163	1		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	1		T6	1		T35	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T28	6		T46	3		T185	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T30	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T11	1		T55	9		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	1		T11	1		T28	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T6	1		T136	16		T145	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	13		T136	17		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T5	13		T13	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T164	1		T148	25		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T9	3		T26	14		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T30	1		T131	1		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T10	1		T12	2		T28	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T9	12		T13	1		T14	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15893	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T146	10		T274	9		T318	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T218	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T43	10		T241	4		T308	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T62	10		T245	14		T231	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T4	8		T29	13		T133	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T135	2		T90	19		T17	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T48	9		T170	13		T293	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T186	9		T84	11		T101	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T28	5		T46	7		T185	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T6	13		T40	1		T141	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T55	11		T293	1		T273	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	13		T11	14		T28	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T6	5		T136	14		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	14		T136	14		T48	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	9		T13	2		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T154	2		T17	1		T231	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T9	2		T26	18		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T131	1		T224	6		T50	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	8		T12	1		T28	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T9	17		T14	3		T52	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	3		T32	4		T43	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T128	1		T43	11		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T126	1		T53	2		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T4	9		T29	14		T133	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	1		T135	3		T35	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T127	1		T163	1		T185	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T2	1		T30	1		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T28	6		T46	8		T48	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	14		T6	14		T11	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	6		T11	1		T55	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T28	15		T30	1		T48	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T136	15		T145	2		T131	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	15		T129	1		T136	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	10		T13	3		T135	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T164	1		T148	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T9	3		T26	19		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T9	18		T30	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	9		T12	2		T28	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	1		T14	4		T52	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T83	1		T231	12		T292	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T136	11		T32	15		T274	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T259	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T47	6		T100	12		T284	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T53	9		T62	15		T245	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T4	9		T51	34		T125	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T35	1		T186	10		T90	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T127	12		T185	5		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T254	15		T230	13		T250	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T28	5		T46	2		T186	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T185	10		T246	15		T199	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T55	8		T222	11		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T28	11		T170	8		T18	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T136	15		T145	21		T131	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	12		T136	16		T148	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	12		T37	6		T146	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T148	9		T49	1		T147	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T9	2		T26	13		T16	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	11		T127	12		T62	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	1		T28	4		T127	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	3		T52	20		T62	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T316	11		T302	17		T319	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T136	9		T32	10		T274	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T259	19		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T317	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T146	11		T140	1		T274	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T315	1		T227	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T218	4		T259	1		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T128	1		T43	11		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T126	1		T53	2		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T4	9		T29	14		T133	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T135	3		T90	20		T17	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T127	1		T163	1		T48	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	1		T6	1		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T28	6		T46	8		T185	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T6	14		T30	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	1		T55	12		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	14		T11	15		T28	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T6	6		T136	15		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	15		T136	15		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	10		T13	3		T135	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T164	1		T148	2		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T9	3		T26	19		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T30	1		T131	2		T224	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T10	9		T12	2		T28	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T9	18		T13	1		T14	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16016	1			T1	12		T3	18		T7	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T317	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T146	9		T274	4		T318	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T218	1		T259	19		T177	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T246	1		T284	13		T31	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T53	9		T62	15		T245	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T4	9		T51	34		T125	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T90	20		T17	3		T149	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T127	12		T148	10		T246	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T35	1		T186	10		T254	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T28	5		T46	2		T185	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T199	4		T230	13		T223	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T55	8		T265	1		T320	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T28	11		T185	10		T246	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T136	15		T145	13		T222	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	12		T136	16		T170	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	12		T145	8		T37	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T148	23		T49	1		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T9	2		T26	13		T16	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T50	1		T149	10		T226	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	1		T28	4		T127	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T9	11		T14	3		T52	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20915

1

T1

12

T2

15

T3

18

auto[1]

auto[0]

4279

1

T4

9

T5

24

T9

13