Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.14


Total test records in report: 919
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T792 /workspace/coverage/default/21.adc_ctrl_alert_test.3184338629 Jun 29 06:42:45 PM PDT 24 Jun 29 06:42:48 PM PDT 24 318483795 ps
T793 /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.970120686 Jun 29 06:43:28 PM PDT 24 Jun 29 06:49:31 PM PDT 24 326500142124 ps
T794 /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3745510643 Jun 29 06:43:19 PM PDT 24 Jun 29 06:50:11 PM PDT 24 166979715184 ps
T795 /workspace/coverage/default/42.adc_ctrl_filters_both.3830627386 Jun 29 06:43:58 PM PDT 24 Jun 29 07:04:35 PM PDT 24 508277562625 ps
T796 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1935674518 Jun 29 06:41:47 PM PDT 24 Jun 29 06:41:49 PM PDT 24 417097479 ps
T59 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2772999960 Jun 29 06:41:29 PM PDT 24 Jun 29 06:41:54 PM PDT 24 28460833165 ps
T797 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2644340902 Jun 29 06:41:41 PM PDT 24 Jun 29 06:41:43 PM PDT 24 350105544 ps
T798 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3564705290 Jun 29 06:41:51 PM PDT 24 Jun 29 06:41:53 PM PDT 24 287132474 ps
T63 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2373145557 Jun 29 06:41:33 PM PDT 24 Jun 29 06:41:38 PM PDT 24 4592238645 ps
T66 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1676976363 Jun 29 06:41:32 PM PDT 24 Jun 29 06:41:36 PM PDT 24 466431430 ps
T108 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.964572360 Jun 29 06:41:34 PM PDT 24 Jun 29 06:41:36 PM PDT 24 570976402 ps
T91 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3327270375 Jun 29 06:41:30 PM PDT 24 Jun 29 06:41:31 PM PDT 24 573184346 ps
T67 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2070952370 Jun 29 06:41:37 PM PDT 24 Jun 29 06:41:39 PM PDT 24 710616860 ps
T71 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.399202520 Jun 29 06:41:56 PM PDT 24 Jun 29 06:42:00 PM PDT 24 446157779 ps
T104 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2841251672 Jun 29 06:41:35 PM PDT 24 Jun 29 06:41:36 PM PDT 24 485376065 ps
T799 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2950995926 Jun 29 06:41:44 PM PDT 24 Jun 29 06:41:46 PM PDT 24 300285772 ps
T60 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.74143910 Jun 29 06:41:54 PM PDT 24 Jun 29 06:41:58 PM PDT 24 2309790681 ps
T74 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1503376761 Jun 29 06:41:40 PM PDT 24 Jun 29 06:41:43 PM PDT 24 573739912 ps
T61 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2222245951 Jun 29 06:41:29 PM PDT 24 Jun 29 06:41:32 PM PDT 24 2273221247 ps
T800 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.212414283 Jun 29 06:41:54 PM PDT 24 Jun 29 06:41:58 PM PDT 24 393773325 ps
T109 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2324676224 Jun 29 06:41:34 PM PDT 24 Jun 29 06:41:37 PM PDT 24 701164250 ps
T124 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3425077793 Jun 29 06:41:31 PM PDT 24 Jun 29 06:41:33 PM PDT 24 523398904 ps
T92 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2998423423 Jun 29 06:41:43 PM PDT 24 Jun 29 06:41:46 PM PDT 24 317371030 ps
T64 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2765135545 Jun 29 06:41:42 PM PDT 24 Jun 29 06:41:46 PM PDT 24 4226299506 ps
T72 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2922563939 Jun 29 06:41:50 PM PDT 24 Jun 29 06:41:53 PM PDT 24 1011206140 ps
T93 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3457474863 Jun 29 06:41:11 PM PDT 24 Jun 29 06:41:14 PM PDT 24 543345843 ps
T65 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.21762959 Jun 29 06:41:53 PM PDT 24 Jun 29 06:42:06 PM PDT 24 7724416345 ps
T78 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2357565135 Jun 29 06:41:12 PM PDT 24 Jun 29 06:41:15 PM PDT 24 406514765 ps
T79 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1534405893 Jun 29 06:41:26 PM PDT 24 Jun 29 06:41:38 PM PDT 24 4082902543 ps
T73 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1377840127 Jun 29 06:41:43 PM PDT 24 Jun 29 06:41:47 PM PDT 24 552364090 ps
T801 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.774647253 Jun 29 06:41:53 PM PDT 24 Jun 29 06:41:56 PM PDT 24 291516014 ps
T802 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1408190207 Jun 29 06:41:48 PM PDT 24 Jun 29 06:41:50 PM PDT 24 303757785 ps
T803 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1548133483 Jun 29 06:41:54 PM PDT 24 Jun 29 06:41:58 PM PDT 24 471169869 ps
T119 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2813095978 Jun 29 06:41:09 PM PDT 24 Jun 29 06:41:10 PM PDT 24 491135352 ps
T804 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.24680319 Jun 29 06:41:10 PM PDT 24 Jun 29 06:41:12 PM PDT 24 394997485 ps
T805 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1049949330 Jun 29 06:41:30 PM PDT 24 Jun 29 06:41:31 PM PDT 24 346558747 ps
T806 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1025939390 Jun 29 06:41:47 PM PDT 24 Jun 29 06:41:50 PM PDT 24 597749370 ps
T807 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2158059141 Jun 29 06:41:46 PM PDT 24 Jun 29 06:41:48 PM PDT 24 374506298 ps
T110 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4017627162 Jun 29 06:41:37 PM PDT 24 Jun 29 06:41:39 PM PDT 24 365827842 ps
T808 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4051493644 Jun 29 06:41:41 PM PDT 24 Jun 29 06:41:42 PM PDT 24 554959454 ps
T120 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.63280218 Jun 29 06:41:42 PM PDT 24 Jun 29 06:41:46 PM PDT 24 3942318855 ps
T121 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2432320703 Jun 29 06:41:51 PM PDT 24 Jun 29 06:42:06 PM PDT 24 4033133371 ps
T111 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.862282557 Jun 29 06:41:10 PM PDT 24 Jun 29 06:41:11 PM PDT 24 560059178 ps
T112 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1609443954 Jun 29 06:41:09 PM PDT 24 Jun 29 06:41:11 PM PDT 24 530277035 ps
T809 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2169223425 Jun 29 06:41:30 PM PDT 24 Jun 29 06:41:32 PM PDT 24 528558246 ps
T122 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3801289331 Jun 29 06:42:12 PM PDT 24 Jun 29 06:42:15 PM PDT 24 4529322444 ps
T347 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1887167776 Jun 29 06:41:58 PM PDT 24 Jun 29 06:42:10 PM PDT 24 4359064684 ps
T123 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2833598216 Jun 29 06:41:58 PM PDT 24 Jun 29 06:42:01 PM PDT 24 432822482 ps
T810 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1670500534 Jun 29 06:41:40 PM PDT 24 Jun 29 06:41:42 PM PDT 24 485902514 ps
T811 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3532573916 Jun 29 06:41:46 PM PDT 24 Jun 29 06:41:48 PM PDT 24 497131466 ps
T113 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4194019018 Jun 29 06:41:11 PM PDT 24 Jun 29 06:41:13 PM PDT 24 536452063 ps
T812 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.381065407 Jun 29 06:41:45 PM PDT 24 Jun 29 06:41:47 PM PDT 24 363789128 ps
T813 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1194636999 Jun 29 06:41:51 PM PDT 24 Jun 29 06:41:54 PM PDT 24 481232147 ps
T814 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.701300570 Jun 29 06:41:44 PM PDT 24 Jun 29 06:41:46 PM PDT 24 509885865 ps
T815 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.560840967 Jun 29 06:41:31 PM PDT 24 Jun 29 06:41:33 PM PDT 24 517139650 ps
T816 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1304934719 Jun 29 06:41:46 PM PDT 24 Jun 29 06:41:48 PM PDT 24 386801098 ps
T817 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4074637207 Jun 29 06:41:47 PM PDT 24 Jun 29 06:41:50 PM PDT 24 362330195 ps
T818 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2628439514 Jun 29 06:41:52 PM PDT 24 Jun 29 06:42:03 PM PDT 24 2660757792 ps
T819 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2654887454 Jun 29 06:41:10 PM PDT 24 Jun 29 06:41:13 PM PDT 24 567091662 ps
T820 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.843125271 Jun 29 06:41:43 PM PDT 24 Jun 29 06:41:45 PM PDT 24 358973776 ps
T821 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.933454800 Jun 29 06:41:44 PM PDT 24 Jun 29 06:41:49 PM PDT 24 4697776255 ps
T349 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3672160957 Jun 29 06:41:10 PM PDT 24 Jun 29 06:41:16 PM PDT 24 4548670260 ps
T822 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1868312350 Jun 29 06:41:38 PM PDT 24 Jun 29 06:41:42 PM PDT 24 2570688584 ps
T114 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3138694662 Jun 29 06:41:11 PM PDT 24 Jun 29 06:41:14 PM PDT 24 494676415 ps
T823 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1863059922 Jun 29 06:41:55 PM PDT 24 Jun 29 06:41:58 PM PDT 24 472433445 ps
T824 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2266349321 Jun 29 06:41:47 PM PDT 24 Jun 29 06:41:49 PM PDT 24 400487297 ps
T825 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.830326657 Jun 29 06:41:43 PM PDT 24 Jun 29 06:41:45 PM PDT 24 393860673 ps
T826 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1644473226 Jun 29 06:41:42 PM PDT 24 Jun 29 06:41:43 PM PDT 24 546837052 ps
T827 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1776925975 Jun 29 06:41:29 PM PDT 24 Jun 29 06:41:31 PM PDT 24 472443264 ps
T115 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4042754454 Jun 29 06:41:29 PM PDT 24 Jun 29 06:43:15 PM PDT 24 52984742514 ps
T348 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2987324495 Jun 29 06:41:36 PM PDT 24 Jun 29 06:41:49 PM PDT 24 8900094893 ps
T828 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2180257837 Jun 29 06:41:09 PM PDT 24 Jun 29 06:41:12 PM PDT 24 1943784954 ps
T829 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2852319121 Jun 29 06:41:47 PM PDT 24 Jun 29 06:41:49 PM PDT 24 529101182 ps
T116 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.132590979 Jun 29 06:41:40 PM PDT 24 Jun 29 06:41:44 PM PDT 24 842557830 ps
T830 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3138854472 Jun 29 06:41:35 PM PDT 24 Jun 29 06:41:45 PM PDT 24 4470192900 ps
T831 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1124554476 Jun 29 06:41:40 PM PDT 24 Jun 29 06:41:44 PM PDT 24 9365356659 ps
T832 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2751867455 Jun 29 06:41:44 PM PDT 24 Jun 29 06:41:46 PM PDT 24 421110918 ps
T80 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2236120205 Jun 29 06:41:11 PM PDT 24 Jun 29 06:41:31 PM PDT 24 8329365447 ps
T117 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1594845528 Jun 29 06:41:28 PM PDT 24 Jun 29 06:41:33 PM PDT 24 1535413344 ps
T118 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.362947902 Jun 29 06:41:35 PM PDT 24 Jun 29 06:41:43 PM PDT 24 2806851161 ps
T833 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3562722637 Jun 29 06:41:09 PM PDT 24 Jun 29 06:41:11 PM PDT 24 473956579 ps
T834 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3554452428 Jun 29 06:41:36 PM PDT 24 Jun 29 06:41:38 PM PDT 24 1033324446 ps
T350 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3113925864 Jun 29 06:41:46 PM PDT 24 Jun 29 06:41:53 PM PDT 24 8846519280 ps
T835 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1132388554 Jun 29 06:41:43 PM PDT 24 Jun 29 06:41:45 PM PDT 24 434394175 ps
T836 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4270971670 Jun 29 06:41:10 PM PDT 24 Jun 29 06:41:11 PM PDT 24 652893830 ps
T837 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.410826017 Jun 29 06:41:39 PM PDT 24 Jun 29 06:41:41 PM PDT 24 594818952 ps
T838 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.170000647 Jun 29 06:41:49 PM PDT 24 Jun 29 06:41:51 PM PDT 24 402493821 ps
T839 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.669192892 Jun 29 06:41:42 PM PDT 24 Jun 29 06:41:54 PM PDT 24 7986394675 ps
T840 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2161676734 Jun 29 06:41:37 PM PDT 24 Jun 29 06:41:39 PM PDT 24 389454970 ps
T841 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2998778028 Jun 29 06:41:30 PM PDT 24 Jun 29 06:41:31 PM PDT 24 493602610 ps
T842 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1912865379 Jun 29 06:41:54 PM PDT 24 Jun 29 06:41:58 PM PDT 24 447875901 ps
T843 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.190344124 Jun 29 06:41:38 PM PDT 24 Jun 29 06:41:40 PM PDT 24 375454105 ps
T844 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3959176259 Jun 29 06:41:39 PM PDT 24 Jun 29 06:41:40 PM PDT 24 534956416 ps
T845 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3457102570 Jun 29 06:41:54 PM PDT 24 Jun 29 06:41:58 PM PDT 24 426757284 ps
T846 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3740297214 Jun 29 06:41:32 PM PDT 24 Jun 29 06:41:35 PM PDT 24 477230728 ps
T847 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1432981028 Jun 29 06:41:55 PM PDT 24 Jun 29 06:41:58 PM PDT 24 456612270 ps
T848 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3782479255 Jun 29 06:41:46 PM PDT 24 Jun 29 06:41:48 PM PDT 24 339475716 ps
T849 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1602413116 Jun 29 06:41:38 PM PDT 24 Jun 29 06:41:43 PM PDT 24 8370830226 ps
T351 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2005290693 Jun 29 06:41:20 PM PDT 24 Jun 29 06:41:33 PM PDT 24 8726509514 ps
T850 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4160563517 Jun 29 06:41:45 PM PDT 24 Jun 29 06:41:48 PM PDT 24 574932066 ps
T851 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3350666597 Jun 29 06:41:11 PM PDT 24 Jun 29 06:41:13 PM PDT 24 582499033 ps
T852 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.4176851725 Jun 29 06:41:35 PM PDT 24 Jun 29 06:41:39 PM PDT 24 422547681 ps
T853 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1634318229 Jun 29 06:41:45 PM PDT 24 Jun 29 06:41:48 PM PDT 24 2951149710 ps
T854 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.660228903 Jun 29 06:41:51 PM PDT 24 Jun 29 06:41:55 PM PDT 24 590581085 ps
T855 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2622309637 Jun 29 06:41:39 PM PDT 24 Jun 29 06:41:59 PM PDT 24 5127297592 ps
T856 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.691310894 Jun 29 06:41:40 PM PDT 24 Jun 29 06:41:43 PM PDT 24 2815237824 ps
T857 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3216832360 Jun 29 06:41:47 PM PDT 24 Jun 29 06:41:49 PM PDT 24 447930706 ps
T858 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1924593123 Jun 29 06:41:46 PM PDT 24 Jun 29 06:41:50 PM PDT 24 8232342939 ps
T859 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4006120100 Jun 29 06:41:42 PM PDT 24 Jun 29 06:41:44 PM PDT 24 621907362 ps
T860 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3209210842 Jun 29 06:41:32 PM PDT 24 Jun 29 06:41:36 PM PDT 24 5098749839 ps
T861 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2529637146 Jun 29 06:41:38 PM PDT 24 Jun 29 06:41:40 PM PDT 24 389915779 ps
T862 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3394303768 Jun 29 06:42:12 PM PDT 24 Jun 29 06:42:13 PM PDT 24 333203315 ps
T863 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3904859455 Jun 29 06:42:02 PM PDT 24 Jun 29 06:42:04 PM PDT 24 384729478 ps
T864 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2868136240 Jun 29 06:41:11 PM PDT 24 Jun 29 06:41:17 PM PDT 24 1033778586 ps
T865 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3460568757 Jun 29 06:41:15 PM PDT 24 Jun 29 06:41:16 PM PDT 24 789511630 ps
T866 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3762387788 Jun 29 06:41:53 PM PDT 24 Jun 29 06:41:56 PM PDT 24 485268419 ps
T867 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3384794000 Jun 29 06:41:28 PM PDT 24 Jun 29 06:41:30 PM PDT 24 4177954355 ps
T868 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3303801913 Jun 29 06:41:34 PM PDT 24 Jun 29 06:41:36 PM PDT 24 462570925 ps
T869 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2703642303 Jun 29 06:41:13 PM PDT 24 Jun 29 06:41:33 PM PDT 24 8130341542 ps
T870 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3211619869 Jun 29 06:41:49 PM PDT 24 Jun 29 06:41:51 PM PDT 24 518877945 ps
T871 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4125481564 Jun 29 06:41:35 PM PDT 24 Jun 29 06:41:37 PM PDT 24 805992685 ps
T872 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2596275607 Jun 29 06:41:34 PM PDT 24 Jun 29 06:41:36 PM PDT 24 2134847683 ps
T873 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2590790925 Jun 29 06:41:56 PM PDT 24 Jun 29 06:42:00 PM PDT 24 557345608 ps
T874 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2432619160 Jun 29 06:41:45 PM PDT 24 Jun 29 06:41:47 PM PDT 24 520197087 ps
T875 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2343873981 Jun 29 06:41:44 PM PDT 24 Jun 29 06:41:46 PM PDT 24 405069966 ps
T876 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1849465606 Jun 29 06:41:57 PM PDT 24 Jun 29 06:42:00 PM PDT 24 493122994 ps
T877 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1694713232 Jun 29 06:41:33 PM PDT 24 Jun 29 06:41:35 PM PDT 24 427860197 ps
T878 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1807039981 Jun 29 06:41:32 PM PDT 24 Jun 29 06:41:37 PM PDT 24 1024313280 ps
T879 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3239231262 Jun 29 06:41:39 PM PDT 24 Jun 29 06:41:41 PM PDT 24 454728093 ps
T880 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.187964616 Jun 29 06:41:10 PM PDT 24 Jun 29 06:41:14 PM PDT 24 529612159 ps
T881 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4132042026 Jun 29 06:41:30 PM PDT 24 Jun 29 06:41:32 PM PDT 24 497238858 ps
T882 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3929277054 Jun 29 06:41:45 PM PDT 24 Jun 29 06:41:47 PM PDT 24 364507375 ps
T883 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.604718829 Jun 29 06:41:18 PM PDT 24 Jun 29 06:41:31 PM PDT 24 8289249745 ps
T884 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.875795843 Jun 29 06:41:51 PM PDT 24 Jun 29 06:41:53 PM PDT 24 558595272 ps
T885 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.18090218 Jun 29 06:41:42 PM PDT 24 Jun 29 06:41:44 PM PDT 24 493362030 ps
T886 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3016141906 Jun 29 06:41:40 PM PDT 24 Jun 29 06:41:43 PM PDT 24 2331803987 ps
T887 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3685090927 Jun 29 06:41:51 PM PDT 24 Jun 29 06:42:03 PM PDT 24 7841592892 ps
T888 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1680064904 Jun 29 06:41:45 PM PDT 24 Jun 29 06:41:52 PM PDT 24 8254526824 ps
T889 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.425271110 Jun 29 06:41:52 PM PDT 24 Jun 29 06:41:55 PM PDT 24 295892356 ps
T890 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1718607208 Jun 29 06:41:34 PM PDT 24 Jun 29 06:41:37 PM PDT 24 4422495522 ps
T891 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1503056154 Jun 29 06:41:49 PM PDT 24 Jun 29 06:41:51 PM PDT 24 332578629 ps
T892 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.208024608 Jun 29 06:41:54 PM PDT 24 Jun 29 06:41:58 PM PDT 24 394688661 ps
T893 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3285709258 Jun 29 06:41:22 PM PDT 24 Jun 29 06:41:24 PM PDT 24 474992490 ps
T894 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.623790071 Jun 29 06:41:40 PM PDT 24 Jun 29 06:41:42 PM PDT 24 424934566 ps
T895 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.472193690 Jun 29 06:41:58 PM PDT 24 Jun 29 06:42:00 PM PDT 24 368761011 ps
T896 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3555843664 Jun 29 06:41:46 PM PDT 24 Jun 29 06:41:47 PM PDT 24 580133937 ps
T897 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3421976211 Jun 29 06:42:03 PM PDT 24 Jun 29 06:42:05 PM PDT 24 461562653 ps
T898 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2991481513 Jun 29 06:41:11 PM PDT 24 Jun 29 06:41:15 PM PDT 24 633724863 ps
T899 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2991754220 Jun 29 06:41:45 PM PDT 24 Jun 29 06:41:47 PM PDT 24 463776602 ps
T900 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1436815642 Jun 29 06:41:52 PM PDT 24 Jun 29 06:41:59 PM PDT 24 4719355532 ps
T901 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.678130557 Jun 29 06:41:35 PM PDT 24 Jun 29 06:41:37 PM PDT 24 464960051 ps
T902 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3529026623 Jun 29 06:41:31 PM PDT 24 Jun 29 06:41:33 PM PDT 24 433240594 ps
T903 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.737923437 Jun 29 06:41:47 PM PDT 24 Jun 29 06:41:49 PM PDT 24 336251738 ps
T904 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1246568346 Jun 29 06:41:37 PM PDT 24 Jun 29 06:41:39 PM PDT 24 413400268 ps
T905 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3792981341 Jun 29 06:41:09 PM PDT 24 Jun 29 06:41:11 PM PDT 24 599839369 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2122702814 Jun 29 06:41:21 PM PDT 24 Jun 29 06:41:22 PM PDT 24 387710380 ps
T907 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2528354820 Jun 29 06:41:46 PM PDT 24 Jun 29 06:41:51 PM PDT 24 4392329799 ps
T908 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1224019343 Jun 29 06:41:39 PM PDT 24 Jun 29 06:41:43 PM PDT 24 556566507 ps
T909 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4216880351 Jun 29 06:41:42 PM PDT 24 Jun 29 06:41:48 PM PDT 24 4371955581 ps
T910 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3714600939 Jun 29 06:41:15 PM PDT 24 Jun 29 06:41:18 PM PDT 24 2723515137 ps
T911 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2007382943 Jun 29 06:41:48 PM PDT 24 Jun 29 06:41:50 PM PDT 24 435037313 ps
T912 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.861363627 Jun 29 06:41:53 PM PDT 24 Jun 29 06:41:57 PM PDT 24 545088083 ps
T913 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3906598842 Jun 29 06:42:04 PM PDT 24 Jun 29 06:42:06 PM PDT 24 391241705 ps
T914 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3091970830 Jun 29 06:41:37 PM PDT 24 Jun 29 06:41:40 PM PDT 24 553241617 ps
T915 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1172051153 Jun 29 06:41:35 PM PDT 24 Jun 29 06:41:37 PM PDT 24 333730068 ps
T916 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3729803908 Jun 29 06:41:55 PM PDT 24 Jun 29 06:42:01 PM PDT 24 497122753 ps
T917 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.695819427 Jun 29 06:41:47 PM PDT 24 Jun 29 06:41:49 PM PDT 24 462634142 ps
T918 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2457302747 Jun 29 06:41:13 PM PDT 24 Jun 29 06:43:08 PM PDT 24 52605936794 ps
T919 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.977806419 Jun 29 06:41:12 PM PDT 24 Jun 29 06:41:14 PM PDT 24 664631189 ps

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4016830126
Short name T9
Test name
Test status
Simulation time 378335763329 ps
CPU time 724.52 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:53:56 PM PDT 24
Peak memory 201864 kb
Host smart-25f8cd1b-dfce-4516-b282-e432d663286f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016830126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4016830126
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.846753250
Short name T28
Test name
Test status
Simulation time 538773988671 ps
CPU time 350.21 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:47:49 PM PDT 24
Peak memory 201868 kb
Host smart-a56a655c-7d8f-4595-9d14-b88d54af6cd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846753250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.846753250
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3821136124
Short name T55
Test name
Test status
Simulation time 455664947125 ps
CPU time 552.84 seconds
Started Jun 29 06:42:39 PM PDT 24
Finished Jun 29 06:51:53 PM PDT 24
Peak memory 210376 kb
Host smart-cd3f03dc-a4bd-4ed7-a42d-c197df7cbbd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821136124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3821136124
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3318329293
Short name T17
Test name
Test status
Simulation time 244415358036 ps
CPU time 256.84 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:46:08 PM PDT 24
Peak memory 210508 kb
Host smart-58a7012d-6969-4f47-8beb-2180b3e9f773
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318329293 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3318329293
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3561223080
Short name T43
Test name
Test status
Simulation time 579635079321 ps
CPU time 918.45 seconds
Started Jun 29 06:42:40 PM PDT 24
Finished Jun 29 06:58:00 PM PDT 24
Peak memory 202176 kb
Host smart-5b2d1854-b7f8-4d9d-82e0-a3582ff8cce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561223080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3561223080
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1911735631
Short name T136
Test name
Test status
Simulation time 502230159151 ps
CPU time 1065.58 seconds
Started Jun 29 06:42:36 PM PDT 24
Finished Jun 29 07:00:22 PM PDT 24
Peak memory 201888 kb
Host smart-5f10e750-67dc-4804-94a9-6b258fea2791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911735631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1911735631
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3294170474
Short name T62
Test name
Test status
Simulation time 544918985986 ps
CPU time 164.93 seconds
Started Jun 29 06:43:19 PM PDT 24
Finished Jun 29 06:46:05 PM PDT 24
Peak memory 201860 kb
Host smart-0b3da410-4c80-4376-b15f-3a73d8f068e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294170474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3294170474
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3572453349
Short name T35
Test name
Test status
Simulation time 36981856106 ps
CPU time 23.1 seconds
Started Jun 29 06:42:29 PM PDT 24
Finished Jun 29 06:42:53 PM PDT 24
Peak memory 218412 kb
Host smart-563a2f31-6a70-4e5c-9f74-f56b2babebee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572453349 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3572453349
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2358940131
Short name T170
Test name
Test status
Simulation time 531603029183 ps
CPU time 318.99 seconds
Started Jun 29 06:41:52 PM PDT 24
Finished Jun 29 06:47:12 PM PDT 24
Peak memory 201836 kb
Host smart-c1116b3b-94e4-40c4-8b22-9def43fcf12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358940131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2358940131
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1481990425
Short name T68
Test name
Test status
Simulation time 7711892278 ps
CPU time 9.59 seconds
Started Jun 29 06:42:03 PM PDT 24
Finished Jun 29 06:42:13 PM PDT 24
Peak memory 218268 kb
Host smart-e3b49c17-02f5-44a1-8f48-a7f0720be668
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481990425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1481990425
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2301863048
Short name T147
Test name
Test status
Simulation time 616292600148 ps
CPU time 1411.5 seconds
Started Jun 29 06:44:43 PM PDT 24
Finished Jun 29 07:08:15 PM PDT 24
Peak memory 201848 kb
Host smart-93047174-4fad-414b-832f-b51e2339731d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301863048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2301863048
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1676976363
Short name T66
Test name
Test status
Simulation time 466431430 ps
CPU time 3.81 seconds
Started Jun 29 06:41:32 PM PDT 24
Finished Jun 29 06:41:36 PM PDT 24
Peak memory 209984 kb
Host smart-317be5f6-193e-4f20-9838-efd82777b6c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676976363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1676976363
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2517034335
Short name T151
Test name
Test status
Simulation time 531208359042 ps
CPU time 357.17 seconds
Started Jun 29 06:42:29 PM PDT 24
Finished Jun 29 06:48:27 PM PDT 24
Peak memory 201840 kb
Host smart-f13dc5bc-3923-417f-8a1f-1c8057f7bb90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517034335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2517034335
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1004283022
Short name T131
Test name
Test status
Simulation time 538376473871 ps
CPU time 124.82 seconds
Started Jun 29 06:42:40 PM PDT 24
Finished Jun 29 06:44:46 PM PDT 24
Peak memory 201940 kb
Host smart-48bfb055-27b5-4c9c-ad43-4b3d71f45257
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004283022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1004283022
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4017627162
Short name T110
Test name
Test status
Simulation time 365827842 ps
CPU time 1.7 seconds
Started Jun 29 06:41:37 PM PDT 24
Finished Jun 29 06:41:39 PM PDT 24
Peak memory 201516 kb
Host smart-ff969720-d473-4abf-9cce-fa734a8d4f48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017627162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.4017627162
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.187164555
Short name T5
Test name
Test status
Simulation time 325053172941 ps
CPU time 683.51 seconds
Started Jun 29 06:42:10 PM PDT 24
Finished Jun 29 06:53:34 PM PDT 24
Peak memory 201856 kb
Host smart-137e18dc-e0e3-4b14-a516-1895756f0840
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187164555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.187164555
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3355141100
Short name T234
Test name
Test status
Simulation time 560005161716 ps
CPU time 559.73 seconds
Started Jun 29 06:45:08 PM PDT 24
Finished Jun 29 06:54:28 PM PDT 24
Peak memory 201888 kb
Host smart-73e2621f-da0d-479e-b42f-169eca9bba5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355141100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3355141100
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2396262008
Short name T51
Test name
Test status
Simulation time 411195606458 ps
CPU time 194.91 seconds
Started Jun 29 06:43:35 PM PDT 24
Finished Jun 29 06:46:50 PM PDT 24
Peak memory 201836 kb
Host smart-0d9c4bfd-a8a1-4627-bddf-b5bdf8105d85
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396262008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2396262008
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.105809899
Short name T341
Test name
Test status
Simulation time 510470167725 ps
CPU time 1056.02 seconds
Started Jun 29 06:42:39 PM PDT 24
Finished Jun 29 07:00:16 PM PDT 24
Peak memory 201888 kb
Host smart-0ab4339d-8689-4e1c-9f97-bd9968392c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105809899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.105809899
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3655860379
Short name T186
Test name
Test status
Simulation time 387240204672 ps
CPU time 224.75 seconds
Started Jun 29 06:42:21 PM PDT 24
Finished Jun 29 06:46:06 PM PDT 24
Peak memory 201888 kb
Host smart-4ef4700a-2c64-457e-9700-54993c18f3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655860379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3655860379
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2125088053
Short name T284
Test name
Test status
Simulation time 380653126279 ps
CPU time 464.82 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:49:40 PM PDT 24
Peak memory 201900 kb
Host smart-9efc42b1-f800-4cca-b957-68b196ba2453
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125088053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2125088053
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.4038756540
Short name T232
Test name
Test status
Simulation time 594604572995 ps
CPU time 1319.61 seconds
Started Jun 29 06:42:28 PM PDT 24
Finished Jun 29 07:04:28 PM PDT 24
Peak memory 201952 kb
Host smart-82b0dc86-dfee-4112-9c62-d0546aaa5ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038756540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.4038756540
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1952335396
Short name T218
Test name
Test status
Simulation time 301098049132 ps
CPU time 411.81 seconds
Started Jun 29 06:43:20 PM PDT 24
Finished Jun 29 06:50:12 PM PDT 24
Peak memory 218088 kb
Host smart-6cd46182-f43f-424e-9871-4fe011fbcada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952335396 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1952335396
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2464810413
Short name T6
Test name
Test status
Simulation time 502415710940 ps
CPU time 1192.2 seconds
Started Jun 29 06:41:44 PM PDT 24
Finished Jun 29 07:01:37 PM PDT 24
Peak memory 201940 kb
Host smart-69e02489-24a1-4432-8a9d-713dd051889c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464810413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2464810413
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3369316179
Short name T101
Test name
Test status
Simulation time 492901281386 ps
CPU time 1100.85 seconds
Started Jun 29 06:42:29 PM PDT 24
Finished Jun 29 07:00:51 PM PDT 24
Peak memory 201884 kb
Host smart-559eaab1-dae6-4ab4-921c-c0c8a0be1ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369316179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3369316179
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3228806722
Short name T231
Test name
Test status
Simulation time 481704062805 ps
CPU time 965.25 seconds
Started Jun 29 06:42:23 PM PDT 24
Finished Jun 29 06:58:29 PM PDT 24
Peak memory 201944 kb
Host smart-0d5ca4dc-456b-49b7-a228-0798be7df0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228806722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3228806722
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3577271327
Short name T290
Test name
Test status
Simulation time 553003066216 ps
CPU time 591.42 seconds
Started Jun 29 06:43:54 PM PDT 24
Finished Jun 29 06:53:46 PM PDT 24
Peak memory 201848 kb
Host smart-7d05e9a3-ba1d-48a2-bcc5-e7238e584ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577271327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3577271327
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1270597448
Short name T90
Test name
Test status
Simulation time 352765771341 ps
CPU time 101.94 seconds
Started Jun 29 06:42:26 PM PDT 24
Finished Jun 29 06:44:08 PM PDT 24
Peak memory 201868 kb
Host smart-1ef99c53-5dda-4329-a912-4452e1fb3953
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270597448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1270597448
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1251641499
Short name T274
Test name
Test status
Simulation time 164627641565 ps
CPU time 25.8 seconds
Started Jun 29 06:42:15 PM PDT 24
Finished Jun 29 06:42:41 PM PDT 24
Peak memory 201892 kb
Host smart-921b614f-d28c-4924-9aaf-0c12ac5a3ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251641499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1251641499
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3820747455
Short name T142
Test name
Test status
Simulation time 350583867 ps
CPU time 1.03 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:42:01 PM PDT 24
Peak memory 201636 kb
Host smart-62d2361c-3275-443c-9849-2904ec0523d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820747455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3820747455
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1118234796
Short name T127
Test name
Test status
Simulation time 548316430955 ps
CPU time 1229.84 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 07:03:19 PM PDT 24
Peak memory 201924 kb
Host smart-82097a82-39c5-4f86-90dc-f057ba28d88a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118234796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1118234796
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2236120205
Short name T80
Test name
Test status
Simulation time 8329365447 ps
CPU time 19.45 seconds
Started Jun 29 06:41:11 PM PDT 24
Finished Jun 29 06:41:31 PM PDT 24
Peak memory 201816 kb
Host smart-5ffe8b4a-8c26-4732-acd6-0ac710305eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236120205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2236120205
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.549696413
Short name T229
Test name
Test status
Simulation time 76145033393 ps
CPU time 71.38 seconds
Started Jun 29 06:41:49 PM PDT 24
Finished Jun 29 06:43:01 PM PDT 24
Peak memory 210164 kb
Host smart-640b31cc-2f7a-494d-9d8e-d2fccbbe429c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549696413 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.549696413
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.934169031
Short name T257
Test name
Test status
Simulation time 446799928558 ps
CPU time 775.71 seconds
Started Jun 29 06:42:29 PM PDT 24
Finished Jun 29 06:55:25 PM PDT 24
Peak memory 201868 kb
Host smart-752a0ab8-4c6c-482b-8734-0595adb1d018
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934169031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.934169031
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.4150510965
Short name T329
Test name
Test status
Simulation time 343269678549 ps
CPU time 767.52 seconds
Started Jun 29 06:42:33 PM PDT 24
Finished Jun 29 06:55:21 PM PDT 24
Peak memory 201900 kb
Host smart-92e668bf-2fce-4d81-b286-9b7e505e6fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150510965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.4150510965
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2427792868
Short name T259
Test name
Test status
Simulation time 502952779683 ps
CPU time 484.04 seconds
Started Jun 29 06:42:34 PM PDT 24
Finished Jun 29 06:50:39 PM PDT 24
Peak memory 201868 kb
Host smart-dc3c2c0f-4e58-4850-a0f5-2a3160ca1271
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427792868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2427792868
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1974879297
Short name T14
Test name
Test status
Simulation time 162817242722 ps
CPU time 343.66 seconds
Started Jun 29 06:42:24 PM PDT 24
Finished Jun 29 06:48:08 PM PDT 24
Peak memory 201868 kb
Host smart-6cb33d7e-b72b-4085-9bcb-40e1c6c1d17c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974879297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1974879297
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2842027610
Short name T200
Test name
Test status
Simulation time 473106067273 ps
CPU time 512.49 seconds
Started Jun 29 06:44:17 PM PDT 24
Finished Jun 29 06:52:50 PM PDT 24
Peak memory 201872 kb
Host smart-a893219b-1bdc-428a-90f6-23ddb89e2285
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842027610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2842027610
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1670720530
Short name T283
Test name
Test status
Simulation time 925049190027 ps
CPU time 132.59 seconds
Started Jun 29 06:42:40 PM PDT 24
Finished Jun 29 06:44:54 PM PDT 24
Peak memory 210500 kb
Host smart-b0ee212b-62fb-4474-9b09-663d7f1b3940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670720530 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1670720530
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1521437313
Short name T20
Test name
Test status
Simulation time 45347481841 ps
CPU time 73.12 seconds
Started Jun 29 06:44:29 PM PDT 24
Finished Jun 29 06:45:43 PM PDT 24
Peak memory 210480 kb
Host smart-b6a1b7cc-4e71-4eb3-888a-7ab212854a9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521437313 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1521437313
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3817883503
Short name T8
Test name
Test status
Simulation time 111334193106 ps
CPU time 627.77 seconds
Started Jun 29 06:42:26 PM PDT 24
Finished Jun 29 06:52:54 PM PDT 24
Peak memory 202236 kb
Host smart-3d001512-3f57-4381-9d90-422d164bd81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817883503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3817883503
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2709931580
Short name T222
Test name
Test status
Simulation time 182163291383 ps
CPU time 113.07 seconds
Started Jun 29 06:42:22 PM PDT 24
Finished Jun 29 06:44:16 PM PDT 24
Peak memory 201860 kb
Host smart-c50a9d95-a2c4-4240-b82a-5c5149aa7476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709931580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2709931580
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.217282310
Short name T182
Test name
Test status
Simulation time 167965494541 ps
CPU time 218.15 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:45:36 PM PDT 24
Peak memory 201880 kb
Host smart-694b5245-7434-40c4-ace0-30c2a1548d84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=217282310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.217282310
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3177780246
Short name T302
Test name
Test status
Simulation time 563046082398 ps
CPU time 114.75 seconds
Started Jun 29 06:42:29 PM PDT 24
Finished Jun 29 06:44:24 PM PDT 24
Peak memory 201964 kb
Host smart-a036af7b-3ced-4479-99d7-c2b2e994e98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177780246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3177780246
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1493249386
Short name T326
Test name
Test status
Simulation time 408905498691 ps
CPU time 844.07 seconds
Started Jun 29 06:43:54 PM PDT 24
Finished Jun 29 06:57:59 PM PDT 24
Peak memory 202092 kb
Host smart-dfba4d22-9aaf-478d-9827-f40752c8add4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493249386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1493249386
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1343657186
Short name T173
Test name
Test status
Simulation time 423589529838 ps
CPU time 250.46 seconds
Started Jun 29 06:42:27 PM PDT 24
Finished Jun 29 06:46:38 PM PDT 24
Peak memory 201864 kb
Host smart-0c78e29c-db3c-4a92-b418-1ae9173b18e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343657186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1343657186
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3737708980
Short name T321
Test name
Test status
Simulation time 332140090159 ps
CPU time 112.13 seconds
Started Jun 29 06:43:13 PM PDT 24
Finished Jun 29 06:45:05 PM PDT 24
Peak memory 201896 kb
Host smart-b5b06f7c-1589-4772-a594-77f785cdf31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737708980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3737708980
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2873983346
Short name T237
Test name
Test status
Simulation time 326593264141 ps
CPU time 761.07 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:54:40 PM PDT 24
Peak memory 201852 kb
Host smart-63ab91be-56e3-42d8-84b8-3244e7e1eddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873983346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2873983346
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2461610664
Short name T252
Test name
Test status
Simulation time 489878290400 ps
CPU time 403.22 seconds
Started Jun 29 06:42:08 PM PDT 24
Finished Jun 29 06:48:52 PM PDT 24
Peak memory 210564 kb
Host smart-b89d3291-9a8d-4f8e-ac98-7dab7691d0e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461610664 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2461610664
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.4266406479
Short name T269
Test name
Test status
Simulation time 386657060545 ps
CPU time 880.01 seconds
Started Jun 29 06:42:46 PM PDT 24
Finished Jun 29 06:57:27 PM PDT 24
Peak memory 201884 kb
Host smart-06a93e9a-5173-4d43-9c6f-90fa62bcc2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266406479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.4266406479
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.8195583
Short name T242
Test name
Test status
Simulation time 365353041150 ps
CPU time 249.97 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:46:09 PM PDT 24
Peak memory 201836 kb
Host smart-d1c5bf91-db28-4566-8512-b86e27143555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8195583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.8195583
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.410076164
Short name T254
Test name
Test status
Simulation time 527850601528 ps
CPU time 511.12 seconds
Started Jun 29 06:42:38 PM PDT 24
Finished Jun 29 06:51:10 PM PDT 24
Peak memory 201876 kb
Host smart-a148f626-fb6a-457a-a1ec-7dcb60586b97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410076164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.410076164
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.4132469971
Short name T315
Test name
Test status
Simulation time 158019333673 ps
CPU time 354.26 seconds
Started Jun 29 06:42:35 PM PDT 24
Finished Jun 29 06:48:30 PM PDT 24
Peak memory 201892 kb
Host smart-844e43f9-da4b-4dde-b506-ff9fd606ebf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132469971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.4132469971
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1076904637
Short name T288
Test name
Test status
Simulation time 543658680724 ps
CPU time 1208.2 seconds
Started Jun 29 06:42:38 PM PDT 24
Finished Jun 29 07:02:47 PM PDT 24
Peak memory 201920 kb
Host smart-da5e01cf-9901-4768-bcf4-7d0a83dea75d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076904637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1076904637
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1786142310
Short name T291
Test name
Test status
Simulation time 92339263819 ps
CPU time 53.38 seconds
Started Jun 29 06:42:49 PM PDT 24
Finished Jun 29 06:43:43 PM PDT 24
Peak memory 210184 kb
Host smart-ce65e197-8042-46be-8457-2fe0882d9c8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786142310 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1786142310
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.575601665
Short name T214
Test name
Test status
Simulation time 113680561611 ps
CPU time 666.37 seconds
Started Jun 29 06:42:07 PM PDT 24
Finished Jun 29 06:53:14 PM PDT 24
Peak memory 202188 kb
Host smart-277e4f2d-3588-4e94-b1f3-c902edf9f321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575601665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.575601665
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4042754454
Short name T115
Test name
Test status
Simulation time 52984742514 ps
CPU time 105.02 seconds
Started Jun 29 06:41:29 PM PDT 24
Finished Jun 29 06:43:15 PM PDT 24
Peak memory 201856 kb
Host smart-702840d7-5737-4121-99a1-cc085e4f6dfa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042754454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4042754454
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1377840127
Short name T73
Test name
Test status
Simulation time 552364090 ps
CPU time 3.27 seconds
Started Jun 29 06:41:43 PM PDT 24
Finished Jun 29 06:41:47 PM PDT 24
Peak memory 217924 kb
Host smart-0b5f5459-663c-41a4-acf2-b72df4cce850
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377840127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1377840127
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1915547403
Short name T301
Test name
Test status
Simulation time 234065453931 ps
CPU time 142.65 seconds
Started Jun 29 06:42:08 PM PDT 24
Finished Jun 29 06:44:31 PM PDT 24
Peak memory 213704 kb
Host smart-63ef45e8-d0b2-4216-9290-5f0f7b3a2567
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915547403 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1915547403
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.511563550
Short name T317
Test name
Test status
Simulation time 287477863341 ps
CPU time 669.56 seconds
Started Jun 29 06:42:24 PM PDT 24
Finished Jun 29 06:53:34 PM PDT 24
Peak memory 201880 kb
Host smart-68c94326-ab70-4159-bb96-13d56f0bec8d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511563550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.511563550
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2459585729
Short name T273
Test name
Test status
Simulation time 498282409494 ps
CPU time 285.45 seconds
Started Jun 29 06:42:31 PM PDT 24
Finished Jun 29 06:47:17 PM PDT 24
Peak memory 202128 kb
Host smart-e721a802-8f16-4d71-a518-b8a2f9d5557c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459585729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2459585729
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1437796516
Short name T310
Test name
Test status
Simulation time 349440321182 ps
CPU time 74.17 seconds
Started Jun 29 06:43:27 PM PDT 24
Finished Jun 29 06:44:42 PM PDT 24
Peak memory 201892 kb
Host smart-307985d9-a690-4703-a82b-8096ff5d32df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437796516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1437796516
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.4042890195
Short name T202
Test name
Test status
Simulation time 121528720437 ps
CPU time 460.07 seconds
Started Jun 29 06:44:41 PM PDT 24
Finished Jun 29 06:52:21 PM PDT 24
Peak memory 202184 kb
Host smart-bf0250ad-e2c8-4211-b2de-72ab9c67bffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042890195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.4042890195
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.887665968
Short name T141
Test name
Test status
Simulation time 326491462108 ps
CPU time 363.85 seconds
Started Jun 29 06:41:59 PM PDT 24
Finished Jun 29 06:48:04 PM PDT 24
Peak memory 201872 kb
Host smart-372e9df2-994a-47e1-89ee-50cefaf9fc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887665968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.887665968
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.4281097129
Short name T235
Test name
Test status
Simulation time 493522407424 ps
CPU time 518.54 seconds
Started Jun 29 06:42:16 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 201844 kb
Host smart-c37d6ea4-ac6f-4257-8b23-6e9f6637df2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281097129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.4281097129
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.890748076
Short name T337
Test name
Test status
Simulation time 519944209133 ps
CPU time 1197.02 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 07:01:54 PM PDT 24
Peak memory 201956 kb
Host smart-d4defc20-27a4-44d0-8f1b-d35aab794ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890748076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.890748076
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.771617413
Short name T176
Test name
Test status
Simulation time 487676368429 ps
CPU time 296.58 seconds
Started Jun 29 06:42:51 PM PDT 24
Finished Jun 29 06:47:48 PM PDT 24
Peak memory 201876 kb
Host smart-5ee8ddbe-91c6-4ae0-910e-2ce112d81232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771617413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.771617413
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4082360899
Short name T268
Test name
Test status
Simulation time 490210793997 ps
CPU time 574.64 seconds
Started Jun 29 06:44:01 PM PDT 24
Finished Jun 29 06:53:36 PM PDT 24
Peak memory 201964 kb
Host smart-46e62d7a-9c9a-4a30-80c8-6fc160618639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082360899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4082360899
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2987324495
Short name T348
Test name
Test status
Simulation time 8900094893 ps
CPU time 12.94 seconds
Started Jun 29 06:41:36 PM PDT 24
Finished Jun 29 06:41:49 PM PDT 24
Peak memory 201868 kb
Host smart-601f1e58-258b-45c3-8f81-0484b38a4bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987324495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2987324495
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3574065553
Short name T333
Test name
Test status
Simulation time 543089805166 ps
CPU time 601.88 seconds
Started Jun 29 06:42:01 PM PDT 24
Finished Jun 29 06:52:03 PM PDT 24
Peak memory 201936 kb
Host smart-ab9a5f70-b6f7-4d9a-b7b5-20322bc5720c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574065553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3574065553
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1943936368
Short name T582
Test name
Test status
Simulation time 511502192644 ps
CPU time 1158.55 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 07:01:18 PM PDT 24
Peak memory 201876 kb
Host smart-b9318f88-7d37-4418-8a2b-bebad084cdb0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943936368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1943936368
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1686336845
Short name T215
Test name
Test status
Simulation time 460218757020 ps
CPU time 1150.08 seconds
Started Jun 29 06:42:02 PM PDT 24
Finished Jun 29 07:01:12 PM PDT 24
Peak memory 202176 kb
Host smart-179abed6-7b01-4c6f-b66d-27b46639bed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686336845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1686336845
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1119017746
Short name T332
Test name
Test status
Simulation time 497210560849 ps
CPU time 499.93 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:50:45 PM PDT 24
Peak memory 201844 kb
Host smart-24c7590f-d51b-478b-993d-eb7349297bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119017746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1119017746
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3087511760
Short name T261
Test name
Test status
Simulation time 325527366033 ps
CPU time 405.84 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:49:12 PM PDT 24
Peak memory 201884 kb
Host smart-c33e958c-bce5-4d20-b118-6dda8c82884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087511760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3087511760
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2135710095
Short name T150
Test name
Test status
Simulation time 566046947444 ps
CPU time 1258.47 seconds
Started Jun 29 06:42:28 PM PDT 24
Finished Jun 29 07:03:28 PM PDT 24
Peak memory 201864 kb
Host smart-2b5eef27-9f7a-4d6b-86c1-c3efdc90678f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135710095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2135710095
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2571775479
Short name T308
Test name
Test status
Simulation time 164162892600 ps
CPU time 196.57 seconds
Started Jun 29 06:42:40 PM PDT 24
Finished Jun 29 06:45:58 PM PDT 24
Peak memory 201928 kb
Host smart-3e89f2ea-ae21-487c-b8d8-ab426625825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571775479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2571775479
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.925826244
Short name T275
Test name
Test status
Simulation time 497921359003 ps
CPU time 166.21 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:45:37 PM PDT 24
Peak memory 201916 kb
Host smart-6ab2d608-4702-4d67-9789-2573ac8c5216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925826244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.925826244
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.468061606
Short name T355
Test name
Test status
Simulation time 67906354787 ps
CPU time 145.46 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:45:12 PM PDT 24
Peak memory 210616 kb
Host smart-ffd4a430-eeea-4405-b077-b24d6ea4cfe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468061606 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.468061606
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3012025457
Short name T155
Test name
Test status
Simulation time 162765966374 ps
CPU time 351.67 seconds
Started Jun 29 06:42:40 PM PDT 24
Finished Jun 29 06:48:33 PM PDT 24
Peak memory 201876 kb
Host smart-11069156-c5f9-45df-8147-e81f7585f8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012025457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3012025457
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.4164396729
Short name T208
Test name
Test status
Simulation time 86640590640 ps
CPU time 307.51 seconds
Started Jun 29 06:41:50 PM PDT 24
Finished Jun 29 06:46:59 PM PDT 24
Peak memory 202204 kb
Host smart-fae7804b-7879-4162-b0f3-c5aea68dcaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164396729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.4164396729
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1813841140
Short name T253
Test name
Test status
Simulation time 514105736521 ps
CPU time 291.09 seconds
Started Jun 29 06:43:15 PM PDT 24
Finished Jun 29 06:48:06 PM PDT 24
Peak memory 201880 kb
Host smart-e2d931f5-c26e-4b0e-bd79-f860196094b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813841140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1813841140
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.243713959
Short name T213
Test name
Test status
Simulation time 248670973264 ps
CPU time 686.56 seconds
Started Jun 29 06:43:22 PM PDT 24
Finished Jun 29 06:54:49 PM PDT 24
Peak memory 211532 kb
Host smart-2c3d9270-f0d3-4625-bd8f-ad2a8e209029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243713959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
243713959
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.4277128636
Short name T23
Test name
Test status
Simulation time 47029903626 ps
CPU time 120.35 seconds
Started Jun 29 06:43:28 PM PDT 24
Finished Jun 29 06:45:29 PM PDT 24
Peak memory 217572 kb
Host smart-86dd2f3b-cf47-42d4-a8f2-0d7df7d9538f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277128636 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.4277128636
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2739843066
Short name T298
Test name
Test status
Simulation time 138270238429 ps
CPU time 337.51 seconds
Started Jun 29 06:43:43 PM PDT 24
Finished Jun 29 06:49:21 PM PDT 24
Peak memory 218024 kb
Host smart-fccf946d-bebb-43d9-8bf3-77b21fe2fc43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739843066 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2739843066
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3481092289
Short name T313
Test name
Test status
Simulation time 166687847714 ps
CPU time 93.4 seconds
Started Jun 29 06:41:52 PM PDT 24
Finished Jun 29 06:43:27 PM PDT 24
Peak memory 201928 kb
Host smart-9d97fe0b-b182-4b66-a30c-93242133b9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481092289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3481092289
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2991481513
Short name T898
Test name
Test status
Simulation time 633724863 ps
CPU time 2.78 seconds
Started Jun 29 06:41:11 PM PDT 24
Finished Jun 29 06:41:15 PM PDT 24
Peak memory 201728 kb
Host smart-1759f811-5ca1-4098-b23b-5023f1112d5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991481513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2991481513
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3460568757
Short name T865
Test name
Test status
Simulation time 789511630 ps
CPU time 0.94 seconds
Started Jun 29 06:41:15 PM PDT 24
Finished Jun 29 06:41:16 PM PDT 24
Peak memory 201512 kb
Host smart-17407403-ef5a-4d0a-935e-6d9d73c697e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460568757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3460568757
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4132042026
Short name T881
Test name
Test status
Simulation time 497238858 ps
CPU time 1.26 seconds
Started Jun 29 06:41:30 PM PDT 24
Finished Jun 29 06:41:32 PM PDT 24
Peak memory 201576 kb
Host smart-6628d461-5df0-4c50-9fcd-98faadc9cadc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132042026 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.4132042026
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2813095978
Short name T119
Test name
Test status
Simulation time 491135352 ps
CPU time 1.41 seconds
Started Jun 29 06:41:09 PM PDT 24
Finished Jun 29 06:41:10 PM PDT 24
Peak memory 201516 kb
Host smart-0027d7d0-0b13-4aa9-b916-aaec539c3f13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813095978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2813095978
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2122702814
Short name T906
Test name
Test status
Simulation time 387710380 ps
CPU time 0.84 seconds
Started Jun 29 06:41:21 PM PDT 24
Finished Jun 29 06:41:22 PM PDT 24
Peak memory 201440 kb
Host smart-c99d1eb3-e261-4610-aa86-c772ce706788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122702814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2122702814
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3714600939
Short name T910
Test name
Test status
Simulation time 2723515137 ps
CPU time 2.05 seconds
Started Jun 29 06:41:15 PM PDT 24
Finished Jun 29 06:41:18 PM PDT 24
Peak memory 201636 kb
Host smart-ed9cd59b-5fd4-4d00-8afd-c47b5e7c121d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714600939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3714600939
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2654887454
Short name T819
Test name
Test status
Simulation time 567091662 ps
CPU time 1.89 seconds
Started Jun 29 06:41:10 PM PDT 24
Finished Jun 29 06:41:13 PM PDT 24
Peak memory 201776 kb
Host smart-d4401d47-69a1-4a08-8c21-1d1cad5c7593
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654887454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2654887454
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3672160957
Short name T349
Test name
Test status
Simulation time 4548670260 ps
CPU time 6.1 seconds
Started Jun 29 06:41:10 PM PDT 24
Finished Jun 29 06:41:16 PM PDT 24
Peak memory 201868 kb
Host smart-ececc9bd-5c65-49be-bc0a-217c0d10d0d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672160957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3672160957
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3138694662
Short name T114
Test name
Test status
Simulation time 494676415 ps
CPU time 2.02 seconds
Started Jun 29 06:41:11 PM PDT 24
Finished Jun 29 06:41:14 PM PDT 24
Peak memory 201728 kb
Host smart-1f178832-d8f0-43f6-b2b1-541cdf61b64c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138694662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3138694662
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.362947902
Short name T118
Test name
Test status
Simulation time 2806851161 ps
CPU time 7.26 seconds
Started Jun 29 06:41:35 PM PDT 24
Finished Jun 29 06:41:43 PM PDT 24
Peak memory 201820 kb
Host smart-1ec1fe52-94ae-4264-a9aa-690e0cf41b7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362947902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.362947902
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.132590979
Short name T116
Test name
Test status
Simulation time 842557830 ps
CPU time 2.66 seconds
Started Jun 29 06:41:40 PM PDT 24
Finished Jun 29 06:41:44 PM PDT 24
Peak memory 201516 kb
Host smart-0a11f350-57ba-447a-935f-5d4d73a6bdca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132590979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.132590979
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3792981341
Short name T905
Test name
Test status
Simulation time 599839369 ps
CPU time 1.47 seconds
Started Jun 29 06:41:09 PM PDT 24
Finished Jun 29 06:41:11 PM PDT 24
Peak memory 201576 kb
Host smart-47390645-17c2-4615-804e-1460ece5260d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792981341 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3792981341
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.862282557
Short name T111
Test name
Test status
Simulation time 560059178 ps
CPU time 1.11 seconds
Started Jun 29 06:41:10 PM PDT 24
Finished Jun 29 06:41:11 PM PDT 24
Peak memory 201472 kb
Host smart-1296ff49-6d6e-4dee-985a-a6fa2b148b40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862282557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.862282557
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3285709258
Short name T893
Test name
Test status
Simulation time 474992490 ps
CPU time 1.8 seconds
Started Jun 29 06:41:22 PM PDT 24
Finished Jun 29 06:41:24 PM PDT 24
Peak memory 201440 kb
Host smart-5e5ecd55-00c5-45f2-9181-46d7f1ee82e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285709258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3285709258
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3384794000
Short name T867
Test name
Test status
Simulation time 4177954355 ps
CPU time 1.8 seconds
Started Jun 29 06:41:28 PM PDT 24
Finished Jun 29 06:41:30 PM PDT 24
Peak memory 201816 kb
Host smart-0dce630a-deed-43b9-8a32-522853c82c9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384794000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3384794000
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.977806419
Short name T919
Test name
Test status
Simulation time 664631189 ps
CPU time 1.72 seconds
Started Jun 29 06:41:12 PM PDT 24
Finished Jun 29 06:41:14 PM PDT 24
Peak memory 201748 kb
Host smart-8cab2de1-06ee-4f19-b5c5-8b49cf4f6c93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977806419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.977806419
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2005290693
Short name T351
Test name
Test status
Simulation time 8726509514 ps
CPU time 12.82 seconds
Started Jun 29 06:41:20 PM PDT 24
Finished Jun 29 06:41:33 PM PDT 24
Peak memory 201856 kb
Host smart-5a9fceae-80dc-40f5-88e5-aa7ffb4dd7b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005290693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2005290693
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2590790925
Short name T873
Test name
Test status
Simulation time 557345608 ps
CPU time 1.58 seconds
Started Jun 29 06:41:56 PM PDT 24
Finished Jun 29 06:42:00 PM PDT 24
Peak memory 201544 kb
Host smart-ab240964-8056-49cb-9ae9-ec948306100a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590790925 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2590790925
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3959176259
Short name T844
Test name
Test status
Simulation time 534956416 ps
CPU time 0.91 seconds
Started Jun 29 06:41:39 PM PDT 24
Finished Jun 29 06:41:40 PM PDT 24
Peak memory 201512 kb
Host smart-570c50d8-f241-4088-82c5-74067da1eb53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959176259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3959176259
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2644340902
Short name T797
Test name
Test status
Simulation time 350105544 ps
CPU time 0.82 seconds
Started Jun 29 06:41:41 PM PDT 24
Finished Jun 29 06:41:43 PM PDT 24
Peak memory 201444 kb
Host smart-0f3e8181-8b6c-4ecd-ba48-01a943664787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644340902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2644340902
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1634318229
Short name T853
Test name
Test status
Simulation time 2951149710 ps
CPU time 2.46 seconds
Started Jun 29 06:41:45 PM PDT 24
Finished Jun 29 06:41:48 PM PDT 24
Peak memory 201652 kb
Host smart-cef01852-6fc3-45a0-9f97-ac6845026660
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634318229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1634318229
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.410826017
Short name T837
Test name
Test status
Simulation time 594818952 ps
CPU time 1.92 seconds
Started Jun 29 06:41:39 PM PDT 24
Finished Jun 29 06:41:41 PM PDT 24
Peak memory 201816 kb
Host smart-0b564ddb-bfd7-448c-855e-695bededa4f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410826017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.410826017
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1602413116
Short name T849
Test name
Test status
Simulation time 8370830226 ps
CPU time 4.65 seconds
Started Jun 29 06:41:38 PM PDT 24
Finished Jun 29 06:41:43 PM PDT 24
Peak memory 201824 kb
Host smart-151dc6d0-e82d-4f78-b386-e148d5e23f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602413116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1602413116
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.18090218
Short name T885
Test name
Test status
Simulation time 493362030 ps
CPU time 1.38 seconds
Started Jun 29 06:41:42 PM PDT 24
Finished Jun 29 06:41:44 PM PDT 24
Peak memory 201572 kb
Host smart-5305f588-e7f8-4f12-bf4c-4be1d6f63f0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18090218 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.18090218
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.964572360
Short name T108
Test name
Test status
Simulation time 570976402 ps
CPU time 1.41 seconds
Started Jun 29 06:41:34 PM PDT 24
Finished Jun 29 06:41:36 PM PDT 24
Peak memory 201440 kb
Host smart-5f1fba6b-0544-40de-9d74-fcb23fb63681
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964572360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.964572360
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3782479255
Short name T848
Test name
Test status
Simulation time 339475716 ps
CPU time 1.01 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:41:48 PM PDT 24
Peak memory 201412 kb
Host smart-96460603-3f34-4b4d-ae9e-369d250d3309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782479255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3782479255
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3138854472
Short name T830
Test name
Test status
Simulation time 4470192900 ps
CPU time 9.38 seconds
Started Jun 29 06:41:35 PM PDT 24
Finished Jun 29 06:41:45 PM PDT 24
Peak memory 201860 kb
Host smart-3013b9ae-2b0c-436a-92f3-ea5a7cf10fbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138854472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3138854472
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1887167776
Short name T347
Test name
Test status
Simulation time 4359064684 ps
CPU time 9.97 seconds
Started Jun 29 06:41:58 PM PDT 24
Finished Jun 29 06:42:10 PM PDT 24
Peak memory 201824 kb
Host smart-381cd33f-8bc2-4bad-8c6f-c13aa6e9cf58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887167776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1887167776
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2841251672
Short name T104
Test name
Test status
Simulation time 485376065 ps
CPU time 1.09 seconds
Started Jun 29 06:41:35 PM PDT 24
Finished Jun 29 06:41:36 PM PDT 24
Peak memory 201528 kb
Host smart-874cf888-f355-41b1-ac6e-3a8fb29dc7ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841251672 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2841251672
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.843125271
Short name T820
Test name
Test status
Simulation time 358973776 ps
CPU time 0.95 seconds
Started Jun 29 06:41:43 PM PDT 24
Finished Jun 29 06:41:45 PM PDT 24
Peak memory 201444 kb
Host smart-2bd4b0b2-a5e5-438d-8a17-c194676c845c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843125271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.843125271
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2432619160
Short name T874
Test name
Test status
Simulation time 520197087 ps
CPU time 1.22 seconds
Started Jun 29 06:41:45 PM PDT 24
Finished Jun 29 06:41:47 PM PDT 24
Peak memory 201432 kb
Host smart-362a4771-118e-4dca-8617-6db647ca2eff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432619160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2432619160
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.933454800
Short name T821
Test name
Test status
Simulation time 4697776255 ps
CPU time 3.77 seconds
Started Jun 29 06:41:44 PM PDT 24
Finished Jun 29 06:41:49 PM PDT 24
Peak memory 201868 kb
Host smart-cb2c7009-ab33-4110-b011-0de11c836310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933454800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.933454800
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1224019343
Short name T908
Test name
Test status
Simulation time 556566507 ps
CPU time 3.75 seconds
Started Jun 29 06:41:39 PM PDT 24
Finished Jun 29 06:41:43 PM PDT 24
Peak memory 210984 kb
Host smart-450a0c4f-98b5-4cc7-b04e-5b96edc6dac4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224019343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1224019343
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3685090927
Short name T887
Test name
Test status
Simulation time 7841592892 ps
CPU time 11.94 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:42:03 PM PDT 24
Peak memory 201856 kb
Host smart-1e0c2c3b-cfc5-4dc6-8b0e-a8d111cc7fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685090927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3685090927
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1025939390
Short name T806
Test name
Test status
Simulation time 597749370 ps
CPU time 1.69 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:41:50 PM PDT 24
Peak memory 201552 kb
Host smart-175fc615-44d7-46a4-af52-533a5cc15744
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025939390 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1025939390
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1503056154
Short name T891
Test name
Test status
Simulation time 332578629 ps
CPU time 1.13 seconds
Started Jun 29 06:41:49 PM PDT 24
Finished Jun 29 06:41:51 PM PDT 24
Peak memory 201516 kb
Host smart-21b3a767-5662-465f-be2b-8974d5703d4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503056154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1503056154
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.212414283
Short name T800
Test name
Test status
Simulation time 393773325 ps
CPU time 1.61 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:41:58 PM PDT 24
Peak memory 201436 kb
Host smart-34010a4d-1eb8-4e08-b5f1-e270f385f942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212414283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.212414283
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2628439514
Short name T818
Test name
Test status
Simulation time 2660757792 ps
CPU time 9.75 seconds
Started Jun 29 06:41:52 PM PDT 24
Finished Jun 29 06:42:03 PM PDT 24
Peak memory 201856 kb
Host smart-aaf6ff60-723f-4659-a071-79cc2d7d0e99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628439514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2628439514
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3729803908
Short name T916
Test name
Test status
Simulation time 497122753 ps
CPU time 3.3 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:42:01 PM PDT 24
Peak memory 201776 kb
Host smart-1c2e02ad-ea54-4102-9b5d-88ac134d5ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729803908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3729803908
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4051493644
Short name T808
Test name
Test status
Simulation time 554959454 ps
CPU time 1.34 seconds
Started Jun 29 06:41:41 PM PDT 24
Finished Jun 29 06:41:42 PM PDT 24
Peak memory 201568 kb
Host smart-fc0f7a5b-88e1-49d0-8def-0c076e7d8152
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051493644 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.4051493644
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.623790071
Short name T894
Test name
Test status
Simulation time 424934566 ps
CPU time 1.18 seconds
Started Jun 29 06:41:40 PM PDT 24
Finished Jun 29 06:41:42 PM PDT 24
Peak memory 201436 kb
Host smart-9023a3e2-fb9b-4dd9-8ffc-69ab01afa549
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623790071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.623790071
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3239231262
Short name T879
Test name
Test status
Simulation time 454728093 ps
CPU time 0.9 seconds
Started Jun 29 06:41:39 PM PDT 24
Finished Jun 29 06:41:41 PM PDT 24
Peak memory 201408 kb
Host smart-74cc3720-5bd0-4811-a3c7-24f7435e3581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239231262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3239231262
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1868312350
Short name T822
Test name
Test status
Simulation time 2570688584 ps
CPU time 3.14 seconds
Started Jun 29 06:41:38 PM PDT 24
Finished Jun 29 06:41:42 PM PDT 24
Peak memory 201652 kb
Host smart-121b92b3-f465-4371-87c1-78ac9e8696a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868312350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1868312350
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2922563939
Short name T72
Test name
Test status
Simulation time 1011206140 ps
CPU time 2.62 seconds
Started Jun 29 06:41:50 PM PDT 24
Finished Jun 29 06:41:53 PM PDT 24
Peak memory 201744 kb
Host smart-6db1d254-b5d2-47af-89aa-5319591e0bb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922563939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2922563939
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2765135545
Short name T64
Test name
Test status
Simulation time 4226299506 ps
CPU time 3.06 seconds
Started Jun 29 06:41:42 PM PDT 24
Finished Jun 29 06:41:46 PM PDT 24
Peak memory 201888 kb
Host smart-ca0378f6-73d4-4174-b0dc-a3cc3fda8cea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765135545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2765135545
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4125481564
Short name T871
Test name
Test status
Simulation time 805992685 ps
CPU time 1.19 seconds
Started Jun 29 06:41:35 PM PDT 24
Finished Jun 29 06:41:37 PM PDT 24
Peak memory 201588 kb
Host smart-eaf69d38-b8cb-4f84-ab69-e9ca968b2837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125481564 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.4125481564
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2751867455
Short name T832
Test name
Test status
Simulation time 421110918 ps
CPU time 1.38 seconds
Started Jun 29 06:41:44 PM PDT 24
Finished Jun 29 06:41:46 PM PDT 24
Peak memory 201516 kb
Host smart-d3f53a74-f069-4657-b1cc-87f60697c99b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751867455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2751867455
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.830326657
Short name T825
Test name
Test status
Simulation time 393860673 ps
CPU time 0.92 seconds
Started Jun 29 06:41:43 PM PDT 24
Finished Jun 29 06:41:45 PM PDT 24
Peak memory 201636 kb
Host smart-ad810074-5649-48a7-a55b-a7980ac8d6ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830326657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.830326657
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2622309637
Short name T855
Test name
Test status
Simulation time 5127297592 ps
CPU time 19.31 seconds
Started Jun 29 06:41:39 PM PDT 24
Finished Jun 29 06:41:59 PM PDT 24
Peak memory 201836 kb
Host smart-41e1de6a-8639-4b4f-9b7e-20e5d19e1980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622309637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2622309637
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.399202520
Short name T71
Test name
Test status
Simulation time 446157779 ps
CPU time 1.88 seconds
Started Jun 29 06:41:56 PM PDT 24
Finished Jun 29 06:42:00 PM PDT 24
Peak memory 201784 kb
Host smart-0ce0731a-bd64-48dd-9f4d-b93b9e9c3703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399202520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.399202520
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1680064904
Short name T888
Test name
Test status
Simulation time 8254526824 ps
CPU time 5.47 seconds
Started Jun 29 06:41:45 PM PDT 24
Finished Jun 29 06:41:52 PM PDT 24
Peak memory 201852 kb
Host smart-a557acd0-c714-4831-a6b1-497d1f2c9828
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680064904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1680064904
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3740297214
Short name T846
Test name
Test status
Simulation time 477230728 ps
CPU time 2.07 seconds
Started Jun 29 06:41:32 PM PDT 24
Finished Jun 29 06:41:35 PM PDT 24
Peak memory 201572 kb
Host smart-ba6e321a-5d34-4208-a34b-20f986abb0ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740297214 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3740297214
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2161676734
Short name T840
Test name
Test status
Simulation time 389454970 ps
CPU time 0.92 seconds
Started Jun 29 06:41:37 PM PDT 24
Finished Jun 29 06:41:39 PM PDT 24
Peak memory 201452 kb
Host smart-02615ec4-331e-4e06-9b98-8ba50c0a8fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161676734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2161676734
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3016141906
Short name T886
Test name
Test status
Simulation time 2331803987 ps
CPU time 2.91 seconds
Started Jun 29 06:41:40 PM PDT 24
Finished Jun 29 06:41:43 PM PDT 24
Peak memory 201648 kb
Host smart-337f979c-d346-49f4-acbd-398d46a9c578
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016141906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3016141906
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1503376761
Short name T74
Test name
Test status
Simulation time 573739912 ps
CPU time 2.57 seconds
Started Jun 29 06:41:40 PM PDT 24
Finished Jun 29 06:41:43 PM PDT 24
Peak memory 217668 kb
Host smart-03eb22da-1085-44f9-9811-519c8f33bb6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503376761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1503376761
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.21762959
Short name T65
Test name
Test status
Simulation time 7724416345 ps
CPU time 11.19 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:42:06 PM PDT 24
Peak memory 201752 kb
Host smart-f0328a2f-814b-48fc-af1a-383a8a514154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21762959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_int
g_err.21762959
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2266349321
Short name T824
Test name
Test status
Simulation time 400487297 ps
CPU time 1.67 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:41:49 PM PDT 24
Peak memory 201544 kb
Host smart-094366c3-cf8c-419c-8955-15df63b6105a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266349321 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2266349321
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1194636999
Short name T813
Test name
Test status
Simulation time 481232147 ps
CPU time 1.32 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:41:54 PM PDT 24
Peak memory 201512 kb
Host smart-921b98c2-bba6-48f7-a8fd-c52e9c5f74cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194636999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1194636999
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3762387788
Short name T866
Test name
Test status
Simulation time 485268419 ps
CPU time 0.89 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:41:56 PM PDT 24
Peak memory 201448 kb
Host smart-613f2b31-e42d-46ff-94fa-519f53d9a2f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762387788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3762387788
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3801289331
Short name T122
Test name
Test status
Simulation time 4529322444 ps
CPU time 2.11 seconds
Started Jun 29 06:42:12 PM PDT 24
Finished Jun 29 06:42:15 PM PDT 24
Peak memory 201780 kb
Host smart-0491db10-8aa6-4b63-825d-9bee9655b585
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801289331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3801289331
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2991754220
Short name T899
Test name
Test status
Simulation time 463776602 ps
CPU time 2.15 seconds
Started Jun 29 06:41:45 PM PDT 24
Finished Jun 29 06:41:47 PM PDT 24
Peak memory 201752 kb
Host smart-c91265e1-7215-44f5-a53c-1fead5ac819a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991754220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2991754220
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.669192892
Short name T839
Test name
Test status
Simulation time 7986394675 ps
CPU time 11.51 seconds
Started Jun 29 06:41:42 PM PDT 24
Finished Jun 29 06:41:54 PM PDT 24
Peak memory 201856 kb
Host smart-43ffd49e-9712-4c01-9796-98493d14252b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669192892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.669192892
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3929277054
Short name T882
Test name
Test status
Simulation time 364507375 ps
CPU time 1.61 seconds
Started Jun 29 06:41:45 PM PDT 24
Finished Jun 29 06:41:47 PM PDT 24
Peak memory 201508 kb
Host smart-7de901a0-d844-4d78-833b-e60bab55065e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929277054 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3929277054
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2833598216
Short name T123
Test name
Test status
Simulation time 432822482 ps
CPU time 1.74 seconds
Started Jun 29 06:41:58 PM PDT 24
Finished Jun 29 06:42:01 PM PDT 24
Peak memory 201716 kb
Host smart-5298985b-3148-4a78-a691-f8370e6c9a5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833598216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2833598216
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2950995926
Short name T799
Test name
Test status
Simulation time 300285772 ps
CPU time 1.28 seconds
Started Jun 29 06:41:44 PM PDT 24
Finished Jun 29 06:41:46 PM PDT 24
Peak memory 201432 kb
Host smart-6f08b8a5-1ce3-4ad2-b038-9114fab0ab9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950995926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2950995926
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.63280218
Short name T120
Test name
Test status
Simulation time 3942318855 ps
CPU time 3.47 seconds
Started Jun 29 06:41:42 PM PDT 24
Finished Jun 29 06:41:46 PM PDT 24
Peak memory 201856 kb
Host smart-2e9187ce-0798-42fa-9bb2-e0fdddf77d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63280218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ct
rl_same_csr_outstanding.63280218
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.861363627
Short name T912
Test name
Test status
Simulation time 545088083 ps
CPU time 1.84 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:41:57 PM PDT 24
Peak memory 201752 kb
Host smart-1eecb18a-5790-4c66-858f-cf0b2c416d5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861363627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.861363627
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2528354820
Short name T907
Test name
Test status
Simulation time 4392329799 ps
CPU time 4.17 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:41:51 PM PDT 24
Peak memory 201888 kb
Host smart-4bd55174-7380-4214-b407-df9281ca8544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528354820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2528354820
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3532573916
Short name T811
Test name
Test status
Simulation time 497131466 ps
CPU time 1.17 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:41:48 PM PDT 24
Peak memory 201576 kb
Host smart-e8108035-7048-447b-b506-2c0c01f952ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532573916 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3532573916
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3216832360
Short name T857
Test name
Test status
Simulation time 447930706 ps
CPU time 1.04 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:41:49 PM PDT 24
Peak memory 201528 kb
Host smart-e8a67f55-45af-49b8-acae-d1f219bd5992
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216832360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3216832360
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2852319121
Short name T829
Test name
Test status
Simulation time 529101182 ps
CPU time 1.21 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:41:49 PM PDT 24
Peak memory 201436 kb
Host smart-3d9aa0e2-c2c6-4222-a791-16b9ab46d55e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852319121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2852319121
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1436815642
Short name T900
Test name
Test status
Simulation time 4719355532 ps
CPU time 5.04 seconds
Started Jun 29 06:41:52 PM PDT 24
Finished Jun 29 06:41:59 PM PDT 24
Peak memory 201800 kb
Host smart-2ae45879-26be-4602-899d-cb0fcf7384c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436815642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1436815642
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.660228903
Short name T854
Test name
Test status
Simulation time 590581085 ps
CPU time 2.45 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:41:55 PM PDT 24
Peak memory 210968 kb
Host smart-05464504-58b3-4484-9305-edaf8ac76748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660228903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.660228903
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1124554476
Short name T831
Test name
Test status
Simulation time 9365356659 ps
CPU time 4.28 seconds
Started Jun 29 06:41:40 PM PDT 24
Finished Jun 29 06:41:44 PM PDT 24
Peak memory 201868 kb
Host smart-04a73800-78a3-4653-914c-8ae75c5ede14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124554476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1124554476
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1807039981
Short name T878
Test name
Test status
Simulation time 1024313280 ps
CPU time 3.9 seconds
Started Jun 29 06:41:32 PM PDT 24
Finished Jun 29 06:41:37 PM PDT 24
Peak memory 201676 kb
Host smart-8fcc2c62-37be-42ce-a3c0-3a0579c1422a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807039981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1807039981
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2772999960
Short name T59
Test name
Test status
Simulation time 28460833165 ps
CPU time 24.29 seconds
Started Jun 29 06:41:29 PM PDT 24
Finished Jun 29 06:41:54 PM PDT 24
Peak memory 201896 kb
Host smart-9d209114-d764-4b4c-9989-cc7302f33397
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772999960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2772999960
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4270971670
Short name T836
Test name
Test status
Simulation time 652893830 ps
CPU time 1 seconds
Started Jun 29 06:41:10 PM PDT 24
Finished Jun 29 06:41:11 PM PDT 24
Peak memory 201508 kb
Host smart-a009cdef-f94c-4d6a-b27b-1ab2826d0458
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270971670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.4270971670
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3457474863
Short name T93
Test name
Test status
Simulation time 543345843 ps
CPU time 2.28 seconds
Started Jun 29 06:41:11 PM PDT 24
Finished Jun 29 06:41:14 PM PDT 24
Peak memory 201532 kb
Host smart-6cb18528-8ad7-4596-8ff6-397e4467f4d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457474863 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3457474863
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4194019018
Short name T113
Test name
Test status
Simulation time 536452063 ps
CPU time 1.06 seconds
Started Jun 29 06:41:11 PM PDT 24
Finished Jun 29 06:41:13 PM PDT 24
Peak memory 201472 kb
Host smart-c565ccef-f405-4b65-a0a2-1e4ecfae129b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194019018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.4194019018
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2998778028
Short name T841
Test name
Test status
Simulation time 493602610 ps
CPU time 1.24 seconds
Started Jun 29 06:41:30 PM PDT 24
Finished Jun 29 06:41:31 PM PDT 24
Peak memory 201440 kb
Host smart-48d481ff-6485-482b-b604-929b39b83bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998778028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2998778028
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2180257837
Short name T828
Test name
Test status
Simulation time 1943784954 ps
CPU time 2.9 seconds
Started Jun 29 06:41:09 PM PDT 24
Finished Jun 29 06:41:12 PM PDT 24
Peak memory 201448 kb
Host smart-aac13e2b-b4f6-4ac4-a54d-09c1379c1e15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180257837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2180257837
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2357565135
Short name T78
Test name
Test status
Simulation time 406514765 ps
CPU time 3.3 seconds
Started Jun 29 06:41:12 PM PDT 24
Finished Jun 29 06:41:15 PM PDT 24
Peak memory 201740 kb
Host smart-6edc5e7c-fcef-4b4e-8425-81a6cb95ebb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357565135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2357565135
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1534405893
Short name T79
Test name
Test status
Simulation time 4082902543 ps
CPU time 11.83 seconds
Started Jun 29 06:41:26 PM PDT 24
Finished Jun 29 06:41:38 PM PDT 24
Peak memory 201784 kb
Host smart-0218a13d-93fb-4dfb-bd8e-87109afa9f7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534405893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1534405893
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1548133483
Short name T803
Test name
Test status
Simulation time 471169869 ps
CPU time 1.69 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:41:58 PM PDT 24
Peak memory 201440 kb
Host smart-6a1fa567-2a5e-4e12-8ca9-31f857b7a89c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548133483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1548133483
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.425271110
Short name T889
Test name
Test status
Simulation time 295892356 ps
CPU time 1.33 seconds
Started Jun 29 06:41:52 PM PDT 24
Finished Jun 29 06:41:55 PM PDT 24
Peak memory 201440 kb
Host smart-e700abb3-94a9-42db-a3ca-90d2de9ad7a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425271110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.425271110
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1912865379
Short name T842
Test name
Test status
Simulation time 447875901 ps
CPU time 0.7 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:41:58 PM PDT 24
Peak memory 201448 kb
Host smart-9e37298d-d568-4f47-9968-888dd431d138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912865379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1912865379
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2007382943
Short name T911
Test name
Test status
Simulation time 435037313 ps
CPU time 1.61 seconds
Started Jun 29 06:41:48 PM PDT 24
Finished Jun 29 06:41:50 PM PDT 24
Peak memory 201412 kb
Host smart-31f86882-6c5b-4b17-a56b-15c8a31026f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007382943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2007382943
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3564705290
Short name T798
Test name
Test status
Simulation time 287132474 ps
CPU time 1.31 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:41:53 PM PDT 24
Peak memory 201432 kb
Host smart-2ad2fd29-e64e-44db-bf05-810707dd9dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564705290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3564705290
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1849465606
Short name T876
Test name
Test status
Simulation time 493122994 ps
CPU time 0.83 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:42:00 PM PDT 24
Peak memory 201436 kb
Host smart-20e4bb4e-0f47-4f0d-9d07-67c1b99ba7ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849465606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1849465606
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1132388554
Short name T835
Test name
Test status
Simulation time 434394175 ps
CPU time 1.14 seconds
Started Jun 29 06:41:43 PM PDT 24
Finished Jun 29 06:41:45 PM PDT 24
Peak memory 201436 kb
Host smart-62eb18e3-5d7d-4e4d-ad53-20c2dda00825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132388554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1132388554
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3906598842
Short name T913
Test name
Test status
Simulation time 391241705 ps
CPU time 1.17 seconds
Started Jun 29 06:42:04 PM PDT 24
Finished Jun 29 06:42:06 PM PDT 24
Peak memory 201432 kb
Host smart-a8d2a85c-b0fb-492e-9e75-240add4e4dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906598842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3906598842
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.701300570
Short name T814
Test name
Test status
Simulation time 509885865 ps
CPU time 1.8 seconds
Started Jun 29 06:41:44 PM PDT 24
Finished Jun 29 06:41:46 PM PDT 24
Peak memory 201416 kb
Host smart-dc75a995-c610-4eda-80ac-3efc69852ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701300570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.701300570
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1304934719
Short name T816
Test name
Test status
Simulation time 386801098 ps
CPU time 0.86 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:41:48 PM PDT 24
Peak memory 201436 kb
Host smart-364ab887-a311-4c96-91f8-248bef496cfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304934719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1304934719
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2868136240
Short name T864
Test name
Test status
Simulation time 1033778586 ps
CPU time 5.56 seconds
Started Jun 29 06:41:11 PM PDT 24
Finished Jun 29 06:41:17 PM PDT 24
Peak memory 201732 kb
Host smart-cf5c6cdb-bdc5-4571-88d8-305804ac9747
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868136240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2868136240
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2457302747
Short name T918
Test name
Test status
Simulation time 52605936794 ps
CPU time 114.63 seconds
Started Jun 29 06:41:13 PM PDT 24
Finished Jun 29 06:43:08 PM PDT 24
Peak memory 201808 kb
Host smart-f8857af3-7ae0-4d3c-9b42-ea3efc15d05f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457302747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2457302747
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3554452428
Short name T834
Test name
Test status
Simulation time 1033324446 ps
CPU time 1.45 seconds
Started Jun 29 06:41:36 PM PDT 24
Finished Jun 29 06:41:38 PM PDT 24
Peak memory 201440 kb
Host smart-99423f8a-77c8-4adb-96ff-7544a323fe1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554452428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3554452428
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3327270375
Short name T91
Test name
Test status
Simulation time 573184346 ps
CPU time 1.27 seconds
Started Jun 29 06:41:30 PM PDT 24
Finished Jun 29 06:41:31 PM PDT 24
Peak memory 201772 kb
Host smart-2086e658-ffb0-4ad1-b06b-7a849628cb45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327270375 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3327270375
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1609443954
Short name T112
Test name
Test status
Simulation time 530277035 ps
CPU time 1.3 seconds
Started Jun 29 06:41:09 PM PDT 24
Finished Jun 29 06:41:11 PM PDT 24
Peak memory 201516 kb
Host smart-22cf1646-a7d6-48f7-b5b7-6e85716e2145
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609443954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1609443954
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.24680319
Short name T804
Test name
Test status
Simulation time 394997485 ps
CPU time 1.14 seconds
Started Jun 29 06:41:10 PM PDT 24
Finished Jun 29 06:41:12 PM PDT 24
Peak memory 201440 kb
Host smart-064d89de-8e2f-41c4-8b89-af809eb111ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24680319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.24680319
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2222245951
Short name T61
Test name
Test status
Simulation time 2273221247 ps
CPU time 2.23 seconds
Started Jun 29 06:41:29 PM PDT 24
Finished Jun 29 06:41:32 PM PDT 24
Peak memory 201644 kb
Host smart-e1d5c663-c518-469f-abab-f79beae7afdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222245951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2222245951
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1776925975
Short name T827
Test name
Test status
Simulation time 472443264 ps
CPU time 1.98 seconds
Started Jun 29 06:41:29 PM PDT 24
Finished Jun 29 06:41:31 PM PDT 24
Peak memory 201776 kb
Host smart-8af8d70f-e608-439b-ac10-bb36dc1ce8dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776925975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1776925975
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1863059922
Short name T823
Test name
Test status
Simulation time 472433445 ps
CPU time 0.72 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:41:58 PM PDT 24
Peak memory 201436 kb
Host smart-2d9e2a82-564b-408b-bd67-84e137909d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863059922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1863059922
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.170000647
Short name T838
Test name
Test status
Simulation time 402493821 ps
CPU time 1.58 seconds
Started Jun 29 06:41:49 PM PDT 24
Finished Jun 29 06:41:51 PM PDT 24
Peak memory 201412 kb
Host smart-f5d7aa09-9e27-4c6e-99df-71272697a9dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170000647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.170000647
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3394303768
Short name T862
Test name
Test status
Simulation time 333203315 ps
CPU time 1.04 seconds
Started Jun 29 06:42:12 PM PDT 24
Finished Jun 29 06:42:13 PM PDT 24
Peak memory 201432 kb
Host smart-4ac77675-7531-45d5-bdf2-766eb56d3d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394303768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3394303768
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3211619869
Short name T870
Test name
Test status
Simulation time 518877945 ps
CPU time 1.3 seconds
Started Jun 29 06:41:49 PM PDT 24
Finished Jun 29 06:41:51 PM PDT 24
Peak memory 201432 kb
Host smart-8b267057-dda1-4bdf-a057-8d2afeb0de94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211619869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3211619869
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2529637146
Short name T861
Test name
Test status
Simulation time 389915779 ps
CPU time 1.61 seconds
Started Jun 29 06:41:38 PM PDT 24
Finished Jun 29 06:41:40 PM PDT 24
Peak memory 201436 kb
Host smart-beb15060-fe55-4a76-a3a2-b91778ad9617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529637146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2529637146
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.381065407
Short name T812
Test name
Test status
Simulation time 363789128 ps
CPU time 1.08 seconds
Started Jun 29 06:41:45 PM PDT 24
Finished Jun 29 06:41:47 PM PDT 24
Peak memory 201436 kb
Host smart-5b440c73-701b-4b55-9132-e06725a46799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381065407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.381065407
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.695819427
Short name T917
Test name
Test status
Simulation time 462634142 ps
CPU time 0.96 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:41:49 PM PDT 24
Peak memory 201440 kb
Host smart-fb2bb60b-a7af-423a-9eb7-2d38370adfa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695819427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.695819427
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4074637207
Short name T817
Test name
Test status
Simulation time 362330195 ps
CPU time 1.48 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:41:50 PM PDT 24
Peak memory 201436 kb
Host smart-7982152e-f3e8-4883-a217-59868de2ed8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074637207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.4074637207
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3904859455
Short name T863
Test name
Test status
Simulation time 384729478 ps
CPU time 1.49 seconds
Started Jun 29 06:42:02 PM PDT 24
Finished Jun 29 06:42:04 PM PDT 24
Peak memory 201364 kb
Host smart-caf003eb-a71b-4ce1-b2d6-180523ea97ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904859455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3904859455
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.737923437
Short name T903
Test name
Test status
Simulation time 336251738 ps
CPU time 0.76 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:41:49 PM PDT 24
Peak memory 201440 kb
Host smart-66e90c67-a436-45dc-9958-16862d3566c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737923437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.737923437
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2324676224
Short name T109
Test name
Test status
Simulation time 701164250 ps
CPU time 2.98 seconds
Started Jun 29 06:41:34 PM PDT 24
Finished Jun 29 06:41:37 PM PDT 24
Peak memory 201728 kb
Host smart-01b56976-a1d0-4be1-9792-f2d8ff4f49d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324676224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2324676224
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1594845528
Short name T117
Test name
Test status
Simulation time 1535413344 ps
CPU time 3.92 seconds
Started Jun 29 06:41:28 PM PDT 24
Finished Jun 29 06:41:33 PM PDT 24
Peak memory 201756 kb
Host smart-02258bfb-6a33-4446-9050-2ae950c9ac50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594845528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1594845528
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3350666597
Short name T851
Test name
Test status
Simulation time 582499033 ps
CPU time 1.01 seconds
Started Jun 29 06:41:11 PM PDT 24
Finished Jun 29 06:41:13 PM PDT 24
Peak memory 201512 kb
Host smart-f3b8cc2d-e336-411f-926b-d1b2aedfeff9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350666597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3350666597
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2169223425
Short name T809
Test name
Test status
Simulation time 528558246 ps
CPU time 1.36 seconds
Started Jun 29 06:41:30 PM PDT 24
Finished Jun 29 06:41:32 PM PDT 24
Peak memory 201592 kb
Host smart-88de6cbc-d181-4cec-85bd-5fff5d8705cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169223425 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2169223425
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1172051153
Short name T915
Test name
Test status
Simulation time 333730068 ps
CPU time 1.58 seconds
Started Jun 29 06:41:35 PM PDT 24
Finished Jun 29 06:41:37 PM PDT 24
Peak memory 201512 kb
Host smart-d4b3a53f-5022-4ce5-9d2f-e92a86ef33b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172051153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1172051153
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3562722637
Short name T833
Test name
Test status
Simulation time 473956579 ps
CPU time 1.67 seconds
Started Jun 29 06:41:09 PM PDT 24
Finished Jun 29 06:41:11 PM PDT 24
Peak memory 201440 kb
Host smart-7859847e-2768-421e-b1f9-3375ea19bc76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562722637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3562722637
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3209210842
Short name T860
Test name
Test status
Simulation time 5098749839 ps
CPU time 3.82 seconds
Started Jun 29 06:41:32 PM PDT 24
Finished Jun 29 06:41:36 PM PDT 24
Peak memory 201888 kb
Host smart-8dcb9a4b-a9ae-480e-9465-04609c7373c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209210842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3209210842
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.187964616
Short name T880
Test name
Test status
Simulation time 529612159 ps
CPU time 2.85 seconds
Started Jun 29 06:41:10 PM PDT 24
Finished Jun 29 06:41:14 PM PDT 24
Peak memory 217988 kb
Host smart-6340f991-bbf4-4d52-aef4-e2d1d5ad58dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187964616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.187964616
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2703642303
Short name T869
Test name
Test status
Simulation time 8130341542 ps
CPU time 19.39 seconds
Started Jun 29 06:41:13 PM PDT 24
Finished Jun 29 06:41:33 PM PDT 24
Peak memory 201852 kb
Host smart-901a9e3a-bdd2-4e53-ab9d-b38cb16c0cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703642303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2703642303
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.774647253
Short name T801
Test name
Test status
Simulation time 291516014 ps
CPU time 1.3 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:41:56 PM PDT 24
Peak memory 201440 kb
Host smart-d92cc6f9-659b-4919-a174-e29e406dfd15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774647253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.774647253
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3555843664
Short name T896
Test name
Test status
Simulation time 580133937 ps
CPU time 0.74 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:41:47 PM PDT 24
Peak memory 201440 kb
Host smart-8fd98c35-7810-4b2c-a69e-b05185b99802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555843664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3555843664
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3457102570
Short name T845
Test name
Test status
Simulation time 426757284 ps
CPU time 0.87 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:41:58 PM PDT 24
Peak memory 201448 kb
Host smart-1af9d57a-acbb-441c-97d7-7f184eba942a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457102570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3457102570
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.208024608
Short name T892
Test name
Test status
Simulation time 394688661 ps
CPU time 1.55 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:41:58 PM PDT 24
Peak memory 201440 kb
Host smart-dfba87db-78f6-4b3b-a55c-ea848e72f973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208024608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.208024608
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1408190207
Short name T802
Test name
Test status
Simulation time 303757785 ps
CPU time 1 seconds
Started Jun 29 06:41:48 PM PDT 24
Finished Jun 29 06:41:50 PM PDT 24
Peak memory 201388 kb
Host smart-bfd6adbf-d563-494b-b664-0781b9b7faf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408190207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1408190207
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1432981028
Short name T847
Test name
Test status
Simulation time 456612270 ps
CPU time 0.93 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:41:58 PM PDT 24
Peak memory 201440 kb
Host smart-3f1be38a-08df-4633-937e-e2c73b67742b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432981028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1432981028
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3421976211
Short name T897
Test name
Test status
Simulation time 461562653 ps
CPU time 1.73 seconds
Started Jun 29 06:42:03 PM PDT 24
Finished Jun 29 06:42:05 PM PDT 24
Peak memory 201440 kb
Host smart-5473ed2d-88b8-4331-8329-5ddeb203fc20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421976211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3421976211
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.875795843
Short name T884
Test name
Test status
Simulation time 558595272 ps
CPU time 0.82 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:41:53 PM PDT 24
Peak memory 201376 kb
Host smart-6cd8e989-b179-4812-bf59-169f5ffb6ea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875795843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.875795843
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1935674518
Short name T796
Test name
Test status
Simulation time 417097479 ps
CPU time 1.06 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:41:49 PM PDT 24
Peak memory 201432 kb
Host smart-55760015-1316-4c27-8095-ced55e7cdc74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935674518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1935674518
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2158059141
Short name T807
Test name
Test status
Simulation time 374506298 ps
CPU time 1.02 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:41:48 PM PDT 24
Peak memory 201412 kb
Host smart-b239a932-a70c-412a-984a-79271cb9448e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158059141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2158059141
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2343873981
Short name T875
Test name
Test status
Simulation time 405069966 ps
CPU time 1.84 seconds
Started Jun 29 06:41:44 PM PDT 24
Finished Jun 29 06:41:46 PM PDT 24
Peak memory 201504 kb
Host smart-1fefc70c-f7a7-401c-b5c4-ab87a34cfdf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343873981 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2343873981
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4160563517
Short name T850
Test name
Test status
Simulation time 574932066 ps
CPU time 2.16 seconds
Started Jun 29 06:41:45 PM PDT 24
Finished Jun 29 06:41:48 PM PDT 24
Peak memory 201508 kb
Host smart-6a374484-3e5e-4a8d-87c7-8ee799b33442
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160563517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4160563517
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1049949330
Short name T805
Test name
Test status
Simulation time 346558747 ps
CPU time 0.92 seconds
Started Jun 29 06:41:30 PM PDT 24
Finished Jun 29 06:41:31 PM PDT 24
Peak memory 201452 kb
Host smart-2ab4de14-b643-46a2-931b-1268d0cbb057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049949330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1049949330
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4216880351
Short name T909
Test name
Test status
Simulation time 4371955581 ps
CPU time 5.39 seconds
Started Jun 29 06:41:42 PM PDT 24
Finished Jun 29 06:41:48 PM PDT 24
Peak memory 201856 kb
Host smart-b4499c95-78cb-4c6b-a94a-55a0684e5a47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216880351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.4216880351
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2070952370
Short name T67
Test name
Test status
Simulation time 710616860 ps
CPU time 2.16 seconds
Started Jun 29 06:41:37 PM PDT 24
Finished Jun 29 06:41:39 PM PDT 24
Peak memory 211024 kb
Host smart-99b47343-178e-4093-9b9b-d7edd554ccbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070952370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2070952370
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3113925864
Short name T350
Test name
Test status
Simulation time 8846519280 ps
CPU time 6.1 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:41:53 PM PDT 24
Peak memory 201836 kb
Host smart-0ae16131-917f-48dd-ab1e-31b4c3802089
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113925864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3113925864
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1694713232
Short name T877
Test name
Test status
Simulation time 427860197 ps
CPU time 1.07 seconds
Started Jun 29 06:41:33 PM PDT 24
Finished Jun 29 06:41:35 PM PDT 24
Peak memory 201572 kb
Host smart-8645c7af-16d3-4f6d-9c5d-1f51f6a305b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694713232 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1694713232
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1246568346
Short name T904
Test name
Test status
Simulation time 413400268 ps
CPU time 0.99 seconds
Started Jun 29 06:41:37 PM PDT 24
Finished Jun 29 06:41:39 PM PDT 24
Peak memory 201492 kb
Host smart-d70a7aa0-9d76-40a8-9ee8-1b712e766e27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246568346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1246568346
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1644473226
Short name T826
Test name
Test status
Simulation time 546837052 ps
CPU time 0.71 seconds
Started Jun 29 06:41:42 PM PDT 24
Finished Jun 29 06:41:43 PM PDT 24
Peak memory 201440 kb
Host smart-1b3016fe-e9b1-4321-8b8a-7069f28f3124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644473226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1644473226
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2432320703
Short name T121
Test name
Test status
Simulation time 4033133371 ps
CPU time 13.39 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:42:06 PM PDT 24
Peak memory 201888 kb
Host smart-f31e73e3-e98d-4124-b555-196ac62aa084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432320703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2432320703
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1718607208
Short name T890
Test name
Test status
Simulation time 4422495522 ps
CPU time 2.87 seconds
Started Jun 29 06:41:34 PM PDT 24
Finished Jun 29 06:41:37 PM PDT 24
Peak memory 201864 kb
Host smart-59ac0163-5693-41dc-aa11-5febcc29a13a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718607208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1718607208
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.190344124
Short name T843
Test name
Test status
Simulation time 375454105 ps
CPU time 1.37 seconds
Started Jun 29 06:41:38 PM PDT 24
Finished Jun 29 06:41:40 PM PDT 24
Peak memory 201576 kb
Host smart-fb23f1fd-e367-4beb-b83a-d2c89b57c2be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190344124 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.190344124
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1670500534
Short name T810
Test name
Test status
Simulation time 485902514 ps
CPU time 0.99 seconds
Started Jun 29 06:41:40 PM PDT 24
Finished Jun 29 06:41:42 PM PDT 24
Peak memory 201528 kb
Host smart-5cee2e49-c3cb-4d72-925a-0ada1f8e3edb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670500534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1670500534
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.560840967
Short name T815
Test name
Test status
Simulation time 517139650 ps
CPU time 1.94 seconds
Started Jun 29 06:41:31 PM PDT 24
Finished Jun 29 06:41:33 PM PDT 24
Peak memory 201440 kb
Host smart-76fe97da-c793-43ca-9e5d-cc0740b4b93f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560840967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.560840967
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.74143910
Short name T60
Test name
Test status
Simulation time 2309790681 ps
CPU time 2.19 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:41:58 PM PDT 24
Peak memory 201640 kb
Host smart-8d0e495a-710c-4eb7-95cc-cbaaef2988ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74143910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctr
l_same_csr_outstanding.74143910
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3091970830
Short name T914
Test name
Test status
Simulation time 553241617 ps
CPU time 3.14 seconds
Started Jun 29 06:41:37 PM PDT 24
Finished Jun 29 06:41:40 PM PDT 24
Peak memory 201796 kb
Host smart-a5c9c98e-5490-41e3-b070-3ac26b4cedca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091970830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3091970830
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.604718829
Short name T883
Test name
Test status
Simulation time 8289249745 ps
CPU time 12.9 seconds
Started Jun 29 06:41:18 PM PDT 24
Finished Jun 29 06:41:31 PM PDT 24
Peak memory 201836 kb
Host smart-93835e4f-e706-42e1-a037-d0857e3d84b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604718829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.604718829
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4006120100
Short name T859
Test name
Test status
Simulation time 621907362 ps
CPU time 1.41 seconds
Started Jun 29 06:41:42 PM PDT 24
Finished Jun 29 06:41:44 PM PDT 24
Peak memory 201576 kb
Host smart-c33a3b54-b991-4f4f-b1f0-898a21f23501
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006120100 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.4006120100
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.678130557
Short name T901
Test name
Test status
Simulation time 464960051 ps
CPU time 1.03 seconds
Started Jun 29 06:41:35 PM PDT 24
Finished Jun 29 06:41:37 PM PDT 24
Peak memory 201472 kb
Host smart-ab408542-e04d-4936-be3e-842f56a1c6ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678130557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.678130557
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3529026623
Short name T902
Test name
Test status
Simulation time 433240594 ps
CPU time 1.68 seconds
Started Jun 29 06:41:31 PM PDT 24
Finished Jun 29 06:41:33 PM PDT 24
Peak memory 201440 kb
Host smart-19a1e0d9-1bd1-4588-9440-819760adbf99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529026623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3529026623
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.691310894
Short name T856
Test name
Test status
Simulation time 2815237824 ps
CPU time 2.41 seconds
Started Jun 29 06:41:40 PM PDT 24
Finished Jun 29 06:41:43 PM PDT 24
Peak memory 201756 kb
Host smart-3cdd7c1e-4454-46ec-a43c-f17e5acf3815
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691310894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.691310894
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.4176851725
Short name T852
Test name
Test status
Simulation time 422547681 ps
CPU time 3.22 seconds
Started Jun 29 06:41:35 PM PDT 24
Finished Jun 29 06:41:39 PM PDT 24
Peak memory 201720 kb
Host smart-488b1e74-57e8-4428-b616-92868d53bf3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176851725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.4176851725
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2373145557
Short name T63
Test name
Test status
Simulation time 4592238645 ps
CPU time 5.01 seconds
Started Jun 29 06:41:33 PM PDT 24
Finished Jun 29 06:41:38 PM PDT 24
Peak memory 201868 kb
Host smart-ed9f4220-f640-4333-8098-4075d43dc49b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373145557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2373145557
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2998423423
Short name T92
Test name
Test status
Simulation time 317371030 ps
CPU time 1.61 seconds
Started Jun 29 06:41:43 PM PDT 24
Finished Jun 29 06:41:46 PM PDT 24
Peak memory 201572 kb
Host smart-d23f6202-92b4-491c-b34f-e024e669145b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998423423 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2998423423
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3425077793
Short name T124
Test name
Test status
Simulation time 523398904 ps
CPU time 1.98 seconds
Started Jun 29 06:41:31 PM PDT 24
Finished Jun 29 06:41:33 PM PDT 24
Peak memory 201516 kb
Host smart-478ccc80-ce5e-40e5-85fa-d49774e6b8c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425077793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3425077793
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.472193690
Short name T895
Test name
Test status
Simulation time 368761011 ps
CPU time 1.06 seconds
Started Jun 29 06:41:58 PM PDT 24
Finished Jun 29 06:42:00 PM PDT 24
Peak memory 201444 kb
Host smart-8896eb99-44b9-413a-a9fb-26ef4d40d12b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472193690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.472193690
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2596275607
Short name T872
Test name
Test status
Simulation time 2134847683 ps
CPU time 2.03 seconds
Started Jun 29 06:41:34 PM PDT 24
Finished Jun 29 06:41:36 PM PDT 24
Peak memory 201528 kb
Host smart-e900db36-94a0-4e78-99d0-48825f68c6a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596275607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2596275607
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3303801913
Short name T868
Test name
Test status
Simulation time 462570925 ps
CPU time 2.24 seconds
Started Jun 29 06:41:34 PM PDT 24
Finished Jun 29 06:41:36 PM PDT 24
Peak memory 218128 kb
Host smart-fcc0f6bd-931d-4d67-88dc-70339c263875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303801913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3303801913
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1924593123
Short name T858
Test name
Test status
Simulation time 8232342939 ps
CPU time 3.81 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:41:50 PM PDT 24
Peak memory 201800 kb
Host smart-8272b5a9-e11a-4b50-8ee5-af5336e8cf0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924593123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1924593123
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1615734250
Short name T540
Test name
Test status
Simulation time 461138162 ps
CPU time 1.74 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:41:57 PM PDT 24
Peak memory 201628 kb
Host smart-290137ce-01a3-412f-9235-0d95dacf2c08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615734250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1615734250
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1555580626
Short name T751
Test name
Test status
Simulation time 354214649185 ps
CPU time 838.28 seconds
Started Jun 29 06:41:44 PM PDT 24
Finished Jun 29 06:55:43 PM PDT 24
Peak memory 201868 kb
Host smart-89066637-c59e-40b8-a281-9e22c388f4a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555580626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1555580626
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1208092570
Short name T227
Test name
Test status
Simulation time 491213428718 ps
CPU time 1064.14 seconds
Started Jun 29 06:42:01 PM PDT 24
Finished Jun 29 06:59:46 PM PDT 24
Peak memory 201908 kb
Host smart-b89ccdd0-1c1f-4eed-af8e-0092d373029a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208092570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1208092570
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.4166610589
Short name T652
Test name
Test status
Simulation time 491956301423 ps
CPU time 1068.58 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:59:35 PM PDT 24
Peak memory 201860 kb
Host smart-653fdc9a-b7d5-4561-8f1c-bb923cb6b86d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166610589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.4166610589
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2325126290
Short name T641
Test name
Test status
Simulation time 609583341892 ps
CPU time 241.58 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:45:59 PM PDT 24
Peak memory 201832 kb
Host smart-d209a9c9-b4ce-4625-ab46-1b50b9d0fc4d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325126290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2325126290
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2399430854
Short name T221
Test name
Test status
Simulation time 80510030215 ps
CPU time 429.11 seconds
Started Jun 29 06:42:04 PM PDT 24
Finished Jun 29 06:49:19 PM PDT 24
Peak memory 202416 kb
Host smart-46d1527a-82df-44b1-bcbf-170bda7f0a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399430854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2399430854
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.287193922
Short name T95
Test name
Test status
Simulation time 34815385715 ps
CPU time 42.98 seconds
Started Jun 29 06:42:00 PM PDT 24
Finished Jun 29 06:42:43 PM PDT 24
Peak memory 201668 kb
Host smart-1b745c7f-2614-47fc-bec2-168393296705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287193922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.287193922
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3502244804
Short name T632
Test name
Test status
Simulation time 2951228386 ps
CPU time 7.48 seconds
Started Jun 29 06:42:12 PM PDT 24
Finished Jun 29 06:42:20 PM PDT 24
Peak memory 201684 kb
Host smart-0269e2db-f15d-4a77-b1c8-666165e5598f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502244804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3502244804
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3698793724
Short name T704
Test name
Test status
Simulation time 5707115961 ps
CPU time 7.2 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:41:55 PM PDT 24
Peak memory 201684 kb
Host smart-f78d5d4f-8c66-4c22-9245-ba3f031deb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698793724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3698793724
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2241921437
Short name T643
Test name
Test status
Simulation time 168251302315 ps
CPU time 407.57 seconds
Started Jun 29 06:41:48 PM PDT 24
Finished Jun 29 06:48:36 PM PDT 24
Peak memory 201868 kb
Host smart-c2310be7-d00f-4f64-ba2b-66c5493e0e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241921437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2241921437
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1754045810
Short name T731
Test name
Test status
Simulation time 23787688119 ps
CPU time 72.71 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:43:13 PM PDT 24
Peak memory 210560 kb
Host smart-b23bc457-6cef-4cc1-90b6-69bac26127b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754045810 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1754045810
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.4075652757
Short name T492
Test name
Test status
Simulation time 406532356 ps
CPU time 0.76 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:41:49 PM PDT 24
Peak memory 201628 kb
Host smart-c6a44f9c-9300-4424-98ca-830c78c6530b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075652757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.4075652757
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2339711322
Short name T159
Test name
Test status
Simulation time 163650738076 ps
CPU time 100.13 seconds
Started Jun 29 06:41:42 PM PDT 24
Finished Jun 29 06:43:23 PM PDT 24
Peak memory 201892 kb
Host smart-ad35dbec-30d1-4214-806e-b49f14657325
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339711322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2339711322
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.4134603413
Short name T238
Test name
Test status
Simulation time 523148017212 ps
CPU time 641.9 seconds
Started Jun 29 06:41:56 PM PDT 24
Finished Jun 29 06:52:41 PM PDT 24
Peak memory 201908 kb
Host smart-5cab59a4-e39b-4757-a1ca-e39ab74fd0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134603413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.4134603413
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.264232966
Short name T135
Test name
Test status
Simulation time 326481667308 ps
CPU time 205.39 seconds
Started Jun 29 06:41:58 PM PDT 24
Finished Jun 29 06:45:25 PM PDT 24
Peak memory 201888 kb
Host smart-b4a86713-7504-4531-b4ee-f49b4c37d772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264232966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.264232966
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3016093064
Short name T385
Test name
Test status
Simulation time 332625788975 ps
CPU time 703.44 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:53:38 PM PDT 24
Peak memory 201864 kb
Host smart-ffc0dab4-ebd4-4d5f-8fa7-b04c16fd2f99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016093064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3016093064
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3731148389
Short name T292
Test name
Test status
Simulation time 491396751295 ps
CPU time 311.34 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:47:11 PM PDT 24
Peak memory 201948 kb
Host smart-4cf0b66c-7f2e-48d1-852b-5059e6e61982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731148389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3731148389
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3046961120
Short name T706
Test name
Test status
Simulation time 489581994511 ps
CPU time 600.4 seconds
Started Jun 29 06:41:44 PM PDT 24
Finished Jun 29 06:51:45 PM PDT 24
Peak memory 201820 kb
Host smart-68a0957c-ab51-4d7d-b19c-97eb9f3ca63d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046961120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3046961120
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3384012422
Short name T552
Test name
Test status
Simulation time 171040335450 ps
CPU time 100.34 seconds
Started Jun 29 06:41:58 PM PDT 24
Finished Jun 29 06:43:40 PM PDT 24
Peak memory 201884 kb
Host smart-4cf7bdc9-8c32-4392-8f55-96c60d190ca7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384012422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3384012422
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2395297374
Short name T762
Test name
Test status
Simulation time 196611613011 ps
CPU time 117.84 seconds
Started Jun 29 06:42:02 PM PDT 24
Finished Jun 29 06:44:00 PM PDT 24
Peak memory 201860 kb
Host smart-5d07595f-0eda-4d59-8142-6f8ff9911dc5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395297374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2395297374
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2641809862
Short name T352
Test name
Test status
Simulation time 126320322874 ps
CPU time 480.56 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:49:47 PM PDT 24
Peak memory 202148 kb
Host smart-6ac3d225-4a8e-4520-8eac-bde50ade5e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641809862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2641809862
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2040291403
Short name T770
Test name
Test status
Simulation time 34445419043 ps
CPU time 69.82 seconds
Started Jun 29 06:41:50 PM PDT 24
Finished Jun 29 06:43:00 PM PDT 24
Peak memory 201668 kb
Host smart-d00b8e52-973d-4112-a1a9-3e1e24b6d8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040291403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2040291403
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3707573841
Short name T607
Test name
Test status
Simulation time 4430164363 ps
CPU time 10.06 seconds
Started Jun 29 06:41:45 PM PDT 24
Finished Jun 29 06:41:56 PM PDT 24
Peak memory 201628 kb
Host smart-4e5840b5-be53-4f4c-aef4-a91955a318b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707573841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3707573841
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2382537922
Short name T81
Test name
Test status
Simulation time 4188413332 ps
CPU time 5.31 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:42:04 PM PDT 24
Peak memory 217092 kb
Host smart-164b03eb-99e9-474d-943d-ccf10b4ac42b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382537922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2382537922
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.621908675
Short name T458
Test name
Test status
Simulation time 5854749722 ps
CPU time 7.3 seconds
Started Jun 29 06:41:43 PM PDT 24
Finished Jun 29 06:41:50 PM PDT 24
Peak memory 201688 kb
Host smart-0fe3498e-7929-4790-b3ef-009a8d264bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621908675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.621908675
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.4286733857
Short name T791
Test name
Test status
Simulation time 389162144656 ps
CPU time 1217.45 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 07:02:16 PM PDT 24
Peak memory 218524 kb
Host smart-8a7a5c48-e5bf-480e-97ab-a9c33760e98e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286733857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
4286733857
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1210797036
Short name T22
Test name
Test status
Simulation time 146054735678 ps
CPU time 156.4 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:44:25 PM PDT 24
Peak memory 210576 kb
Host smart-7ce51520-720c-41a0-be1f-f4366a2e57a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210797036 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1210797036
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4097382035
Short name T487
Test name
Test status
Simulation time 324780707808 ps
CPU time 250.13 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:46:14 PM PDT 24
Peak memory 201812 kb
Host smart-352f51f5-06f6-4089-a1df-e2abd2aba013
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097382035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.4097382035
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3730658265
Short name T776
Test name
Test status
Simulation time 322245648842 ps
CPU time 347.65 seconds
Started Jun 29 06:41:56 PM PDT 24
Finished Jun 29 06:47:46 PM PDT 24
Peak memory 201888 kb
Host smart-30479bca-d4a1-4ef4-8c5a-eebe404cd198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730658265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3730658265
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.4056457746
Short name T688
Test name
Test status
Simulation time 333371022663 ps
CPU time 199.48 seconds
Started Jun 29 06:41:52 PM PDT 24
Finished Jun 29 06:45:13 PM PDT 24
Peak memory 201908 kb
Host smart-c90ae976-6998-4fc4-bbaf-189ba72c51bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056457746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.4056457746
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1983878825
Short name T683
Test name
Test status
Simulation time 401090396127 ps
CPU time 893.53 seconds
Started Jun 29 06:42:05 PM PDT 24
Finished Jun 29 06:56:59 PM PDT 24
Peak memory 201868 kb
Host smart-39eb948a-67b7-4435-8252-527c30c1e1d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983878825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1983878825
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.258401024
Short name T219
Test name
Test status
Simulation time 114224520339 ps
CPU time 599.68 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:51:57 PM PDT 24
Peak memory 202260 kb
Host smart-0d87e158-c08f-4b6a-b539-7835d9bc8f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258401024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.258401024
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.599106600
Short name T525
Test name
Test status
Simulation time 39448842792 ps
CPU time 90.96 seconds
Started Jun 29 06:41:50 PM PDT 24
Finished Jun 29 06:43:21 PM PDT 24
Peak memory 201680 kb
Host smart-32f6f102-db51-421e-9162-434f84f4a7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599106600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.599106600
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3961836650
Short name T478
Test name
Test status
Simulation time 3285651786 ps
CPU time 2.53 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:42:02 PM PDT 24
Peak memory 201532 kb
Host smart-cd42f099-753b-4b3d-88a0-96d54c7e4ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961836650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3961836650
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1012427003
Short name T610
Test name
Test status
Simulation time 6009151376 ps
CPU time 4.68 seconds
Started Jun 29 06:42:03 PM PDT 24
Finished Jun 29 06:42:08 PM PDT 24
Peak memory 201676 kb
Host smart-547f6987-32e3-4b6a-91a3-52d55a848093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012427003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1012427003
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3067662804
Short name T339
Test name
Test status
Simulation time 234876237785 ps
CPU time 748.32 seconds
Started Jun 29 06:42:11 PM PDT 24
Finished Jun 29 06:54:40 PM PDT 24
Peak memory 218828 kb
Host smart-8b2ac165-cbd7-4e93-bf85-588e1e3bceae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067662804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3067662804
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1748041603
Short name T103
Test name
Test status
Simulation time 52588532503 ps
CPU time 106.31 seconds
Started Jun 29 06:41:48 PM PDT 24
Finished Jun 29 06:43:35 PM PDT 24
Peak memory 210268 kb
Host smart-8d214ef1-785f-43f2-b24c-a66daf584197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748041603 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1748041603
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2346637365
Short name T486
Test name
Test status
Simulation time 360293634 ps
CPU time 0.73 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:41:58 PM PDT 24
Peak memory 201628 kb
Host smart-8562c430-6688-479b-8471-d36a10ff0a45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346637365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2346637365
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1748248425
Short name T277
Test name
Test status
Simulation time 504568308617 ps
CPU time 1122.81 seconds
Started Jun 29 06:42:14 PM PDT 24
Finished Jun 29 07:00:58 PM PDT 24
Peak memory 201868 kb
Host smart-74de1a2f-a771-492c-baa7-b4904db4ded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748248425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1748248425
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3293689917
Short name T344
Test name
Test status
Simulation time 487987264756 ps
CPU time 1036.61 seconds
Started Jun 29 06:42:05 PM PDT 24
Finished Jun 29 06:59:22 PM PDT 24
Peak memory 201880 kb
Host smart-e9a65339-3d37-4ad0-b333-210427db2667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293689917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3293689917
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3015683005
Short name T782
Test name
Test status
Simulation time 161782425149 ps
CPU time 336.5 seconds
Started Jun 29 06:42:15 PM PDT 24
Finished Jun 29 06:47:52 PM PDT 24
Peak memory 201852 kb
Host smart-77e054b2-c26e-4434-8e33-030588f2ab10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015683005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3015683005
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3788737581
Short name T568
Test name
Test status
Simulation time 331348658659 ps
CPU time 190.28 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:45:06 PM PDT 24
Peak memory 201900 kb
Host smart-190983a7-8247-4e81-b983-bff384ac7d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788737581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3788737581
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2744242506
Short name T562
Test name
Test status
Simulation time 166739759211 ps
CPU time 352.61 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:47:49 PM PDT 24
Peak memory 201752 kb
Host smart-49c925b6-9963-402f-b1af-a5da170434f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744242506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2744242506
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.93630946
Short name T609
Test name
Test status
Simulation time 540013533291 ps
CPU time 1153.28 seconds
Started Jun 29 06:42:22 PM PDT 24
Finished Jun 29 07:01:35 PM PDT 24
Peak memory 201888 kb
Host smart-a8a223b7-8ea7-49f3-a809-7aa1e49b2711
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93630946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_w
akeup.93630946
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.4101314873
Short name T192
Test name
Test status
Simulation time 608291847419 ps
CPU time 353.02 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:47:46 PM PDT 24
Peak memory 201844 kb
Host smart-4ec4b672-09f9-4c22-8a2f-b1fc64f2dd93
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101314873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.4101314873
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.200164319
Short name T86
Test name
Test status
Simulation time 58801563159 ps
CPU time 260.57 seconds
Started Jun 29 06:42:29 PM PDT 24
Finished Jun 29 06:46:50 PM PDT 24
Peak memory 202472 kb
Host smart-d02c30d8-b816-41b4-a42f-df42df89e5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200164319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.200164319
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.954660561
Short name T774
Test name
Test status
Simulation time 24961333898 ps
CPU time 53.47 seconds
Started Jun 29 06:42:03 PM PDT 24
Finished Jun 29 06:42:57 PM PDT 24
Peak memory 201652 kb
Host smart-62d4844b-f836-4d7d-9c50-ac03e2d5de22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954660561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.954660561
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3481101946
Short name T640
Test name
Test status
Simulation time 3403423367 ps
CPU time 1.41 seconds
Started Jun 29 06:42:23 PM PDT 24
Finished Jun 29 06:42:24 PM PDT 24
Peak memory 201652 kb
Host smart-5fd234ab-e8ee-48bb-81a5-fc180a01993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481101946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3481101946
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2133354934
Short name T434
Test name
Test status
Simulation time 5841590572 ps
CPU time 3.94 seconds
Started Jun 29 06:42:16 PM PDT 24
Finished Jun 29 06:42:21 PM PDT 24
Peak memory 201916 kb
Host smart-0040f4e3-9487-4f5f-ae52-3be06d24075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133354934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2133354934
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.4218457410
Short name T32
Test name
Test status
Simulation time 172307730162 ps
CPU time 392.56 seconds
Started Jun 29 06:42:18 PM PDT 24
Finished Jun 29 06:48:50 PM PDT 24
Peak memory 201848 kb
Host smart-aaa868e4-4eee-463e-bf0a-c3dfca751a4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218457410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.4218457410
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.794569996
Short name T444
Test name
Test status
Simulation time 13786311827 ps
CPU time 32.37 seconds
Started Jun 29 06:42:23 PM PDT 24
Finished Jun 29 06:42:56 PM PDT 24
Peak memory 210204 kb
Host smart-3d742887-12eb-4474-a9a2-87dd2361bc14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794569996 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.794569996
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.4257863691
Short name T650
Test name
Test status
Simulation time 380728950 ps
CPU time 0.87 seconds
Started Jun 29 06:42:04 PM PDT 24
Finished Jun 29 06:42:06 PM PDT 24
Peak memory 201616 kb
Host smart-b478ee85-886d-4753-b970-704385c6ba66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257863691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.4257863691
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1212181223
Short name T712
Test name
Test status
Simulation time 326865719505 ps
CPU time 744.23 seconds
Started Jun 29 06:42:43 PM PDT 24
Finished Jun 29 06:55:09 PM PDT 24
Peak memory 201936 kb
Host smart-be19411d-5974-4dd0-9b3b-191e739cc95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212181223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1212181223
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.367761161
Short name T722
Test name
Test status
Simulation time 487288215808 ps
CPU time 556.23 seconds
Started Jun 29 06:41:56 PM PDT 24
Finished Jun 29 06:51:15 PM PDT 24
Peak memory 201848 kb
Host smart-4b5857ae-1935-4406-8cac-a048b4abc1e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=367761161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.367761161
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2114622643
Short name T163
Test name
Test status
Simulation time 161463144322 ps
CPU time 350.19 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:47:47 PM PDT 24
Peak memory 201928 kb
Host smart-6a081d42-c2c0-4fb8-833b-915225e84629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114622643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2114622643
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3371378697
Short name T780
Test name
Test status
Simulation time 329280472670 ps
CPU time 53.79 seconds
Started Jun 29 06:42:22 PM PDT 24
Finished Jun 29 06:43:16 PM PDT 24
Peak memory 201848 kb
Host smart-59a4ae6f-9277-423c-ade7-df384ce32014
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371378697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3371378697
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3293888721
Short name T303
Test name
Test status
Simulation time 489137832104 ps
CPU time 242.47 seconds
Started Jun 29 06:41:52 PM PDT 24
Finished Jun 29 06:45:55 PM PDT 24
Peak memory 201840 kb
Host smart-6f1b29a1-7613-43c8-8497-bf6fe851744b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293888721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3293888721
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1948568175
Short name T125
Test name
Test status
Simulation time 406938885769 ps
CPU time 53.81 seconds
Started Jun 29 06:42:12 PM PDT 24
Finished Jun 29 06:43:06 PM PDT 24
Peak memory 202056 kb
Host smart-b4f1d7e9-94b4-4999-afe8-517e0dbc1a1e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948568175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1948568175
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.429380033
Short name T212
Test name
Test status
Simulation time 109139421908 ps
CPU time 385.13 seconds
Started Jun 29 06:42:07 PM PDT 24
Finished Jun 29 06:48:32 PM PDT 24
Peak memory 202248 kb
Host smart-62bcd9b8-59d4-437c-a968-a7edfb44a88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429380033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.429380033
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4094904125
Short name T753
Test name
Test status
Simulation time 25336846329 ps
CPU time 52.6 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:42:49 PM PDT 24
Peak memory 201672 kb
Host smart-f01abae1-a1a6-417f-879e-c2b82547d7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094904125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4094904125
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1872523783
Short name T738
Test name
Test status
Simulation time 4351091807 ps
CPU time 5.49 seconds
Started Jun 29 06:42:04 PM PDT 24
Finished Jun 29 06:42:09 PM PDT 24
Peak memory 201672 kb
Host smart-e1067660-297b-4f9d-97d1-bd1c93d09b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872523783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1872523783
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.4076964147
Short name T416
Test name
Test status
Simulation time 5724607801 ps
CPU time 12.75 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:42:10 PM PDT 24
Peak memory 201672 kb
Host smart-d2255f5b-8f88-4963-916f-cd6fb185726e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076964147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.4076964147
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1707280431
Short name T668
Test name
Test status
Simulation time 207318785672 ps
CPU time 451.86 seconds
Started Jun 29 06:42:27 PM PDT 24
Finished Jun 29 06:50:00 PM PDT 24
Peak memory 201908 kb
Host smart-51752607-893d-4fb1-9c43-37438eb95f4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707280431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1707280431
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1616182186
Short name T38
Test name
Test status
Simulation time 58815523766 ps
CPU time 130.68 seconds
Started Jun 29 06:42:30 PM PDT 24
Finished Jun 29 06:44:42 PM PDT 24
Peak memory 210496 kb
Host smart-b0b55fe1-2fb0-4881-b9a5-5c38c8541d95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616182186 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1616182186
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2032707753
Short name T406
Test name
Test status
Simulation time 290424870 ps
CPU time 1.3 seconds
Started Jun 29 06:41:56 PM PDT 24
Finished Jun 29 06:41:59 PM PDT 24
Peak memory 201628 kb
Host smart-65cb1080-2349-4cbc-b11c-ae45cc20db2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032707753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2032707753
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1745536516
Short name T278
Test name
Test status
Simulation time 205168181818 ps
CPU time 121.23 seconds
Started Jun 29 06:42:01 PM PDT 24
Finished Jun 29 06:44:03 PM PDT 24
Peak memory 201876 kb
Host smart-a8aaaa8a-5026-439a-a09b-0227ce0d016a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745536516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1745536516
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2575324904
Short name T340
Test name
Test status
Simulation time 323007967551 ps
CPU time 187.35 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:45:33 PM PDT 24
Peak memory 201900 kb
Host smart-dd3324c4-2f2e-4e19-829b-30c4d7f904d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575324904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2575324904
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1515821114
Short name T233
Test name
Test status
Simulation time 329204634426 ps
CPU time 411.72 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:48:50 PM PDT 24
Peak memory 201852 kb
Host smart-1bd92cb6-962f-462c-b56a-92a34e45385c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515821114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1515821114
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2727434374
Short name T132
Test name
Test status
Simulation time 328620700972 ps
CPU time 87.14 seconds
Started Jun 29 06:42:04 PM PDT 24
Finished Jun 29 06:43:32 PM PDT 24
Peak memory 201928 kb
Host smart-13c01849-3a07-4d0b-a4f3-c123466a2dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727434374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2727434374
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1190097542
Short name T657
Test name
Test status
Simulation time 485158528090 ps
CPU time 288.31 seconds
Started Jun 29 06:42:01 PM PDT 24
Finished Jun 29 06:46:50 PM PDT 24
Peak memory 201840 kb
Host smart-9eae959f-3d93-4f92-8d0f-c8bc45988a97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190097542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1190097542
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2873537847
Short name T248
Test name
Test status
Simulation time 242887361189 ps
CPU time 265.08 seconds
Started Jun 29 06:42:23 PM PDT 24
Finished Jun 29 06:46:48 PM PDT 24
Peak memory 201852 kb
Host smart-8651ffa1-e91f-442b-8705-eb0ccb615941
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873537847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2873537847
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.550210264
Short name T464
Test name
Test status
Simulation time 611790119146 ps
CPU time 1340.34 seconds
Started Jun 29 06:42:27 PM PDT 24
Finished Jun 29 07:04:49 PM PDT 24
Peak memory 201848 kb
Host smart-1a1cfd89-72fe-4ad9-9e17-8d85710b70cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550210264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.550210264
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3334909414
Short name T603
Test name
Test status
Simulation time 108151384499 ps
CPU time 572.44 seconds
Started Jun 29 06:42:07 PM PDT 24
Finished Jun 29 06:51:40 PM PDT 24
Peak memory 202188 kb
Host smart-2cd264eb-9921-4586-b886-2e65099b945f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334909414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3334909414
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2329331798
Short name T393
Test name
Test status
Simulation time 39644874434 ps
CPU time 67.49 seconds
Started Jun 29 06:42:16 PM PDT 24
Finished Jun 29 06:43:24 PM PDT 24
Peak memory 201540 kb
Host smart-86746686-2c38-4770-854e-57fce19b041e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329331798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2329331798
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3530575369
Short name T88
Test name
Test status
Simulation time 4036336781 ps
CPU time 1.16 seconds
Started Jun 29 06:42:15 PM PDT 24
Finished Jun 29 06:42:16 PM PDT 24
Peak memory 201652 kb
Host smart-04dbaad8-b749-40cc-82f9-0ff026892411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530575369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3530575369
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3136429357
Short name T581
Test name
Test status
Simulation time 5729914686 ps
CPU time 14.14 seconds
Started Jun 29 06:42:08 PM PDT 24
Finished Jun 29 06:42:22 PM PDT 24
Peak memory 201676 kb
Host smart-fa2b9c66-c8be-413e-9af9-75becc0862b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136429357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3136429357
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1755928504
Short name T77
Test name
Test status
Simulation time 340481456 ps
CPU time 0.8 seconds
Started Jun 29 06:42:26 PM PDT 24
Finished Jun 29 06:42:27 PM PDT 24
Peak memory 201596 kb
Host smart-8d04764d-a68b-464e-9402-2e5da19f0095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755928504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1755928504
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1332251797
Short name T714
Test name
Test status
Simulation time 356965021723 ps
CPU time 214.66 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:45:33 PM PDT 24
Peak memory 201864 kb
Host smart-7ee42cee-e1aa-4c46-a4a1-a5c2f4eacc8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332251797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1332251797
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3195661051
Short name T282
Test name
Test status
Simulation time 355950976082 ps
CPU time 229.62 seconds
Started Jun 29 06:42:07 PM PDT 24
Finished Jun 29 06:45:56 PM PDT 24
Peak memory 201884 kb
Host smart-0cfb0912-fea1-4525-b41b-a00ee3196fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195661051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3195661051
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.884928677
Short name T705
Test name
Test status
Simulation time 499122886949 ps
CPU time 1169.6 seconds
Started Jun 29 06:42:12 PM PDT 24
Finished Jun 29 07:01:42 PM PDT 24
Peak memory 201848 kb
Host smart-0b722123-a790-4f0f-9239-057fb42397bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=884928677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.884928677
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3518123503
Short name T99
Test name
Test status
Simulation time 166053164681 ps
CPU time 336.69 seconds
Started Jun 29 06:42:07 PM PDT 24
Finished Jun 29 06:47:45 PM PDT 24
Peak memory 201976 kb
Host smart-b1e53656-0405-489e-9bd5-c4b55c743244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518123503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3518123503
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.45239547
Short name T740
Test name
Test status
Simulation time 482334343815 ps
CPU time 197.82 seconds
Started Jun 29 06:42:21 PM PDT 24
Finished Jun 29 06:45:39 PM PDT 24
Peak memory 201884 kb
Host smart-591a3245-b52b-461b-913d-12650b1affaa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=45239547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed
.45239547
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.219373656
Short name T246
Test name
Test status
Simulation time 594610010989 ps
CPU time 1096.17 seconds
Started Jun 29 06:42:22 PM PDT 24
Finished Jun 29 07:00:38 PM PDT 24
Peak memory 201884 kb
Host smart-0c8cec03-1d51-44e8-81f1-b689ae38f709
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219373656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.219373656
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3273674784
Short name T717
Test name
Test status
Simulation time 193893873872 ps
CPU time 42.27 seconds
Started Jun 29 06:42:21 PM PDT 24
Finished Jun 29 06:43:04 PM PDT 24
Peak memory 201924 kb
Host smart-cd25b08b-7d4c-4142-83c2-2b450aa59e25
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273674784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3273674784
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1691854736
Short name T594
Test name
Test status
Simulation time 65372097104 ps
CPU time 260.94 seconds
Started Jun 29 06:42:17 PM PDT 24
Finished Jun 29 06:46:38 PM PDT 24
Peak memory 202256 kb
Host smart-fecbe113-4e46-4508-8c59-68b99c28d5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691854736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1691854736
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1181526914
Short name T197
Test name
Test status
Simulation time 43129533670 ps
CPU time 101.58 seconds
Started Jun 29 06:42:04 PM PDT 24
Finished Jun 29 06:43:46 PM PDT 24
Peak memory 201668 kb
Host smart-27932e52-623b-41b7-8de2-0e2ae002f876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181526914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1181526914
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3484768228
Short name T510
Test name
Test status
Simulation time 3441104437 ps
CPU time 2.62 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:42:28 PM PDT 24
Peak memory 201652 kb
Host smart-667cc398-0840-4e94-96bf-ace1d3b3b096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484768228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3484768228
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.615612484
Short name T471
Test name
Test status
Simulation time 5932744746 ps
CPU time 13.72 seconds
Started Jun 29 06:42:14 PM PDT 24
Finished Jun 29 06:42:28 PM PDT 24
Peak memory 201652 kb
Host smart-cbf38af1-a826-4f90-9e25-dbbdc19a02c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615612484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.615612484
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3024359154
Short name T538
Test name
Test status
Simulation time 337556884334 ps
CPU time 225.98 seconds
Started Jun 29 06:42:16 PM PDT 24
Finished Jun 29 06:46:03 PM PDT 24
Peak memory 201876 kb
Host smart-ab6c7fbf-2181-4ee0-b358-978b84527885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024359154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3024359154
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.407219091
Short name T260
Test name
Test status
Simulation time 22055936264 ps
CPU time 30.5 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:42:55 PM PDT 24
Peak memory 210268 kb
Host smart-bd4fca72-6747-424a-bf84-85e7d673e05d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407219091 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.407219091
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2388151198
Short name T627
Test name
Test status
Simulation time 533510131 ps
CPU time 0.92 seconds
Started Jun 29 06:42:14 PM PDT 24
Finished Jun 29 06:42:15 PM PDT 24
Peak memory 201536 kb
Host smart-64a01659-2201-42ed-938b-47f2f2f32d7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388151198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2388151198
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.252892159
Short name T280
Test name
Test status
Simulation time 162879215709 ps
CPU time 197.21 seconds
Started Jun 29 06:42:19 PM PDT 24
Finished Jun 29 06:45:36 PM PDT 24
Peak memory 201860 kb
Host smart-dfbe8437-cdd5-4190-a25c-d08e755d40af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252892159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.252892159
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1741106091
Short name T271
Test name
Test status
Simulation time 179027830984 ps
CPU time 121.26 seconds
Started Jun 29 06:42:23 PM PDT 24
Finished Jun 29 06:44:24 PM PDT 24
Peak memory 201888 kb
Host smart-68350148-205c-429a-8472-29b78530f86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741106091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1741106091
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2207363108
Short name T154
Test name
Test status
Simulation time 166790271288 ps
CPU time 342.41 seconds
Started Jun 29 06:42:23 PM PDT 24
Finished Jun 29 06:48:06 PM PDT 24
Peak memory 201920 kb
Host smart-1994dbfb-f5e3-4ec6-8f87-042bdd50504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207363108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2207363108
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2194175427
Short name T697
Test name
Test status
Simulation time 331538320364 ps
CPU time 188.75 seconds
Started Jun 29 06:42:19 PM PDT 24
Finished Jun 29 06:45:29 PM PDT 24
Peak memory 201848 kb
Host smart-be73b337-8504-419c-aff0-637cbd969659
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194175427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2194175427
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2256432575
Short name T130
Test name
Test status
Simulation time 501828525318 ps
CPU time 119.09 seconds
Started Jun 29 06:42:20 PM PDT 24
Finished Jun 29 06:44:19 PM PDT 24
Peak memory 201880 kb
Host smart-1d5a4f18-c8e4-4eb0-97f4-d2e12b1b3fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256432575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2256432575
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1102310943
Short name T85
Test name
Test status
Simulation time 495248635420 ps
CPU time 135.66 seconds
Started Jun 29 06:42:20 PM PDT 24
Finished Jun 29 06:44:36 PM PDT 24
Peak memory 201856 kb
Host smart-f0f85091-ef8d-437f-94e8-8ce9158bdbe1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102310943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1102310943
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1367155240
Short name T169
Test name
Test status
Simulation time 610743431120 ps
CPU time 333.78 seconds
Started Jun 29 06:42:19 PM PDT 24
Finished Jun 29 06:47:53 PM PDT 24
Peak memory 201860 kb
Host smart-2c2603b3-c011-4565-857a-9e733ae398a6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367155240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1367155240
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2409400737
Short name T201
Test name
Test status
Simulation time 92682881709 ps
CPU time 335.81 seconds
Started Jun 29 06:42:07 PM PDT 24
Finished Jun 29 06:47:43 PM PDT 24
Peak memory 202252 kb
Host smart-6f002f53-0b91-4c82-a225-c9040b64d6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409400737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2409400737
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.514733765
Short name T512
Test name
Test status
Simulation time 25155629607 ps
CPU time 14.09 seconds
Started Jun 29 06:42:29 PM PDT 24
Finished Jun 29 06:42:43 PM PDT 24
Peak memory 201676 kb
Host smart-bc0343d2-c109-4f71-8a02-c0cd742dcab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514733765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.514733765
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.39288812
Short name T134
Test name
Test status
Simulation time 3731508874 ps
CPU time 1.71 seconds
Started Jun 29 06:42:36 PM PDT 24
Finished Jun 29 06:42:38 PM PDT 24
Peak memory 201660 kb
Host smart-bcfac715-377a-4980-9285-63de109e6845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39288812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.39288812
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3001331093
Short name T653
Test name
Test status
Simulation time 5996553089 ps
CPU time 13.93 seconds
Started Jun 29 06:42:15 PM PDT 24
Finished Jun 29 06:42:30 PM PDT 24
Peak memory 201672 kb
Host smart-21a5a1e5-8f59-4c52-b1d3-282ef7339693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001331093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3001331093
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3478571632
Short name T331
Test name
Test status
Simulation time 504127519640 ps
CPU time 260.91 seconds
Started Jun 29 06:42:20 PM PDT 24
Finished Jun 29 06:46:42 PM PDT 24
Peak memory 201880 kb
Host smart-a9ad42bf-6806-470c-88d3-84f722429dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478571632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3478571632
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2441688491
Short name T745
Test name
Test status
Simulation time 187506750666 ps
CPU time 66.32 seconds
Started Jun 29 06:42:19 PM PDT 24
Finished Jun 29 06:43:25 PM PDT 24
Peak memory 210200 kb
Host smart-9786aecb-ea8e-4cc6-beac-ff909a03868e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441688491 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2441688491
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2138440780
Short name T595
Test name
Test status
Simulation time 364479627 ps
CPU time 1.43 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:42:27 PM PDT 24
Peak memory 201612 kb
Host smart-f600510b-479d-4310-9d12-c738e692cf17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138440780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2138440780
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3715922147
Short name T711
Test name
Test status
Simulation time 160703052043 ps
CPU time 379.95 seconds
Started Jun 29 06:42:32 PM PDT 24
Finished Jun 29 06:48:53 PM PDT 24
Peak memory 201872 kb
Host smart-252ceb60-f3e4-45d5-9a9a-e37b2b8e8bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715922147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3715922147
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.49079374
Short name T372
Test name
Test status
Simulation time 331021614259 ps
CPU time 199.35 seconds
Started Jun 29 06:42:23 PM PDT 24
Finished Jun 29 06:45:42 PM PDT 24
Peak memory 201848 kb
Host smart-d1a18f0d-8e54-4cca-a151-d9853b11559c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=49079374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt
_fixed.49079374
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.162063460
Short name T160
Test name
Test status
Simulation time 331126790077 ps
CPU time 198.11 seconds
Started Jun 29 06:42:20 PM PDT 24
Finished Jun 29 06:45:39 PM PDT 24
Peak memory 201876 kb
Host smart-68dca2e5-1aab-49e0-a070-f68ea475dcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162063460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.162063460
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3798360528
Short name T692
Test name
Test status
Simulation time 333099269566 ps
CPU time 186.2 seconds
Started Jun 29 06:42:21 PM PDT 24
Finished Jun 29 06:45:28 PM PDT 24
Peak memory 201852 kb
Host smart-00304948-21a0-4d05-84aa-5c05a69df302
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798360528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3798360528
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.169909060
Short name T148
Test name
Test status
Simulation time 549663983623 ps
CPU time 373.64 seconds
Started Jun 29 06:42:19 PM PDT 24
Finished Jun 29 06:48:34 PM PDT 24
Peak memory 201892 kb
Host smart-50c6334b-2f1a-4a2a-b9b9-3a5dea0257d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169909060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.169909060
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1453352607
Short name T379
Test name
Test status
Simulation time 571598979827 ps
CPU time 1414.28 seconds
Started Jun 29 06:42:21 PM PDT 24
Finished Jun 29 07:05:56 PM PDT 24
Peak memory 201840 kb
Host smart-2c8098b0-7425-43aa-83b0-5b810a7d6afc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453352607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1453352607
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3805362265
Short name T744
Test name
Test status
Simulation time 81663895931 ps
CPU time 246.55 seconds
Started Jun 29 06:42:29 PM PDT 24
Finished Jun 29 06:46:37 PM PDT 24
Peak memory 202184 kb
Host smart-191ff300-0893-43dc-9d20-f8794da923d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805362265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3805362265
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.977376229
Short name T161
Test name
Test status
Simulation time 41954553776 ps
CPU time 25.82 seconds
Started Jun 29 06:42:29 PM PDT 24
Finished Jun 29 06:42:55 PM PDT 24
Peak memory 201676 kb
Host smart-62cf57b7-f897-4b7d-a966-441dd9ace92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977376229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.977376229
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2987917457
Short name T549
Test name
Test status
Simulation time 2837058760 ps
CPU time 2.1 seconds
Started Jun 29 06:42:35 PM PDT 24
Finished Jun 29 06:42:38 PM PDT 24
Peak memory 201680 kb
Host smart-bc2d40ee-585d-4051-b379-d1d8bd043b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987917457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2987917457
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3341694505
Short name T686
Test name
Test status
Simulation time 6009951295 ps
CPU time 4.02 seconds
Started Jun 29 06:42:15 PM PDT 24
Finished Jun 29 06:42:20 PM PDT 24
Peak memory 201660 kb
Host smart-6f90f871-851f-4817-a4f7-a691b6bf2a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341694505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3341694505
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.821507999
Short name T39
Test name
Test status
Simulation time 40603967781 ps
CPU time 96.09 seconds
Started Jun 29 06:42:28 PM PDT 24
Finished Jun 29 06:44:05 PM PDT 24
Peak memory 210244 kb
Host smart-b01c783c-c5d0-473c-a5af-7f8cfb1fe324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821507999 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.821507999
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3504044898
Short name T399
Test name
Test status
Simulation time 499017144 ps
CPU time 1.24 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:42:27 PM PDT 24
Peak memory 201640 kb
Host smart-ebc0bc2a-c122-4711-9fa6-ef5934be4547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504044898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3504044898
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1593422936
Short name T327
Test name
Test status
Simulation time 335086142461 ps
CPU time 701.25 seconds
Started Jun 29 06:42:19 PM PDT 24
Finished Jun 29 06:54:01 PM PDT 24
Peak memory 201880 kb
Host smart-b51af88d-7204-400e-8d76-e54f2cb8908a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593422936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1593422936
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2574392381
Short name T2
Test name
Test status
Simulation time 322844102972 ps
CPU time 765.23 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:55:11 PM PDT 24
Peak memory 201920 kb
Host smart-dd8e7587-53a7-4b28-8212-9f53662bb186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574392381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2574392381
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2362141392
Short name T775
Test name
Test status
Simulation time 486335389958 ps
CPU time 231.39 seconds
Started Jun 29 06:42:28 PM PDT 24
Finished Jun 29 06:46:20 PM PDT 24
Peak memory 201836 kb
Host smart-0b468221-8d35-4771-bc91-13a91701e11b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362141392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2362141392
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3426179128
Short name T152
Test name
Test status
Simulation time 324409101940 ps
CPU time 182.27 seconds
Started Jun 29 06:42:39 PM PDT 24
Finished Jun 29 06:45:42 PM PDT 24
Peak memory 201892 kb
Host smart-bcd61f7c-edec-4e72-afde-fab1be8467a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426179128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3426179128
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3105351838
Short name T661
Test name
Test status
Simulation time 499860287613 ps
CPU time 177.5 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:45:24 PM PDT 24
Peak memory 201852 kb
Host smart-e41656e8-34f2-42ec-9e58-5e4ab97e36d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105351838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3105351838
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2345279575
Short name T737
Test name
Test status
Simulation time 207320776056 ps
CPU time 118.45 seconds
Started Jun 29 06:42:31 PM PDT 24
Finished Jun 29 06:44:30 PM PDT 24
Peak memory 201908 kb
Host smart-80044a0e-1506-46b6-9894-808b410b1222
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345279575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2345279575
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.962306259
Short name T56
Test name
Test status
Simulation time 130869715169 ps
CPU time 689.26 seconds
Started Jun 29 06:42:29 PM PDT 24
Finished Jun 29 06:53:59 PM PDT 24
Peak memory 202232 kb
Host smart-5059d53f-2677-49cd-9f12-4efb3c7390e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962306259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.962306259
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.96271120
Short name T786
Test name
Test status
Simulation time 43900177962 ps
CPU time 21.52 seconds
Started Jun 29 06:42:20 PM PDT 24
Finished Jun 29 06:42:42 PM PDT 24
Peak memory 201636 kb
Host smart-5f531095-857e-41da-9a2b-895baeb7d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96271120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.96271120
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1843343075
Short name T107
Test name
Test status
Simulation time 3527130082 ps
CPU time 8.5 seconds
Started Jun 29 06:42:27 PM PDT 24
Finished Jun 29 06:42:36 PM PDT 24
Peak memory 201668 kb
Host smart-e98579cc-e82d-4872-90dd-c36ba9e44f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843343075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1843343075
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2635103579
Short name T691
Test name
Test status
Simulation time 5632549581 ps
CPU time 3.67 seconds
Started Jun 29 06:42:17 PM PDT 24
Finished Jun 29 06:42:21 PM PDT 24
Peak memory 201680 kb
Host smart-d0435dc0-e9f1-4686-bf2f-bb9c078f6991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635103579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2635103579
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1500119867
Short name T634
Test name
Test status
Simulation time 331450684048 ps
CPU time 186.04 seconds
Started Jun 29 06:42:21 PM PDT 24
Finished Jun 29 06:45:28 PM PDT 24
Peak memory 201868 kb
Host smart-9339c1e7-a1c7-4ed3-bc6b-4116a1d93ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500119867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1500119867
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1224958047
Short name T40
Test name
Test status
Simulation time 105320620215 ps
CPU time 128.8 seconds
Started Jun 29 06:42:21 PM PDT 24
Finished Jun 29 06:44:31 PM PDT 24
Peak memory 210512 kb
Host smart-a488055a-4b30-4172-ac53-29aa258a8ee4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224958047 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1224958047
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3102052446
Short name T523
Test name
Test status
Simulation time 339366192 ps
CPU time 1.35 seconds
Started Jun 29 06:42:23 PM PDT 24
Finished Jun 29 06:42:25 PM PDT 24
Peak memory 201616 kb
Host smart-0b3e8788-f331-4a69-ad81-6587af583206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102052446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3102052446
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2780545406
Short name T272
Test name
Test status
Simulation time 175138637513 ps
CPU time 84.91 seconds
Started Jun 29 06:42:23 PM PDT 24
Finished Jun 29 06:43:48 PM PDT 24
Peak memory 201924 kb
Host smart-4d1fa868-1300-4251-b439-4c9dae82dddb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780545406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2780545406
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.741843407
Short name T671
Test name
Test status
Simulation time 498447631502 ps
CPU time 332.56 seconds
Started Jun 29 06:42:30 PM PDT 24
Finished Jun 29 06:48:03 PM PDT 24
Peak memory 201836 kb
Host smart-dbc2c97e-7f03-4b26-8a0f-065ed3831b47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=741843407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.741843407
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.639938112
Short name T188
Test name
Test status
Simulation time 324518290991 ps
CPU time 178.83 seconds
Started Jun 29 06:42:27 PM PDT 24
Finished Jun 29 06:45:27 PM PDT 24
Peak memory 201944 kb
Host smart-7a2c65e6-78b3-4e66-b108-47135b1bef6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639938112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.639938112
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.238449239
Short name T362
Test name
Test status
Simulation time 317377868195 ps
CPU time 339.84 seconds
Started Jun 29 06:42:22 PM PDT 24
Finished Jun 29 06:48:02 PM PDT 24
Peak memory 201856 kb
Host smart-631c3d35-a878-4721-b488-f5a2b6dcea8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=238449239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.238449239
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.126797099
Short name T158
Test name
Test status
Simulation time 370002596886 ps
CPU time 55.75 seconds
Started Jun 29 06:42:19 PM PDT 24
Finished Jun 29 06:43:15 PM PDT 24
Peak memory 201860 kb
Host smart-d517d0ae-091e-4f57-a8ca-fe7b9dc87a5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126797099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.126797099
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3073015166
Short name T423
Test name
Test status
Simulation time 615483410674 ps
CPU time 1360.57 seconds
Started Jun 29 06:42:20 PM PDT 24
Finished Jun 29 07:05:02 PM PDT 24
Peak memory 201828 kb
Host smart-5ea4e43d-86a6-4b53-8dbc-119aa3c20c3a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073015166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3073015166
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1647384654
Short name T205
Test name
Test status
Simulation time 100026853338 ps
CPU time 311.81 seconds
Started Jun 29 06:42:21 PM PDT 24
Finished Jun 29 06:47:34 PM PDT 24
Peak memory 202228 kb
Host smart-caa07c4f-f915-4b88-afa5-23f33aad769c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647384654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1647384654
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1928397521
Short name T734
Test name
Test status
Simulation time 44684352570 ps
CPU time 26.16 seconds
Started Jun 29 06:42:19 PM PDT 24
Finished Jun 29 06:42:45 PM PDT 24
Peak memory 201664 kb
Host smart-4f8fa888-02e5-4789-a77f-7a81e7c7bb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928397521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1928397521
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.983030259
Short name T519
Test name
Test status
Simulation time 4467053956 ps
CPU time 12.24 seconds
Started Jun 29 06:42:26 PM PDT 24
Finished Jun 29 06:42:39 PM PDT 24
Peak memory 201660 kb
Host smart-dd230f9e-5357-41e3-821e-33255037cae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983030259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.983030259
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.477022413
Short name T366
Test name
Test status
Simulation time 5905601166 ps
CPU time 3.88 seconds
Started Jun 29 06:42:24 PM PDT 24
Finished Jun 29 06:42:28 PM PDT 24
Peak memory 201680 kb
Host smart-9c21d514-0490-4b23-bf1f-428fe6e395cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477022413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.477022413
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1005271987
Short name T247
Test name
Test status
Simulation time 546520822438 ps
CPU time 335.1 seconds
Started Jun 29 06:42:30 PM PDT 24
Finished Jun 29 06:48:06 PM PDT 24
Peak memory 201880 kb
Host smart-37283cf6-37cc-4ebd-9b59-7a3ed242d192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005271987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1005271987
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.536299
Short name T15
Test name
Test status
Simulation time 13225957152 ps
CPU time 10.25 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:42:36 PM PDT 24
Peak memory 210248 kb
Host smart-bd539799-050c-43a8-babd-d54a55e8f6a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536299 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.536299
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3210802305
Short name T455
Test name
Test status
Simulation time 445761321 ps
CPU time 1.62 seconds
Started Jun 29 06:42:31 PM PDT 24
Finished Jun 29 06:42:33 PM PDT 24
Peak memory 201604 kb
Host smart-0abea110-8a2d-437a-9f9e-8c53b1865e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210802305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3210802305
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3840106946
Short name T304
Test name
Test status
Simulation time 159489466505 ps
CPU time 2.65 seconds
Started Jun 29 06:42:36 PM PDT 24
Finished Jun 29 06:42:39 PM PDT 24
Peak memory 201880 kb
Host smart-2397e96b-9976-4623-98b4-6830030ec690
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840106946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3840106946
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2634997984
Short name T673
Test name
Test status
Simulation time 517139388115 ps
CPU time 305.46 seconds
Started Jun 29 06:42:27 PM PDT 24
Finished Jun 29 06:47:33 PM PDT 24
Peak memory 201908 kb
Host smart-362f8bb8-333f-4305-8174-a25a0f00f457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634997984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2634997984
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1818083846
Short name T371
Test name
Test status
Simulation time 488242704370 ps
CPU time 256.66 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:46:42 PM PDT 24
Peak memory 201836 kb
Host smart-93ceaa16-2cd9-4ecc-b3d1-67e9daf5d28d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818083846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1818083846
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.507879985
Short name T198
Test name
Test status
Simulation time 330649636687 ps
CPU time 724.52 seconds
Started Jun 29 06:42:33 PM PDT 24
Finished Jun 29 06:54:38 PM PDT 24
Peak memory 201944 kb
Host smart-ddda2eae-1fef-4ff6-bae1-04b563c213d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507879985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.507879985
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2996061498
Short name T758
Test name
Test status
Simulation time 162103654323 ps
CPU time 70.73 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:43:37 PM PDT 24
Peak memory 201836 kb
Host smart-8523be5b-bce8-4d25-89d1-7337de1ea707
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996061498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2996061498
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2059022041
Short name T431
Test name
Test status
Simulation time 610441100105 ps
CPU time 363.91 seconds
Started Jun 29 06:42:18 PM PDT 24
Finished Jun 29 06:48:22 PM PDT 24
Peak memory 201856 kb
Host smart-5ab51954-bf04-48fe-a85b-444dec0f6596
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059022041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2059022041
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.111745011
Short name T220
Test name
Test status
Simulation time 82877081951 ps
CPU time 297.67 seconds
Started Jun 29 06:42:22 PM PDT 24
Finished Jun 29 06:47:20 PM PDT 24
Peak memory 202252 kb
Host smart-fb54b62f-067a-4fcb-906c-dba2715d5819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111745011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.111745011
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1641492967
Short name T504
Test name
Test status
Simulation time 44365169205 ps
CPU time 24.13 seconds
Started Jun 29 06:42:23 PM PDT 24
Finished Jun 29 06:42:48 PM PDT 24
Peak memory 201668 kb
Host smart-f426ef5a-76a5-4be6-ab9c-b9bbef7ea39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641492967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1641492967
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.4065033699
Short name T772
Test name
Test status
Simulation time 3148431074 ps
CPU time 1.07 seconds
Started Jun 29 06:42:27 PM PDT 24
Finished Jun 29 06:42:28 PM PDT 24
Peak memory 201676 kb
Host smart-57862b19-de7e-4210-946e-990197764948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065033699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.4065033699
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1648056309
Short name T689
Test name
Test status
Simulation time 5512570870 ps
CPU time 3.66 seconds
Started Jun 29 06:42:25 PM PDT 24
Finished Jun 29 06:42:30 PM PDT 24
Peak memory 201688 kb
Host smart-70229b5b-7953-4dff-a6e7-bf9d93b62e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648056309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1648056309
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.143347608
Short name T764
Test name
Test status
Simulation time 376102888482 ps
CPU time 218.7 seconds
Started Jun 29 06:42:44 PM PDT 24
Finished Jun 29 06:46:24 PM PDT 24
Peak memory 201872 kb
Host smart-abd19572-56f5-4eb0-adc0-06944dd8d8b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143347608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
143347608
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3718086832
Short name T547
Test name
Test status
Simulation time 212949669407 ps
CPU time 279.18 seconds
Started Jun 29 06:42:27 PM PDT 24
Finished Jun 29 06:47:07 PM PDT 24
Peak memory 217780 kb
Host smart-81b4b303-bf19-4e0a-9409-fb2b91c3a905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718086832 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3718086832
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.4001410772
Short name T618
Test name
Test status
Simulation time 514970730 ps
CPU time 0.91 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:41:53 PM PDT 24
Peak memory 201620 kb
Host smart-d803afb9-5e32-442b-a605-abda0575554d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001410772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.4001410772
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2144705400
Short name T649
Test name
Test status
Simulation time 499110079861 ps
CPU time 1106.08 seconds
Started Jun 29 06:42:20 PM PDT 24
Finished Jun 29 07:00:47 PM PDT 24
Peak memory 201828 kb
Host smart-aed386f8-1bfb-4319-b541-ecad3226b16a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144705400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2144705400
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4091532682
Short name T316
Test name
Test status
Simulation time 504979302442 ps
CPU time 1082.93 seconds
Started Jun 29 06:41:45 PM PDT 24
Finished Jun 29 06:59:49 PM PDT 24
Peak memory 201904 kb
Host smart-88831ca2-ff8d-4c60-abde-bf507588bddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091532682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4091532682
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2979891862
Short name T442
Test name
Test status
Simulation time 324509072621 ps
CPU time 161.29 seconds
Started Jun 29 06:41:49 PM PDT 24
Finished Jun 29 06:44:31 PM PDT 24
Peak memory 201928 kb
Host smart-d1c934c8-b006-4fa1-8896-d174c26ad041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979891862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2979891862
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2525428579
Short name T482
Test name
Test status
Simulation time 161804672749 ps
CPU time 372.38 seconds
Started Jun 29 06:41:50 PM PDT 24
Finished Jun 29 06:48:03 PM PDT 24
Peak memory 201848 kb
Host smart-1c380063-314c-49bc-9c28-cabadb43fd26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525428579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2525428579
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1857516965
Short name T541
Test name
Test status
Simulation time 162776387509 ps
CPU time 90.85 seconds
Started Jun 29 06:41:45 PM PDT 24
Finished Jun 29 06:43:16 PM PDT 24
Peak memory 201852 kb
Host smart-c486e227-f189-4b8e-9d85-4d641757ecce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857516965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1857516965
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1852037340
Short name T526
Test name
Test status
Simulation time 493350613196 ps
CPU time 334.08 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:47:29 PM PDT 24
Peak memory 201848 kb
Host smart-632ef3fe-f639-4d8e-9d65-438e42934d5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852037340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1852037340
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.890308639
Short name T473
Test name
Test status
Simulation time 180370259993 ps
CPU time 431.5 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:48:58 PM PDT 24
Peak memory 201960 kb
Host smart-93a3650f-f2cf-4b6d-a8a8-97cbddb74df9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890308639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.890308639
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.631406508
Short name T476
Test name
Test status
Simulation time 398919015106 ps
CPU time 56.74 seconds
Started Jun 29 06:41:44 PM PDT 24
Finished Jun 29 06:42:42 PM PDT 24
Peak memory 201844 kb
Host smart-e829ccd8-7d3e-4c4d-b105-f70c348f4a9b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631406508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.631406508
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.528556500
Short name T760
Test name
Test status
Simulation time 101366638389 ps
CPU time 328.48 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:47:17 PM PDT 24
Peak memory 202188 kb
Host smart-01b7d939-3990-4439-bfc7-34bb2eb24fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528556500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.528556500
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2936289949
Short name T421
Test name
Test status
Simulation time 35594074484 ps
CPU time 81.69 seconds
Started Jun 29 06:41:45 PM PDT 24
Finished Jun 29 06:43:08 PM PDT 24
Peak memory 201684 kb
Host smart-c50d881c-5166-4cb5-b23f-c922747977a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936289949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2936289949
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3373386539
Short name T1
Test name
Test status
Simulation time 3683219513 ps
CPU time 4.82 seconds
Started Jun 29 06:41:49 PM PDT 24
Finished Jun 29 06:41:54 PM PDT 24
Peak memory 201692 kb
Host smart-26300c83-548f-4504-a507-de8f9bee8ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373386539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3373386539
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.288534507
Short name T69
Test name
Test status
Simulation time 4148888887 ps
CPU time 3.08 seconds
Started Jun 29 06:41:48 PM PDT 24
Finished Jun 29 06:41:52 PM PDT 24
Peak memory 217096 kb
Host smart-d4e7d24e-3bcf-4c4d-b213-dbe790c89d76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288534507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.288534507
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2044011978
Short name T681
Test name
Test status
Simulation time 5815000974 ps
CPU time 14.75 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:42:02 PM PDT 24
Peak memory 201692 kb
Host smart-a0865385-7b92-4b2d-9d70-8667fec65b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044011978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2044011978
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3756391935
Short name T180
Test name
Test status
Simulation time 6281336086 ps
CPU time 16.1 seconds
Started Jun 29 06:42:02 PM PDT 24
Finished Jun 29 06:42:19 PM PDT 24
Peak memory 201672 kb
Host smart-754e4af6-e451-4f01-b887-cd96e7297928
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756391935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3756391935
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2992368997
Short name T520
Test name
Test status
Simulation time 137174215659 ps
CPU time 85.33 seconds
Started Jun 29 06:41:48 PM PDT 24
Finished Jun 29 06:43:14 PM PDT 24
Peak memory 218588 kb
Host smart-9b616a2b-ac42-4396-b396-da5f561678b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992368997 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2992368997
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3268869283
Short name T614
Test name
Test status
Simulation time 340561339 ps
CPU time 1.02 seconds
Started Jun 29 06:42:26 PM PDT 24
Finished Jun 29 06:42:27 PM PDT 24
Peak memory 201608 kb
Host smart-5f7d2f9a-6686-4f8f-a183-6f5b5813bb70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268869283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3268869283
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1825952563
Short name T300
Test name
Test status
Simulation time 156597722990 ps
CPU time 76.28 seconds
Started Jun 29 06:42:35 PM PDT 24
Finished Jun 29 06:43:52 PM PDT 24
Peak memory 201928 kb
Host smart-c2a14007-f629-45aa-b607-636522856a36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825952563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1825952563
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1377635652
Short name T713
Test name
Test status
Simulation time 320850657909 ps
CPU time 155.86 seconds
Started Jun 29 06:42:31 PM PDT 24
Finished Jun 29 06:45:08 PM PDT 24
Peak memory 201932 kb
Host smart-3047b338-ca72-4579-aba2-2d29f4e5be09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377635652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1377635652
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.115012377
Short name T224
Test name
Test status
Simulation time 168047064814 ps
CPU time 104.78 seconds
Started Jun 29 06:42:30 PM PDT 24
Finished Jun 29 06:44:16 PM PDT 24
Peak memory 201892 kb
Host smart-0200a443-49db-4439-b36d-eb3ccdfb06ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115012377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.115012377
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1197284720
Short name T391
Test name
Test status
Simulation time 497009261460 ps
CPU time 554.81 seconds
Started Jun 29 06:42:46 PM PDT 24
Finished Jun 29 06:52:02 PM PDT 24
Peak memory 201904 kb
Host smart-c5ca5831-9f74-4e91-86db-716a2c1ec1ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197284720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1197284720
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1921994746
Short name T228
Test name
Test status
Simulation time 160281416380 ps
CPU time 93.71 seconds
Started Jun 29 06:42:24 PM PDT 24
Finished Jun 29 06:43:58 PM PDT 24
Peak memory 201876 kb
Host smart-cb9e1bc8-df98-4d3f-ac8c-7dac32a8f348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921994746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1921994746
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2064657828
Short name T361
Test name
Test status
Simulation time 162043334630 ps
CPU time 364.12 seconds
Started Jun 29 06:42:35 PM PDT 24
Finished Jun 29 06:48:39 PM PDT 24
Peak memory 201796 kb
Host smart-dd547a94-6676-4b8e-8c95-257f44c0ffe9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064657828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2064657828
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.4200221877
Short name T286
Test name
Test status
Simulation time 496860792574 ps
CPU time 1162.36 seconds
Started Jun 29 06:42:33 PM PDT 24
Finished Jun 29 07:01:56 PM PDT 24
Peak memory 201896 kb
Host smart-9d0503ff-0bc2-4df3-a800-9fe400c689b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200221877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.4200221877
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1100314676
Short name T493
Test name
Test status
Simulation time 194556587163 ps
CPU time 467.66 seconds
Started Jun 29 06:42:28 PM PDT 24
Finished Jun 29 06:50:16 PM PDT 24
Peak memory 201812 kb
Host smart-fe57307b-4c65-4872-9a7b-a73822994206
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100314676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1100314676
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1418093898
Short name T785
Test name
Test status
Simulation time 97653586666 ps
CPU time 467.23 seconds
Started Jun 29 06:42:30 PM PDT 24
Finished Jun 29 06:50:18 PM PDT 24
Peak memory 202212 kb
Host smart-21cbf70e-93ef-4cd2-87a0-038ac7dd1c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418093898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1418093898
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3570707022
Short name T539
Test name
Test status
Simulation time 22130026101 ps
CPU time 12.91 seconds
Started Jun 29 06:42:34 PM PDT 24
Finished Jun 29 06:42:47 PM PDT 24
Peak memory 201680 kb
Host smart-6260c864-d5c9-4cdd-95d6-edef464a434b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570707022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3570707022
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.589268686
Short name T25
Test name
Test status
Simulation time 4844207124 ps
CPU time 6.03 seconds
Started Jun 29 06:42:33 PM PDT 24
Finished Jun 29 06:42:40 PM PDT 24
Peak memory 201680 kb
Host smart-0d6146d5-f531-4a58-82ba-887ab8112528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589268686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.589268686
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.42164305
Short name T45
Test name
Test status
Simulation time 5962674454 ps
CPU time 3.91 seconds
Started Jun 29 06:42:32 PM PDT 24
Finished Jun 29 06:42:36 PM PDT 24
Peak memory 201680 kb
Host smart-bb327064-cb70-4725-acc1-18a1b82dbb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42164305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.42164305
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2660209414
Short name T457
Test name
Test status
Simulation time 50525835026 ps
CPU time 63.91 seconds
Started Jun 29 06:42:43 PM PDT 24
Finished Jun 29 06:43:48 PM PDT 24
Peak memory 201680 kb
Host smart-65a2a6d1-0b30-4609-8a90-0a96c6ee2dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660209414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2660209414
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3184338629
Short name T792
Test name
Test status
Simulation time 318483795 ps
CPU time 1.04 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:42:48 PM PDT 24
Peak memory 201572 kb
Host smart-bd31aeb7-283b-4ecd-a44a-6a6c94ef40cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184338629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3184338629
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2411430472
Short name T718
Test name
Test status
Simulation time 324967262324 ps
CPU time 203.83 seconds
Started Jun 29 06:42:35 PM PDT 24
Finished Jun 29 06:46:00 PM PDT 24
Peak memory 201872 kb
Host smart-0d7c98e6-bb32-459b-a6d6-c92d7074bf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411430472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2411430472
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.269429086
Short name T481
Test name
Test status
Simulation time 331182211920 ps
CPU time 140.57 seconds
Started Jun 29 06:42:37 PM PDT 24
Finished Jun 29 06:44:59 PM PDT 24
Peak memory 201760 kb
Host smart-b80587ea-bf3e-4240-abec-df26d0fd78d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=269429086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.269429086
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1098171493
Short name T126
Test name
Test status
Simulation time 329186531640 ps
CPU time 230.44 seconds
Started Jun 29 06:42:43 PM PDT 24
Finished Jun 29 06:46:35 PM PDT 24
Peak memory 201892 kb
Host smart-f8fe31d4-470f-4258-aadc-74e09087dc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098171493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1098171493
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1650895525
Short name T783
Test name
Test status
Simulation time 323552737695 ps
CPU time 806.02 seconds
Started Jun 29 06:42:33 PM PDT 24
Finished Jun 29 06:56:00 PM PDT 24
Peak memory 201864 kb
Host smart-d9b772b4-ab51-4ce8-a572-a0aa95e52e05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650895525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1650895525
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3739021217
Short name T573
Test name
Test status
Simulation time 339517111837 ps
CPU time 801.9 seconds
Started Jun 29 06:42:30 PM PDT 24
Finished Jun 29 06:55:53 PM PDT 24
Peak memory 201876 kb
Host smart-609b07ed-3bad-428b-9773-f3299126e60a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739021217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3739021217
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3607833278
Short name T680
Test name
Test status
Simulation time 210616058495 ps
CPU time 510.07 seconds
Started Jun 29 06:42:38 PM PDT 24
Finished Jun 29 06:51:08 PM PDT 24
Peak memory 201856 kb
Host smart-1883daa2-541f-45e8-b4eb-fe3fef242fdc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607833278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3607833278
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1883029578
Short name T191
Test name
Test status
Simulation time 26264132688 ps
CPU time 16.22 seconds
Started Jun 29 06:42:30 PM PDT 24
Finished Jun 29 06:42:47 PM PDT 24
Peak memory 201676 kb
Host smart-fd87d217-6ba9-4c70-9309-ec367a5fee5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883029578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1883029578
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3754105642
Short name T401
Test name
Test status
Simulation time 4430932793 ps
CPU time 1.75 seconds
Started Jun 29 06:42:28 PM PDT 24
Finished Jun 29 06:42:30 PM PDT 24
Peak memory 201668 kb
Host smart-03cefc85-1375-4944-8e37-33d2ce6b1854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754105642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3754105642
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2343576202
Short name T569
Test name
Test status
Simulation time 6111034590 ps
CPU time 3.18 seconds
Started Jun 29 06:42:27 PM PDT 24
Finished Jun 29 06:42:31 PM PDT 24
Peak memory 201680 kb
Host smart-b4401457-ffd3-47c7-b960-d89d2fd6118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343576202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2343576202
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2998498878
Short name T637
Test name
Test status
Simulation time 286832936007 ps
CPU time 704.55 seconds
Started Jun 29 06:42:36 PM PDT 24
Finished Jun 29 06:54:21 PM PDT 24
Peak memory 210352 kb
Host smart-85dfaa94-0a2d-4439-a41f-d9a4d9916be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998498878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2998498878
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1830496611
Short name T325
Test name
Test status
Simulation time 46415814762 ps
CPU time 124.46 seconds
Started Jun 29 06:42:31 PM PDT 24
Finished Jun 29 06:44:36 PM PDT 24
Peak memory 210484 kb
Host smart-6e669177-f341-4a48-84ac-2406054171f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830496611 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1830496611
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.299995140
Short name T75
Test name
Test status
Simulation time 385366344 ps
CPU time 0.87 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:42:48 PM PDT 24
Peak memory 201388 kb
Host smart-756db0ea-d3aa-496c-94df-b4ef15edac9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299995140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.299995140
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1320896114
Short name T343
Test name
Test status
Simulation time 171890933470 ps
CPU time 93.76 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:44:23 PM PDT 24
Peak memory 201920 kb
Host smart-eb6c9da3-11fa-4093-93ff-e0e9b5adbd88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320896114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1320896114
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.891687739
Short name T703
Test name
Test status
Simulation time 166443443716 ps
CPU time 96.52 seconds
Started Jun 29 06:42:30 PM PDT 24
Finished Jun 29 06:44:08 PM PDT 24
Peak memory 201868 kb
Host smart-36750f3c-7a78-4f64-9e31-2b376df8124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891687739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.891687739
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3503837616
Short name T484
Test name
Test status
Simulation time 492994867399 ps
CPU time 101.52 seconds
Started Jun 29 06:42:33 PM PDT 24
Finished Jun 29 06:44:15 PM PDT 24
Peak memory 201860 kb
Host smart-64b1ca00-f94d-415d-842e-612a85cf1611
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503837616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3503837616
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1698763468
Short name T606
Test name
Test status
Simulation time 335689474957 ps
CPU time 363.95 seconds
Started Jun 29 06:42:30 PM PDT 24
Finished Jun 29 06:48:34 PM PDT 24
Peak memory 201964 kb
Host smart-4dcca37f-da25-4e32-8358-af7dc403973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698763468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1698763468
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2638095517
Short name T364
Test name
Test status
Simulation time 164752106624 ps
CPU time 186.15 seconds
Started Jun 29 06:42:35 PM PDT 24
Finished Jun 29 06:45:41 PM PDT 24
Peak memory 201844 kb
Host smart-e08b1b82-c3a7-4b3e-9241-4b1e5c572c03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638095517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2638095517
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.564191010
Short name T763
Test name
Test status
Simulation time 395157294600 ps
CPU time 322.12 seconds
Started Jun 29 06:42:29 PM PDT 24
Finished Jun 29 06:47:52 PM PDT 24
Peak memory 201860 kb
Host smart-df71026b-c026-4790-acd6-1f2aac2480ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564191010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.564191010
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1848459014
Short name T553
Test name
Test status
Simulation time 72351501403 ps
CPU time 241.59 seconds
Started Jun 29 06:42:37 PM PDT 24
Finished Jun 29 06:46:39 PM PDT 24
Peak memory 202192 kb
Host smart-90cbcc61-a841-432b-b6bb-902cbe5bfd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848459014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1848459014
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3753233670
Short name T495
Test name
Test status
Simulation time 44094450067 ps
CPU time 49.66 seconds
Started Jun 29 06:42:33 PM PDT 24
Finished Jun 29 06:43:23 PM PDT 24
Peak memory 201676 kb
Host smart-2aed2b54-5665-4f9e-a187-ad5cc4909f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753233670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3753233670
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2362449407
Short name T162
Test name
Test status
Simulation time 2926144229 ps
CPU time 3.18 seconds
Started Jun 29 06:42:47 PM PDT 24
Finished Jun 29 06:42:51 PM PDT 24
Peak memory 201584 kb
Host smart-d3117c76-bdc7-443d-8c08-ba2e24fbef79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362449407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2362449407
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2791987036
Short name T708
Test name
Test status
Simulation time 5982188939 ps
CPU time 14.05 seconds
Started Jun 29 06:42:27 PM PDT 24
Finished Jun 29 06:42:42 PM PDT 24
Peak memory 201676 kb
Host smart-c9a9d8a0-26c1-488e-818f-bf9f722bc30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791987036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2791987036
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2807348041
Short name T403
Test name
Test status
Simulation time 54559425079 ps
CPU time 7.41 seconds
Started Jun 29 06:42:38 PM PDT 24
Finished Jun 29 06:42:46 PM PDT 24
Peak memory 201880 kb
Host smart-533a9ecc-812c-4767-851c-770635306a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807348041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2807348041
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3862911820
Short name T12
Test name
Test status
Simulation time 60217983117 ps
CPU time 47.34 seconds
Started Jun 29 06:42:34 PM PDT 24
Finished Jun 29 06:43:21 PM PDT 24
Peak memory 210864 kb
Host smart-3149a0c0-bdbc-478a-b76f-7966e495049b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862911820 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3862911820
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2440617806
Short name T518
Test name
Test status
Simulation time 487613092 ps
CPU time 1.76 seconds
Started Jun 29 06:42:35 PM PDT 24
Finished Jun 29 06:42:37 PM PDT 24
Peak memory 201624 kb
Host smart-25a962fa-ecdc-4749-97ac-e9063efc9d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440617806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2440617806
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1665586619
Short name T285
Test name
Test status
Simulation time 162063868285 ps
CPU time 200.83 seconds
Started Jun 29 06:42:35 PM PDT 24
Finished Jun 29 06:45:56 PM PDT 24
Peak memory 201836 kb
Host smart-e52931ae-4520-4442-a433-2823e940da88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665586619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1665586619
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2995968832
Short name T230
Test name
Test status
Simulation time 333093574247 ps
CPU time 55.35 seconds
Started Jun 29 06:42:36 PM PDT 24
Finished Jun 29 06:43:32 PM PDT 24
Peak memory 201928 kb
Host smart-dd79502c-cb49-47d5-abd0-38eb04d166ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995968832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2995968832
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.601309921
Short name T241
Test name
Test status
Simulation time 162735576201 ps
CPU time 108.46 seconds
Started Jun 29 06:42:47 PM PDT 24
Finished Jun 29 06:44:36 PM PDT 24
Peak memory 201816 kb
Host smart-34409630-9f2f-46f3-8a5c-a73ef641423e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601309921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.601309921
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3124029146
Short name T666
Test name
Test status
Simulation time 494797715303 ps
CPU time 1154.26 seconds
Started Jun 29 06:42:49 PM PDT 24
Finished Jun 29 07:02:04 PM PDT 24
Peak memory 201864 kb
Host smart-dbac59da-45c4-48ef-9674-ef887cd19b17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124029146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3124029146
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.973607682
Short name T755
Test name
Test status
Simulation time 163619351576 ps
CPU time 183.09 seconds
Started Jun 29 06:42:32 PM PDT 24
Finished Jun 29 06:45:35 PM PDT 24
Peak memory 201824 kb
Host smart-cf0525fb-41ff-443f-94c8-645b55b34b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973607682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.973607682
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3419023477
Short name T181
Test name
Test status
Simulation time 163066700054 ps
CPU time 98.97 seconds
Started Jun 29 06:42:37 PM PDT 24
Finished Jun 29 06:44:16 PM PDT 24
Peak memory 201844 kb
Host smart-766c8e50-0330-4cb7-910a-2808f408af57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419023477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3419023477
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1994439861
Short name T149
Test name
Test status
Simulation time 536745963481 ps
CPU time 329.27 seconds
Started Jun 29 06:42:37 PM PDT 24
Finished Jun 29 06:48:07 PM PDT 24
Peak memory 201892 kb
Host smart-5d30808c-828e-4356-8cb7-13c6e645677a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994439861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1994439861
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.712483552
Short name T536
Test name
Test status
Simulation time 205305629776 ps
CPU time 207.02 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:46:18 PM PDT 24
Peak memory 201860 kb
Host smart-f0847578-6d84-492c-8153-4f40793f2b2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712483552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.712483552
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2411112919
Short name T612
Test name
Test status
Simulation time 117136650613 ps
CPU time 381.02 seconds
Started Jun 29 06:42:33 PM PDT 24
Finished Jun 29 06:48:54 PM PDT 24
Peak memory 202252 kb
Host smart-c0c7cdc4-9792-4d4f-9047-662f7510c395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411112919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2411112919
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2327827027
Short name T381
Test name
Test status
Simulation time 40723054374 ps
CPU time 23.33 seconds
Started Jun 29 06:42:36 PM PDT 24
Finished Jun 29 06:43:00 PM PDT 24
Peak memory 201672 kb
Host smart-2428cc72-c143-42b4-ac41-ecda39d9d3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327827027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2327827027
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.886359974
Short name T483
Test name
Test status
Simulation time 5061780283 ps
CPU time 3.22 seconds
Started Jun 29 06:42:44 PM PDT 24
Finished Jun 29 06:42:49 PM PDT 24
Peak memory 201712 kb
Host smart-a8e7ac79-0640-4461-9e74-1b997e7d6083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886359974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.886359974
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3394876030
Short name T472
Test name
Test status
Simulation time 5935089623 ps
CPU time 4.27 seconds
Started Jun 29 06:42:46 PM PDT 24
Finished Jun 29 06:42:52 PM PDT 24
Peak memory 201636 kb
Host smart-f1254658-4a86-478c-8a48-e7fe0668e433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394876030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3394876030
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1616246220
Short name T345
Test name
Test status
Simulation time 380945310725 ps
CPU time 142.66 seconds
Started Jun 29 06:42:30 PM PDT 24
Finished Jun 29 06:44:54 PM PDT 24
Peak memory 201836 kb
Host smart-5ef6c611-9fc8-4ce0-b799-c45ac018a50c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616246220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1616246220
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3233179341
Short name T679
Test name
Test status
Simulation time 372108059 ps
CPU time 1.05 seconds
Started Jun 29 06:42:31 PM PDT 24
Finished Jun 29 06:42:33 PM PDT 24
Peak memory 201640 kb
Host smart-bf51569e-ecfe-4efb-9a53-efd55cd7c8a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233179341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3233179341
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3492161242
Short name T741
Test name
Test status
Simulation time 162660582505 ps
CPU time 225.45 seconds
Started Jun 29 06:42:39 PM PDT 24
Finished Jun 29 06:46:26 PM PDT 24
Peak memory 201924 kb
Host smart-609cf64d-7bbf-4d73-96d0-efc1db9d539e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492161242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3492161242
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3321875852
Short name T264
Test name
Test status
Simulation time 161812654766 ps
CPU time 406.02 seconds
Started Jun 29 06:42:36 PM PDT 24
Finished Jun 29 06:49:23 PM PDT 24
Peak memory 201880 kb
Host smart-f77f08b4-1acc-4eba-aba5-32e68dda6357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321875852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3321875852
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.264699119
Short name T279
Test name
Test status
Simulation time 323146876926 ps
CPU time 686.55 seconds
Started Jun 29 06:42:37 PM PDT 24
Finished Jun 29 06:54:04 PM PDT 24
Peak memory 202084 kb
Host smart-65e77802-5298-4d9a-86e0-9fe416e75fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264699119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.264699119
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.55806079
Short name T636
Test name
Test status
Simulation time 164944704874 ps
CPU time 196.29 seconds
Started Jun 29 06:42:46 PM PDT 24
Finished Jun 29 06:46:03 PM PDT 24
Peak memory 201768 kb
Host smart-8d44485d-32d5-4d4c-bc77-42a7b69f5592
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=55806079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt
_fixed.55806079
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.623315962
Short name T542
Test name
Test status
Simulation time 164794712819 ps
CPU time 100.64 seconds
Started Jun 29 06:42:29 PM PDT 24
Finished Jun 29 06:44:10 PM PDT 24
Peak memory 201876 kb
Host smart-084eaa2e-78d8-4e08-bf44-48a338ce23ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623315962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.623315962
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.4094424598
Short name T663
Test name
Test status
Simulation time 327474135477 ps
CPU time 363.78 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:48:51 PM PDT 24
Peak memory 201852 kb
Host smart-2b505d40-c0b5-416e-add0-19eb818873cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094424598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.4094424598
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1062846680
Short name T270
Test name
Test status
Simulation time 370815468882 ps
CPU time 217.9 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:46:27 PM PDT 24
Peak memory 201940 kb
Host smart-a9216375-bcbe-466d-b971-d77a95d1dac4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062846680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1062846680
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1786539932
Short name T571
Test name
Test status
Simulation time 204800874418 ps
CPU time 124.41 seconds
Started Jun 29 06:42:39 PM PDT 24
Finished Jun 29 06:44:45 PM PDT 24
Peak memory 201852 kb
Host smart-d000c1e6-20b9-4edf-9a45-d921a727f10e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786539932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1786539932
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3267206162
Short name T700
Test name
Test status
Simulation time 118307131816 ps
CPU time 493.5 seconds
Started Jun 29 06:42:40 PM PDT 24
Finished Jun 29 06:50:54 PM PDT 24
Peak memory 202188 kb
Host smart-409dfb6f-0fbd-476e-81bb-4310f946e94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267206162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3267206162
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2454215927
Short name T789
Test name
Test status
Simulation time 29277060028 ps
CPU time 17.93 seconds
Started Jun 29 06:42:41 PM PDT 24
Finished Jun 29 06:43:00 PM PDT 24
Peak memory 201688 kb
Host smart-a68f09bf-ad41-4bcb-9c0a-6774bb84f8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454215927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2454215927
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.764844164
Short name T665
Test name
Test status
Simulation time 4833251122 ps
CPU time 6.35 seconds
Started Jun 29 06:42:41 PM PDT 24
Finished Jun 29 06:42:49 PM PDT 24
Peak memory 201700 kb
Host smart-31aa7d6a-3265-409d-8547-163791166201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764844164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.764844164
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2843709158
Short name T413
Test name
Test status
Simulation time 5887260421 ps
CPU time 4.01 seconds
Started Jun 29 06:42:33 PM PDT 24
Finished Jun 29 06:42:37 PM PDT 24
Peak memory 201688 kb
Host smart-aca9c797-bac8-4e2a-a45a-95a9b418b230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843709158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2843709158
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.820839946
Short name T628
Test name
Test status
Simulation time 537445638967 ps
CPU time 269.12 seconds
Started Jun 29 06:42:46 PM PDT 24
Finished Jun 29 06:47:16 PM PDT 24
Peak memory 201804 kb
Host smart-bc097dbe-c0cb-490e-93bd-c52491254ec7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820839946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
820839946
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2638258178
Short name T106
Test name
Test status
Simulation time 68564375616 ps
CPU time 179.4 seconds
Started Jun 29 06:42:33 PM PDT 24
Finished Jun 29 06:45:33 PM PDT 24
Peak memory 218020 kb
Host smart-c0878b4a-3991-4ee5-b3f9-58ba9b38b8f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638258178 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2638258178
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.101382849
Short name T779
Test name
Test status
Simulation time 327031630 ps
CPU time 0.83 seconds
Started Jun 29 06:42:33 PM PDT 24
Finished Jun 29 06:42:35 PM PDT 24
Peak memory 201628 kb
Host smart-641445d0-26db-4947-bc0c-c58956d8b015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101382849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.101382849
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3095242344
Short name T320
Test name
Test status
Simulation time 170905562300 ps
CPU time 89.07 seconds
Started Jun 29 06:42:47 PM PDT 24
Finished Jun 29 06:44:17 PM PDT 24
Peak memory 201852 kb
Host smart-f8b154a7-03ce-46b3-b94f-e2840cbe8523
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095242344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3095242344
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1865610142
Short name T435
Test name
Test status
Simulation time 330945929940 ps
CPU time 206.12 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:46:13 PM PDT 24
Peak memory 201944 kb
Host smart-9baba589-6fb4-4ed7-9970-c65cc38cd3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865610142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1865610142
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3025121916
Short name T426
Test name
Test status
Simulation time 331801011906 ps
CPU time 412.56 seconds
Started Jun 29 06:42:32 PM PDT 24
Finished Jun 29 06:49:25 PM PDT 24
Peak memory 201852 kb
Host smart-17081157-fb8e-4237-aa33-220d68692359
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025121916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3025121916
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2127348335
Short name T296
Test name
Test status
Simulation time 333270983221 ps
CPU time 325.48 seconds
Started Jun 29 06:42:40 PM PDT 24
Finished Jun 29 06:48:07 PM PDT 24
Peak memory 201952 kb
Host smart-a2c39c38-2e49-404b-90b2-d64ac5b7cbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127348335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2127348335
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3740927806
Short name T530
Test name
Test status
Simulation time 162964714659 ps
CPU time 399.31 seconds
Started Jun 29 06:42:31 PM PDT 24
Finished Jun 29 06:49:11 PM PDT 24
Peak memory 201804 kb
Host smart-78c86851-2e0f-45c0-884c-996f99381c31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740927806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3740927806
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3712959251
Short name T225
Test name
Test status
Simulation time 570726437821 ps
CPU time 660.03 seconds
Started Jun 29 06:42:37 PM PDT 24
Finished Jun 29 06:53:38 PM PDT 24
Peak memory 201964 kb
Host smart-c79be6f4-1d5d-45b6-b808-3412a85c380e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712959251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3712959251
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.877717776
Short name T555
Test name
Test status
Simulation time 405830246618 ps
CPU time 869.61 seconds
Started Jun 29 06:42:40 PM PDT 24
Finished Jun 29 06:57:11 PM PDT 24
Peak memory 201860 kb
Host smart-7d15a868-10db-4e4e-96cd-77be3f6e04fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877717776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.877717776
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2021346606
Short name T397
Test name
Test status
Simulation time 93719914333 ps
CPU time 468.46 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:50:35 PM PDT 24
Peak memory 201916 kb
Host smart-2bd6f01a-7e6f-4bf3-b6c7-f59a12c539fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021346606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2021346606
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1639788963
Short name T7
Test name
Test status
Simulation time 35915056836 ps
CPU time 32.88 seconds
Started Jun 29 06:42:32 PM PDT 24
Finished Jun 29 06:43:06 PM PDT 24
Peak memory 201680 kb
Host smart-dadb53ae-8bda-486b-bce5-75bd8d6fdac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639788963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1639788963
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2625120255
Short name T554
Test name
Test status
Simulation time 3612510220 ps
CPU time 4.4 seconds
Started Jun 29 06:42:36 PM PDT 24
Finished Jun 29 06:42:41 PM PDT 24
Peak memory 201676 kb
Host smart-e99fa69c-df53-4369-b830-2900ef55fe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625120255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2625120255
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.639878629
Short name T480
Test name
Test status
Simulation time 5966522748 ps
CPU time 2.36 seconds
Started Jun 29 06:42:38 PM PDT 24
Finished Jun 29 06:42:42 PM PDT 24
Peak memory 201704 kb
Host smart-b3fa83f0-921b-4cc7-bbe9-1ed8b6e62ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639878629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.639878629
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1906893395
Short name T474
Test name
Test status
Simulation time 163520159660 ps
CPU time 342.95 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:48:30 PM PDT 24
Peak memory 201948 kb
Host smart-0f3ada1c-0032-4754-8c43-9673654e0aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906893395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1906893395
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2568383213
Short name T276
Test name
Test status
Simulation time 127945462911 ps
CPU time 68.73 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:43:58 PM PDT 24
Peak memory 212836 kb
Host smart-3282fd32-0139-43cc-b898-7ccf3745c339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568383213 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2568383213
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.469548599
Short name T674
Test name
Test status
Simulation time 533383530 ps
CPU time 0.96 seconds
Started Jun 29 06:42:42 PM PDT 24
Finished Jun 29 06:42:45 PM PDT 24
Peak memory 201628 kb
Host smart-85ab2994-5a7e-403d-beb7-19933e513def
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469548599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.469548599
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1747975762
Short name T258
Test name
Test status
Simulation time 490445714722 ps
CPU time 659.76 seconds
Started Jun 29 06:42:28 PM PDT 24
Finished Jun 29 06:53:29 PM PDT 24
Peak memory 201868 kb
Host smart-44b1d957-2f8c-41cb-b590-c7b7baa849f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747975762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1747975762
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2766425172
Short name T319
Test name
Test status
Simulation time 359932081748 ps
CPU time 66.22 seconds
Started Jun 29 06:42:41 PM PDT 24
Finished Jun 29 06:43:49 PM PDT 24
Peak memory 201956 kb
Host smart-15701b0f-300e-46be-bed3-231c28bd2489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766425172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2766425172
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2177691136
Short name T98
Test name
Test status
Simulation time 162190399738 ps
CPU time 61.24 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:43:50 PM PDT 24
Peak memory 201852 kb
Host smart-d5e74450-0823-4d96-88ad-0211790bd28e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177691136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2177691136
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3172669092
Short name T477
Test name
Test status
Simulation time 492729673155 ps
CPU time 574.45 seconds
Started Jun 29 06:42:43 PM PDT 24
Finished Jun 29 06:52:19 PM PDT 24
Peak memory 201904 kb
Host smart-7fa9b24c-383b-4e90-a8c3-e68efec7c501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172669092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3172669092
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4014366080
Short name T566
Test name
Test status
Simulation time 487244710936 ps
CPU time 1033.01 seconds
Started Jun 29 06:42:37 PM PDT 24
Finished Jun 29 06:59:51 PM PDT 24
Peak memory 201848 kb
Host smart-1cc3cd5c-be91-4a63-b470-30005d6cbea0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014366080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4014366080
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3352310748
Short name T407
Test name
Test status
Simulation time 392728452197 ps
CPU time 213.14 seconds
Started Jun 29 06:42:31 PM PDT 24
Finished Jun 29 06:46:05 PM PDT 24
Peak memory 201832 kb
Host smart-542f6da5-7494-4171-8ea4-f240598a74a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352310748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3352310748
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3301509694
Short name T699
Test name
Test status
Simulation time 97807491196 ps
CPU time 368.43 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:48:55 PM PDT 24
Peak memory 202212 kb
Host smart-c2f1b5ce-debc-4b47-9174-a653aade447d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301509694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3301509694
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1857019380
Short name T672
Test name
Test status
Simulation time 23085149553 ps
CPU time 5.31 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:42:54 PM PDT 24
Peak memory 201680 kb
Host smart-2424ae45-02c2-4a3b-87e7-2463e765883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857019380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1857019380
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2169535879
Short name T591
Test name
Test status
Simulation time 4214420106 ps
CPU time 10.77 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:42:57 PM PDT 24
Peak memory 201672 kb
Host smart-62117b44-a4ca-4161-8399-e2c3e68d20ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169535879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2169535879
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2911427097
Short name T184
Test name
Test status
Simulation time 6127652494 ps
CPU time 4.54 seconds
Started Jun 29 06:42:36 PM PDT 24
Finished Jun 29 06:42:41 PM PDT 24
Peak memory 201676 kb
Host smart-12914b85-c742-48a9-ae64-b2e14cc8178e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911427097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2911427097
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.819732624
Short name T31
Test name
Test status
Simulation time 17525193083 ps
CPU time 37 seconds
Started Jun 29 06:42:46 PM PDT 24
Finished Jun 29 06:43:24 PM PDT 24
Peak memory 202068 kb
Host smart-fe736d1b-af04-4fc3-9848-8f5feefb604d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819732624 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.819732624
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3658137451
Short name T524
Test name
Test status
Simulation time 446982253 ps
CPU time 1.18 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:42:50 PM PDT 24
Peak memory 201624 kb
Host smart-1487f847-df4e-4074-9615-35fb2b7285b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658137451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3658137451
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.717714788
Short name T695
Test name
Test status
Simulation time 190070297928 ps
CPU time 113.7 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:44:44 PM PDT 24
Peak memory 201880 kb
Host smart-f6a45e9b-42f6-4981-911c-47a9952ddeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717714788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.717714788
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1943384295
Short name T642
Test name
Test status
Simulation time 162003567140 ps
CPU time 190.15 seconds
Started Jun 29 06:42:36 PM PDT 24
Finished Jun 29 06:45:47 PM PDT 24
Peak memory 201956 kb
Host smart-6626d915-f39a-448b-a6f1-b7f8dc7e7945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943384295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1943384295
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.745612590
Short name T613
Test name
Test status
Simulation time 487320356487 ps
CPU time 1024.38 seconds
Started Jun 29 06:42:36 PM PDT 24
Finished Jun 29 06:59:41 PM PDT 24
Peak memory 201876 kb
Host smart-3e4348f6-f7a5-46af-b14b-8d7d0f45c109
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=745612590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.745612590
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1966246532
Short name T405
Test name
Test status
Simulation time 165357907524 ps
CPU time 186.57 seconds
Started Jun 29 06:42:46 PM PDT 24
Finished Jun 29 06:45:54 PM PDT 24
Peak memory 201908 kb
Host smart-b1f38140-92c0-4eca-80f0-2f9962468daa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966246532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1966246532
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3488938966
Short name T489
Test name
Test status
Simulation time 406495960403 ps
CPU time 859.71 seconds
Started Jun 29 06:42:41 PM PDT 24
Finished Jun 29 06:57:02 PM PDT 24
Peak memory 201868 kb
Host smart-3c571695-b17d-43ec-926f-e67425b58675
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488938966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3488938966
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1346166269
Short name T570
Test name
Test status
Simulation time 127840431542 ps
CPU time 497.1 seconds
Started Jun 29 06:42:38 PM PDT 24
Finished Jun 29 06:50:56 PM PDT 24
Peak memory 202204 kb
Host smart-1cc9c964-138e-44c1-a28e-46cca487bebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346166269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1346166269
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1721566265
Short name T97
Test name
Test status
Simulation time 26655884623 ps
CPU time 59.98 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:43:51 PM PDT 24
Peak memory 201668 kb
Host smart-74b041e4-4348-41e3-a338-7075831003c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721566265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1721566265
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.198898496
Short name T677
Test name
Test status
Simulation time 4422943173 ps
CPU time 10.25 seconds
Started Jun 29 06:42:39 PM PDT 24
Finished Jun 29 06:42:50 PM PDT 24
Peak memory 201652 kb
Host smart-95a7f3cd-2fb0-4079-afde-d53ccb2c0b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198898496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.198898496
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1371065163
Short name T543
Test name
Test status
Simulation time 6110319794 ps
CPU time 1.5 seconds
Started Jun 29 06:42:51 PM PDT 24
Finished Jun 29 06:42:53 PM PDT 24
Peak memory 201664 kb
Host smart-64c9c733-485f-4293-ad4d-594ee7a2aba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371065163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1371065163
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1989567986
Short name T707
Test name
Test status
Simulation time 350329393296 ps
CPU time 831.05 seconds
Started Jun 29 06:42:41 PM PDT 24
Finished Jun 29 06:56:34 PM PDT 24
Peak memory 201940 kb
Host smart-350a7d7a-31e8-43c8-bac7-824094692b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989567986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1989567986
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1028159169
Short name T76
Test name
Test status
Simulation time 387193817 ps
CPU time 0.84 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:42:48 PM PDT 24
Peak memory 201624 kb
Host smart-f7bfd8e6-d1f3-4c08-ab67-14b6f06bf964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028159169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1028159169
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1297743528
Short name T723
Test name
Test status
Simulation time 579130514765 ps
CPU time 895.07 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:57:46 PM PDT 24
Peak memory 201876 kb
Host smart-aac37a76-3df1-48f5-aabf-2efb738ad606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297743528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1297743528
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1624462456
Short name T437
Test name
Test status
Simulation time 330233664499 ps
CPU time 771.21 seconds
Started Jun 29 06:42:49 PM PDT 24
Finished Jun 29 06:55:41 PM PDT 24
Peak memory 201848 kb
Host smart-ada4237e-09de-4752-9012-e90c848b4567
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624462456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1624462456
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3189578658
Short name T735
Test name
Test status
Simulation time 329956332996 ps
CPU time 753.9 seconds
Started Jun 29 06:42:43 PM PDT 24
Finished Jun 29 06:55:19 PM PDT 24
Peak memory 201944 kb
Host smart-64b2b5fe-05e6-4e5b-a358-26431673f091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189578658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3189578658
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1944093627
Short name T580
Test name
Test status
Simulation time 339103739287 ps
CPU time 145.55 seconds
Started Jun 29 06:42:37 PM PDT 24
Finished Jun 29 06:45:03 PM PDT 24
Peak memory 201832 kb
Host smart-f439f37d-1a2d-43b2-ac10-914f641713e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944093627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1944093627
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2354917851
Short name T766
Test name
Test status
Simulation time 662596300161 ps
CPU time 778.06 seconds
Started Jun 29 06:42:44 PM PDT 24
Finished Jun 29 06:55:43 PM PDT 24
Peak memory 201888 kb
Host smart-532a1911-08f3-4e89-a395-2bdea7e88cb1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354917851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2354917851
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2664261354
Short name T373
Test name
Test status
Simulation time 404709989399 ps
CPU time 962.39 seconds
Started Jun 29 06:42:40 PM PDT 24
Finished Jun 29 06:58:44 PM PDT 24
Peak memory 201844 kb
Host smart-5cf098f3-dc40-434c-ac07-40558411b638
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664261354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2664261354
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2814444768
Short name T754
Test name
Test status
Simulation time 68635953752 ps
CPU time 235.08 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:46:41 PM PDT 24
Peak memory 202176 kb
Host smart-faf1ff99-30e3-4d46-b6d7-66b398eddbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814444768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2814444768
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1043271827
Short name T414
Test name
Test status
Simulation time 39149271501 ps
CPU time 88.38 seconds
Started Jun 29 06:42:39 PM PDT 24
Finished Jun 29 06:44:09 PM PDT 24
Peak memory 201672 kb
Host smart-c8735df9-6e9b-4a61-928e-a70ac5550e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043271827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1043271827
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1577343028
Short name T664
Test name
Test status
Simulation time 3326699264 ps
CPU time 2.54 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:42:53 PM PDT 24
Peak memory 201680 kb
Host smart-94dcaa8a-570c-483f-908a-91c1be41d410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577343028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1577343028
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3343022751
Short name T367
Test name
Test status
Simulation time 5572241300 ps
CPU time 1.83 seconds
Started Jun 29 06:42:40 PM PDT 24
Finished Jun 29 06:42:42 PM PDT 24
Peak memory 201676 kb
Host smart-1cde2d26-2738-4e49-b40e-fe950953e4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343022751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3343022751
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.4145454326
Short name T354
Test name
Test status
Simulation time 131308061367 ps
CPU time 337.25 seconds
Started Jun 29 06:42:49 PM PDT 24
Finished Jun 29 06:48:27 PM PDT 24
Peak memory 202240 kb
Host smart-edc7b622-21ad-4231-9573-f2bb581af2e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145454326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.4145454326
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3296521420
Short name T590
Test name
Test status
Simulation time 491686797 ps
CPU time 1.17 seconds
Started Jun 29 06:42:42 PM PDT 24
Finished Jun 29 06:42:45 PM PDT 24
Peak memory 201600 kb
Host smart-58fc34b3-3784-4581-8975-d02497869961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296521420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3296521420
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2986620922
Short name T378
Test name
Test status
Simulation time 334043552838 ps
CPU time 763.2 seconds
Started Jun 29 06:42:43 PM PDT 24
Finished Jun 29 06:55:28 PM PDT 24
Peak memory 201852 kb
Host smart-402a4eed-1493-4ce9-824f-c76375a5bcd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986620922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2986620922
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3512727804
Short name T631
Test name
Test status
Simulation time 492593996573 ps
CPU time 511.55 seconds
Started Jun 29 06:42:39 PM PDT 24
Finished Jun 29 06:51:12 PM PDT 24
Peak memory 201936 kb
Host smart-b05342e5-7cd8-4cff-a047-d29e414fe415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512727804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3512727804
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.526928116
Short name T168
Test name
Test status
Simulation time 332367378251 ps
CPU time 197.35 seconds
Started Jun 29 06:42:42 PM PDT 24
Finished Jun 29 06:46:00 PM PDT 24
Peak memory 201852 kb
Host smart-304c9beb-1c74-4dc4-b1c1-9e47078c7cbc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=526928116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.526928116
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1580967807
Short name T579
Test name
Test status
Simulation time 199895008772 ps
CPU time 242.96 seconds
Started Jun 29 06:42:40 PM PDT 24
Finished Jun 29 06:46:45 PM PDT 24
Peak memory 201948 kb
Host smart-3b6f5f0b-e8d9-4d47-8107-c4afa2bf2d85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580967807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1580967807
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3935791021
Short name T586
Test name
Test status
Simulation time 615067068915 ps
CPU time 1326.84 seconds
Started Jun 29 06:42:39 PM PDT 24
Finished Jun 29 07:04:46 PM PDT 24
Peak memory 201860 kb
Host smart-a471d22a-f2a8-424f-967f-0044d16ca7c7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935791021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3935791021
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.590792365
Short name T204
Test name
Test status
Simulation time 96914759876 ps
CPU time 319.68 seconds
Started Jun 29 06:42:41 PM PDT 24
Finished Jun 29 06:48:02 PM PDT 24
Peak memory 202128 kb
Host smart-e633c9e7-c8fd-4c8e-88f9-57643eb59a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590792365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.590792365
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.342240997
Short name T410
Test name
Test status
Simulation time 41213403061 ps
CPU time 19.24 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:43:08 PM PDT 24
Peak memory 201680 kb
Host smart-edb83e93-7062-48c7-b500-27f18f0463fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342240997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.342240997
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.566762360
Short name T469
Test name
Test status
Simulation time 4512871621 ps
CPU time 10.6 seconds
Started Jun 29 06:42:44 PM PDT 24
Finished Jun 29 06:42:56 PM PDT 24
Peak memory 201696 kb
Host smart-ad69f8d0-d450-41e3-b75c-06f3a1fb9ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566762360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.566762360
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.246737676
Short name T639
Test name
Test status
Simulation time 5796797995 ps
CPU time 6.8 seconds
Started Jun 29 06:42:44 PM PDT 24
Finished Jun 29 06:42:52 PM PDT 24
Peak memory 201680 kb
Host smart-d4605ba4-4a00-4ee3-8ccc-00aceca568cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246737676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.246737676
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.4010610543
Short name T49
Test name
Test status
Simulation time 18020636107 ps
CPU time 48.18 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:43:37 PM PDT 24
Peak memory 210564 kb
Host smart-67542eb1-aff8-4708-9c47-37096ed5d444
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010610543 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.4010610543
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3715127396
Short name T515
Test name
Test status
Simulation time 446833695 ps
CPU time 1.64 seconds
Started Jun 29 06:42:03 PM PDT 24
Finished Jun 29 06:42:05 PM PDT 24
Peak memory 201628 kb
Host smart-e6c2c293-d161-4722-b4e5-07474217539f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715127396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3715127396
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.4052681507
Short name T342
Test name
Test status
Simulation time 526506704815 ps
CPU time 388.66 seconds
Started Jun 29 06:41:52 PM PDT 24
Finished Jun 29 06:48:22 PM PDT 24
Peak memory 201860 kb
Host smart-850baf64-af04-49d7-9311-9ad941455863
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052681507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.4052681507
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.722803001
Short name T470
Test name
Test status
Simulation time 161944718536 ps
CPU time 195.68 seconds
Started Jun 29 06:42:12 PM PDT 24
Finished Jun 29 06:45:28 PM PDT 24
Peak memory 201944 kb
Host smart-ef7bac23-fb2a-4dff-bc4b-78664b32fe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722803001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.722803001
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.4248400832
Short name T459
Test name
Test status
Simulation time 496025083964 ps
CPU time 1163.73 seconds
Started Jun 29 06:41:48 PM PDT 24
Finished Jun 29 07:01:13 PM PDT 24
Peak memory 201856 kb
Host smart-c6403643-f9de-45de-94d9-40b098c792a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248400832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.4248400832
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3338341277
Short name T83
Test name
Test status
Simulation time 324631776451 ps
CPU time 734.82 seconds
Started Jun 29 06:41:47 PM PDT 24
Finished Jun 29 06:54:03 PM PDT 24
Peak memory 201936 kb
Host smart-252c2b42-7a5d-49d3-9b26-8c34d10f3d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338341277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3338341277
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3944653530
Short name T425
Test name
Test status
Simulation time 333196890405 ps
CPU time 86.06 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:43:21 PM PDT 24
Peak memory 201852 kb
Host smart-c81f6b6e-fd6d-4e03-8ce4-87a0c7b8067a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944653530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3944653530
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1699117393
Short name T545
Test name
Test status
Simulation time 175754066843 ps
CPU time 102.59 seconds
Started Jun 29 06:41:58 PM PDT 24
Finished Jun 29 06:43:42 PM PDT 24
Peak memory 201940 kb
Host smart-2214a3a3-78c9-45ee-9411-8b75006b1fdb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699117393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1699117393
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.572154841
Short name T499
Test name
Test status
Simulation time 399363200771 ps
CPU time 964.61 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:58:02 PM PDT 24
Peak memory 201852 kb
Host smart-e47929a8-b8bf-46dc-b51a-ec8d73a24af8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572154841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.572154841
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2829372847
Short name T648
Test name
Test status
Simulation time 21615616794 ps
CPU time 13.17 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:42:08 PM PDT 24
Peak memory 201668 kb
Host smart-5bdf8116-0346-4096-bb65-defcf413a0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829372847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2829372847
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2064846479
Short name T535
Test name
Test status
Simulation time 3029175358 ps
CPU time 2.33 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:41:57 PM PDT 24
Peak memory 201696 kb
Host smart-906034f3-6b77-4edd-9fa9-6011b894140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064846479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2064846479
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3777117226
Short name T70
Test name
Test status
Simulation time 8197346209 ps
CPU time 5.96 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:42:03 PM PDT 24
Peak memory 218188 kb
Host smart-3d77988e-b059-45ae-a843-295f28dfd89e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777117226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3777117226
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.4172717111
Short name T390
Test name
Test status
Simulation time 5788926651 ps
CPU time 14.55 seconds
Started Jun 29 06:41:50 PM PDT 24
Finished Jun 29 06:42:05 PM PDT 24
Peak memory 201692 kb
Host smart-1ff6cf65-80b1-47c8-a267-af4631c779b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172717111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.4172717111
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.202675683
Short name T670
Test name
Test status
Simulation time 178843237271 ps
CPU time 350.37 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:47:50 PM PDT 24
Peak memory 201872 kb
Host smart-84430265-af32-45a5-b93c-41140364b2f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202675683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.202675683
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.344539560
Short name T44
Test name
Test status
Simulation time 422897178 ps
CPU time 0.84 seconds
Started Jun 29 06:42:51 PM PDT 24
Finished Jun 29 06:42:52 PM PDT 24
Peak memory 201624 kb
Host smart-7092d682-7289-4301-a5ed-5fbe9156e0d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344539560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.344539560
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1228507692
Short name T146
Test name
Test status
Simulation time 565157591123 ps
CPU time 726.24 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:54:56 PM PDT 24
Peak memory 201928 kb
Host smart-1f48f1c2-6eb3-4ca2-96d1-4f5224572a44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228507692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1228507692
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3823725336
Short name T749
Test name
Test status
Simulation time 168222958243 ps
CPU time 192.94 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:46:04 PM PDT 24
Peak memory 201884 kb
Host smart-4339d566-1dc5-4947-8ef0-f35a0c096bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823725336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3823725336
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.4244032549
Short name T48
Test name
Test status
Simulation time 492443540566 ps
CPU time 301.04 seconds
Started Jun 29 06:42:51 PM PDT 24
Finished Jun 29 06:47:52 PM PDT 24
Peak memory 201820 kb
Host smart-f099a44d-892c-414a-9255-9b5d383f619c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244032549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.4244032549
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.151663134
Short name T380
Test name
Test status
Simulation time 489233785908 ps
CPU time 1131.48 seconds
Started Jun 29 06:42:41 PM PDT 24
Finished Jun 29 07:01:34 PM PDT 24
Peak memory 201828 kb
Host smart-d75cee74-452f-435f-b03c-9e9b5c322c61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=151663134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.151663134
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3094669326
Short name T773
Test name
Test status
Simulation time 164382584654 ps
CPU time 381.13 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:49:10 PM PDT 24
Peak memory 202104 kb
Host smart-82a5941c-c277-4a71-aff2-1ad9def7358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094669326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3094669326
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1788503127
Short name T676
Test name
Test status
Simulation time 495359631634 ps
CPU time 105 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:44:31 PM PDT 24
Peak memory 201848 kb
Host smart-8d5e5fbd-1a07-451c-9911-8e3cf5da6e30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788503127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1788503127
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2161359124
Short name T251
Test name
Test status
Simulation time 531697653473 ps
CPU time 1193.65 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 07:02:43 PM PDT 24
Peak memory 201884 kb
Host smart-0a2dc960-56b5-48d5-8f19-798aedc081c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161359124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2161359124
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.856451759
Short name T485
Test name
Test status
Simulation time 598542302018 ps
CPU time 369.87 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:48:56 PM PDT 24
Peak memory 201916 kb
Host smart-6891c237-bf33-4f9f-86ca-2999b80fd602
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856451759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.856451759
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3528269647
Short name T209
Test name
Test status
Simulation time 106324893590 ps
CPU time 338.11 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:48:29 PM PDT 24
Peak memory 202192 kb
Host smart-4760cc1c-9409-4ec9-a5b3-d2426f3f2b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528269647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3528269647
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2299412543
Short name T733
Test name
Test status
Simulation time 31837554655 ps
CPU time 33.36 seconds
Started Jun 29 06:42:49 PM PDT 24
Finished Jun 29 06:43:23 PM PDT 24
Peak memory 201672 kb
Host smart-8a8ff783-bb67-4621-98a7-78bf7262a606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299412543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2299412543
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1006534998
Short name T368
Test name
Test status
Simulation time 3839861480 ps
CPU time 8.41 seconds
Started Jun 29 06:42:41 PM PDT 24
Finished Jun 29 06:42:51 PM PDT 24
Peak memory 201660 kb
Host smart-0d877df3-3926-400b-8191-c8bbf1e39e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006534998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1006534998
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.449440832
Short name T678
Test name
Test status
Simulation time 5841685789 ps
CPU time 12.64 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:43:04 PM PDT 24
Peak memory 201676 kb
Host smart-94f90264-64ce-4be6-a157-2a23df5cb943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449440832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.449440832
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.431427118
Short name T287
Test name
Test status
Simulation time 288309639180 ps
CPU time 423.13 seconds
Started Jun 29 06:42:49 PM PDT 24
Finished Jun 29 06:49:53 PM PDT 24
Peak memory 210432 kb
Host smart-8381c85f-7232-4e88-8b0c-d54ade9113b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431427118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
431427118
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1996411128
Short name T635
Test name
Test status
Simulation time 36579145075 ps
CPU time 149.65 seconds
Started Jun 29 06:42:44 PM PDT 24
Finished Jun 29 06:45:15 PM PDT 24
Peak memory 210644 kb
Host smart-22299c70-a510-4e8e-afbe-8f04deee3f7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996411128 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1996411128
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.282012974
Short name T491
Test name
Test status
Simulation time 343122531 ps
CPU time 0.75 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:42:52 PM PDT 24
Peak memory 201624 kb
Host smart-8c7937e2-8265-4486-99db-db4bd9a9fba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282012974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.282012974
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3842478998
Short name T585
Test name
Test status
Simulation time 166049021099 ps
CPU time 91.97 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:44:18 PM PDT 24
Peak memory 201932 kb
Host smart-c2782c61-a6e3-4801-af7b-4690b7d0eff7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842478998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3842478998
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1611490157
Short name T466
Test name
Test status
Simulation time 162643184756 ps
CPU time 182.62 seconds
Started Jun 29 06:42:41 PM PDT 24
Finished Jun 29 06:45:45 PM PDT 24
Peak memory 201884 kb
Host smart-e97aefae-36c2-474a-9869-5e44392222f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611490157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1611490157
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3059832561
Short name T537
Test name
Test status
Simulation time 326131011091 ps
CPU time 193.33 seconds
Started Jun 29 06:42:56 PM PDT 24
Finished Jun 29 06:46:10 PM PDT 24
Peak memory 201828 kb
Host smart-d2a6b402-354e-4e91-95ba-245b29af8572
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059832561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3059832561
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1291209971
Short name T357
Test name
Test status
Simulation time 324185700429 ps
CPU time 349.12 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:48:40 PM PDT 24
Peak memory 201848 kb
Host smart-918a3e04-6a96-4742-9884-bdce7db1f1ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291209971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1291209971
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.662587952
Short name T588
Test name
Test status
Simulation time 203194800693 ps
CPU time 488.58 seconds
Started Jun 29 06:42:46 PM PDT 24
Finished Jun 29 06:50:56 PM PDT 24
Peak memory 201872 kb
Host smart-f69c9a7a-4a72-4dc4-9e7c-7ec7d3825474
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662587952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.662587952
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2820311141
Short name T514
Test name
Test status
Simulation time 393288149039 ps
CPU time 415.37 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:49:45 PM PDT 24
Peak memory 201860 kb
Host smart-14c28733-241a-463b-91c3-1fd41c7ef79e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820311141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2820311141
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1850396668
Short name T206
Test name
Test status
Simulation time 93320471677 ps
CPU time 298.68 seconds
Started Jun 29 06:42:47 PM PDT 24
Finished Jun 29 06:47:46 PM PDT 24
Peak memory 202264 kb
Host smart-855b7218-ca00-4834-b334-32c811ccbf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850396668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1850396668
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2002885933
Short name T394
Test name
Test status
Simulation time 28177760527 ps
CPU time 16.42 seconds
Started Jun 29 06:42:51 PM PDT 24
Finished Jun 29 06:43:08 PM PDT 24
Peak memory 201676 kb
Host smart-9e5319f7-55a0-4a1c-bfb6-c652c640431a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002885933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2002885933
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3484272041
Short name T96
Test name
Test status
Simulation time 5666732617 ps
CPU time 1.37 seconds
Started Jun 29 06:42:46 PM PDT 24
Finished Jun 29 06:42:48 PM PDT 24
Peak memory 201664 kb
Host smart-a12c0953-99a4-47ca-8c99-9342f81907f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484272041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3484272041
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.625178951
Short name T496
Test name
Test status
Simulation time 5677556540 ps
CPU time 4.23 seconds
Started Jun 29 06:42:40 PM PDT 24
Finished Jun 29 06:42:46 PM PDT 24
Peak memory 201672 kb
Host smart-81e3e7e7-f213-4969-b767-2409ba798a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625178951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.625178951
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1045989578
Short name T207
Test name
Test status
Simulation time 421379765711 ps
CPU time 489.31 seconds
Started Jun 29 06:42:42 PM PDT 24
Finished Jun 29 06:50:52 PM PDT 24
Peak memory 202228 kb
Host smart-f8d28a16-6869-4e2f-9b73-97c609a0f08b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045989578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1045989578
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2945050157
Short name T243
Test name
Test status
Simulation time 71015691435 ps
CPU time 118.38 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:44:47 PM PDT 24
Peak memory 210560 kb
Host smart-e737a97c-529c-4f59-8399-ea8c90254c64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945050157 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2945050157
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.97436454
Short name T583
Test name
Test status
Simulation time 346028462 ps
CPU time 0.83 seconds
Started Jun 29 06:42:54 PM PDT 24
Finished Jun 29 06:42:55 PM PDT 24
Peak memory 201620 kb
Host smart-7f782c82-d952-4d55-bb66-f55510159e1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97436454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.97436454
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3807960329
Short name T137
Test name
Test status
Simulation time 334359140099 ps
CPU time 384.85 seconds
Started Jun 29 06:42:54 PM PDT 24
Finished Jun 29 06:49:19 PM PDT 24
Peak memory 201872 kb
Host smart-da365f3d-8a8b-40e2-9c79-036a2028d7cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807960329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3807960329
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1468186950
Short name T289
Test name
Test status
Simulation time 491856727983 ps
CPU time 193 seconds
Started Jun 29 06:42:49 PM PDT 24
Finished Jun 29 06:46:03 PM PDT 24
Peak memory 201868 kb
Host smart-2146ebe3-eb11-4f55-9e42-7a96e003ae01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468186950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1468186950
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2922431845
Short name T175
Test name
Test status
Simulation time 489529239196 ps
CPU time 306.21 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:47:57 PM PDT 24
Peak memory 201884 kb
Host smart-92beffc1-3322-41e1-9933-17b796a61e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922431845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2922431845
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.4293417770
Short name T690
Test name
Test status
Simulation time 332783574046 ps
CPU time 507.95 seconds
Started Jun 29 06:42:49 PM PDT 24
Finished Jun 29 06:51:18 PM PDT 24
Peak memory 201844 kb
Host smart-a250d9e6-229d-4557-a413-d72c2d415358
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293417770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.4293417770
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3582823980
Short name T429
Test name
Test status
Simulation time 333299100237 ps
CPU time 772.29 seconds
Started Jun 29 06:42:45 PM PDT 24
Finished Jun 29 06:55:39 PM PDT 24
Peak memory 201956 kb
Host smart-28e40358-8408-4743-9cfa-9700ecd26692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582823980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3582823980
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3685616693
Short name T521
Test name
Test status
Simulation time 502710447780 ps
CPU time 1043.31 seconds
Started Jun 29 06:42:54 PM PDT 24
Finished Jun 29 07:00:18 PM PDT 24
Peak memory 201852 kb
Host smart-c67a9774-ea3d-45ce-968a-a4fb97d15735
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685616693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3685616693
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1743845899
Short name T223
Test name
Test status
Simulation time 517973255922 ps
CPU time 304.06 seconds
Started Jun 29 06:42:54 PM PDT 24
Finished Jun 29 06:47:59 PM PDT 24
Peak memory 201936 kb
Host smart-ab2f9f32-b334-44eb-8e26-27efa179127e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743845899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1743845899
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.586256935
Short name T602
Test name
Test status
Simulation time 400751087309 ps
CPU time 249.47 seconds
Started Jun 29 06:42:49 PM PDT 24
Finished Jun 29 06:46:59 PM PDT 24
Peak memory 201864 kb
Host smart-22db10fe-d274-46d2-8b64-c81764e0a59e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586256935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.586256935
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4156526134
Short name T498
Test name
Test status
Simulation time 124241206855 ps
CPU time 694.2 seconds
Started Jun 29 06:43:01 PM PDT 24
Finished Jun 29 06:54:36 PM PDT 24
Peak memory 202188 kb
Host smart-58e3dc83-b7cb-4313-99ed-7b36ed035b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156526134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4156526134
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.126998863
Short name T544
Test name
Test status
Simulation time 34422578920 ps
CPU time 80.86 seconds
Started Jun 29 06:42:51 PM PDT 24
Finished Jun 29 06:44:12 PM PDT 24
Peak memory 201636 kb
Host smart-ce20a480-1fc0-4762-bdba-4030bca01ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126998863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.126998863
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3089351807
Short name T656
Test name
Test status
Simulation time 5345352008 ps
CPU time 12.73 seconds
Started Jun 29 06:42:57 PM PDT 24
Finished Jun 29 06:43:10 PM PDT 24
Peak memory 201680 kb
Host smart-8052a177-da89-4b5b-97c6-c9ea445f34ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089351807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3089351807
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2917878291
Short name T659
Test name
Test status
Simulation time 5918547987 ps
CPU time 7.09 seconds
Started Jun 29 06:42:53 PM PDT 24
Finished Jun 29 06:43:01 PM PDT 24
Peak memory 201676 kb
Host smart-1742b34a-8aaf-4345-bbc9-ed84d704ea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917878291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2917878291
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2554303286
Short name T363
Test name
Test status
Simulation time 19549574693 ps
CPU time 14.55 seconds
Started Jun 29 06:42:50 PM PDT 24
Finished Jun 29 06:43:05 PM PDT 24
Peak memory 201852 kb
Host smart-365d0972-d1d7-460e-9cc2-ac4eab67bd1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554303286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2554303286
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.564529970
Short name T36
Test name
Test status
Simulation time 19875792747 ps
CPU time 44.64 seconds
Started Jun 29 06:42:58 PM PDT 24
Finished Jun 29 06:43:43 PM PDT 24
Peak memory 210128 kb
Host smart-f0a1a203-2091-450b-955c-f572f41564c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564529970 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.564529970
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3843650498
Short name T479
Test name
Test status
Simulation time 517840085 ps
CPU time 0.73 seconds
Started Jun 29 06:43:17 PM PDT 24
Finished Jun 29 06:43:18 PM PDT 24
Peak memory 201840 kb
Host smart-5b80a446-5aee-466d-85d0-f029e5625f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843650498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3843650498
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.4152970827
Short name T732
Test name
Test status
Simulation time 327815407610 ps
CPU time 71.41 seconds
Started Jun 29 06:42:58 PM PDT 24
Finished Jun 29 06:44:10 PM PDT 24
Peak memory 201864 kb
Host smart-69a28877-93bb-446b-8df8-3908887aa485
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152970827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.4152970827
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2943854298
Short name T511
Test name
Test status
Simulation time 458179507384 ps
CPU time 273.2 seconds
Started Jun 29 06:43:00 PM PDT 24
Finished Jun 29 06:47:34 PM PDT 24
Peak memory 201888 kb
Host smart-7fb7850c-d437-40cd-8bd4-3eadad3dd55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943854298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2943854298
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.170438434
Short name T190
Test name
Test status
Simulation time 500808522478 ps
CPU time 306.79 seconds
Started Jun 29 06:42:59 PM PDT 24
Finished Jun 29 06:48:06 PM PDT 24
Peak memory 201920 kb
Host smart-5a3bb2e4-51e6-4a0a-8d75-aec8ccbc7877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170438434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.170438434
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.943173963
Short name T387
Test name
Test status
Simulation time 329033304271 ps
CPU time 161.16 seconds
Started Jun 29 06:42:58 PM PDT 24
Finished Jun 29 06:45:40 PM PDT 24
Peak memory 201864 kb
Host smart-d7099b18-3971-4c4f-9bd4-05e25df88cde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=943173963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.943173963
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1677299689
Short name T139
Test name
Test status
Simulation time 486521131673 ps
CPU time 1020.41 seconds
Started Jun 29 06:42:55 PM PDT 24
Finished Jun 29 06:59:56 PM PDT 24
Peak memory 201920 kb
Host smart-d288194b-1587-4468-b610-54567c833baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677299689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1677299689
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.4278080586
Short name T605
Test name
Test status
Simulation time 491646199641 ps
CPU time 577.01 seconds
Started Jun 29 06:42:57 PM PDT 24
Finished Jun 29 06:52:35 PM PDT 24
Peak memory 201848 kb
Host smart-8d672462-3a4e-47c9-b487-f009075149e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278080586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.4278080586
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1588945694
Short name T145
Test name
Test status
Simulation time 366274866588 ps
CPU time 193.46 seconds
Started Jun 29 06:43:00 PM PDT 24
Finished Jun 29 06:46:14 PM PDT 24
Peak memory 201928 kb
Host smart-a089421b-242d-44b5-b96f-18e01b1fdb84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588945694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1588945694
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3105219650
Short name T757
Test name
Test status
Simulation time 406680743180 ps
CPU time 355.33 seconds
Started Jun 29 06:42:59 PM PDT 24
Finished Jun 29 06:48:54 PM PDT 24
Peak memory 201872 kb
Host smart-d3a2e6f5-e118-4850-9710-c4229f1605bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105219650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3105219650
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3278189301
Short name T531
Test name
Test status
Simulation time 67760178623 ps
CPU time 380.51 seconds
Started Jun 29 06:42:57 PM PDT 24
Finished Jun 29 06:49:18 PM PDT 24
Peak memory 202200 kb
Host smart-94aad130-90b9-47bc-8ee8-f0fa551d1c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278189301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3278189301
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1050422735
Short name T167
Test name
Test status
Simulation time 45212415620 ps
CPU time 26.64 seconds
Started Jun 29 06:42:58 PM PDT 24
Finished Jun 29 06:43:25 PM PDT 24
Peak memory 201628 kb
Host smart-35b71555-f02e-4415-9b2e-6cfc67eea1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050422735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1050422735
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.4288057297
Short name T592
Test name
Test status
Simulation time 4252907614 ps
CPU time 2.93 seconds
Started Jun 29 06:42:59 PM PDT 24
Finished Jun 29 06:43:03 PM PDT 24
Peak memory 201680 kb
Host smart-b0f192c3-b055-4503-86f1-54e4b21ec45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288057297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.4288057297
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3363190998
Short name T453
Test name
Test status
Simulation time 5806849506 ps
CPU time 13.05 seconds
Started Jun 29 06:42:48 PM PDT 24
Finished Jun 29 06:43:02 PM PDT 24
Peak memory 201672 kb
Host smart-a549823f-819e-4408-a9ed-b5d20cb92661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363190998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3363190998
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.901057822
Short name T295
Test name
Test status
Simulation time 524438141473 ps
CPU time 625.86 seconds
Started Jun 29 06:43:15 PM PDT 24
Finished Jun 29 06:53:41 PM PDT 24
Peak memory 201860 kb
Host smart-44e55247-8545-4155-a705-6e2eddd29834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901057822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
901057822
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3359732705
Short name T50
Test name
Test status
Simulation time 28751122584 ps
CPU time 44.21 seconds
Started Jun 29 06:42:57 PM PDT 24
Finished Jun 29 06:43:41 PM PDT 24
Peak memory 210496 kb
Host smart-c96b0d43-ada9-4c94-8b29-f74a85beedce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359732705 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3359732705
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1579474719
Short name T638
Test name
Test status
Simulation time 555135474 ps
CPU time 0.79 seconds
Started Jun 29 06:43:14 PM PDT 24
Finished Jun 29 06:43:15 PM PDT 24
Peak memory 201636 kb
Host smart-aaae7c37-5aac-4ff1-a103-8d6ec62eda7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579474719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1579474719
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.229092631
Short name T177
Test name
Test status
Simulation time 495876143149 ps
CPU time 305.84 seconds
Started Jun 29 06:43:16 PM PDT 24
Finished Jun 29 06:48:22 PM PDT 24
Peak memory 201888 kb
Host smart-d3a495b2-b346-4056-aa7d-06d017a87e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229092631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.229092631
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.868219593
Short name T567
Test name
Test status
Simulation time 158076759232 ps
CPU time 338.3 seconds
Started Jun 29 06:43:15 PM PDT 24
Finished Jun 29 06:48:53 PM PDT 24
Peak memory 201872 kb
Host smart-6161339b-031c-4df4-95fa-cc88558021bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868219593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.868219593
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1685430261
Short name T386
Test name
Test status
Simulation time 340207612277 ps
CPU time 114.1 seconds
Started Jun 29 06:43:14 PM PDT 24
Finished Jun 29 06:45:09 PM PDT 24
Peak memory 201852 kb
Host smart-dbd1ba5c-15cb-44b6-b910-dbdd4b844416
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685430261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1685430261
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1412145734
Short name T307
Test name
Test status
Simulation time 334175735179 ps
CPU time 182.87 seconds
Started Jun 29 06:43:13 PM PDT 24
Finished Jun 29 06:46:16 PM PDT 24
Peak memory 201948 kb
Host smart-f5d277f5-5d8c-4cb2-88ab-57af6e8b7a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412145734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1412145734
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.947999094
Short name T578
Test name
Test status
Simulation time 327196019451 ps
CPU time 201.61 seconds
Started Jun 29 06:43:13 PM PDT 24
Finished Jun 29 06:46:35 PM PDT 24
Peak memory 201852 kb
Host smart-a915da29-4690-4ae7-a13c-f2e280b821c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=947999094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.947999094
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3377237006
Short name T281
Test name
Test status
Simulation time 174218203531 ps
CPU time 105.89 seconds
Started Jun 29 06:43:14 PM PDT 24
Finished Jun 29 06:45:00 PM PDT 24
Peak memory 201928 kb
Host smart-c58b9f2b-e75c-4ca4-8bba-c20fec58e5d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377237006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3377237006
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.4109358115
Short name T726
Test name
Test status
Simulation time 626010560232 ps
CPU time 359.3 seconds
Started Jun 29 06:43:18 PM PDT 24
Finished Jun 29 06:49:17 PM PDT 24
Peak memory 202068 kb
Host smart-fd93dd92-c25e-4d6c-a371-de6a5d39f3f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109358115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.4109358115
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.954804821
Short name T694
Test name
Test status
Simulation time 104946390513 ps
CPU time 614.8 seconds
Started Jun 29 06:43:13 PM PDT 24
Finished Jun 29 06:53:28 PM PDT 24
Peak memory 202244 kb
Host smart-d9f7a3e9-9140-46b3-9bc5-9bfe5259528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954804821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.954804821
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3467404341
Short name T619
Test name
Test status
Simulation time 37861712737 ps
CPU time 22.09 seconds
Started Jun 29 06:43:15 PM PDT 24
Finished Jun 29 06:43:37 PM PDT 24
Peak memory 201680 kb
Host smart-e4eff1e5-d892-4499-b450-f09e63aeaf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467404341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3467404341
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1154382708
Short name T698
Test name
Test status
Simulation time 5443488368 ps
CPU time 14.04 seconds
Started Jun 29 06:43:15 PM PDT 24
Finished Jun 29 06:43:30 PM PDT 24
Peak memory 201692 kb
Host smart-3f4cf355-d70c-41cb-aeaa-2dce0adc2359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154382708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1154382708
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2907462348
Short name T417
Test name
Test status
Simulation time 6004418039 ps
CPU time 3.86 seconds
Started Jun 29 06:43:14 PM PDT 24
Finished Jun 29 06:43:19 PM PDT 24
Peak memory 201680 kb
Host smart-395f001b-d3ae-4419-94a1-99aba6761715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907462348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2907462348
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.279232323
Short name T84
Test name
Test status
Simulation time 167964699485 ps
CPU time 70.01 seconds
Started Jun 29 06:43:14 PM PDT 24
Finished Jun 29 06:44:25 PM PDT 24
Peak memory 201856 kb
Host smart-10fe3248-831b-4b7f-8f8b-5f4e403a143c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279232323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
279232323
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1667485234
Short name T334
Test name
Test status
Simulation time 188739556258 ps
CPU time 107.52 seconds
Started Jun 29 06:43:16 PM PDT 24
Finished Jun 29 06:45:04 PM PDT 24
Peak memory 210252 kb
Host smart-c82a5d10-f523-4e1e-85cc-93042df2c74b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667485234 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1667485234
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1607906186
Short name T382
Test name
Test status
Simulation time 566335010 ps
CPU time 0.68 seconds
Started Jun 29 06:43:20 PM PDT 24
Finished Jun 29 06:43:21 PM PDT 24
Peak memory 201588 kb
Host smart-7dcb8f26-14c2-4f1e-9a7b-1790d444b212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607906186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1607906186
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2140956844
Short name T178
Test name
Test status
Simulation time 324291666414 ps
CPU time 40.76 seconds
Started Jun 29 06:43:13 PM PDT 24
Finished Jun 29 06:43:54 PM PDT 24
Peak memory 201776 kb
Host smart-8f29a6d8-0fdb-48be-b872-e50c84e68a72
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140956844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2140956844
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1749896738
Short name T655
Test name
Test status
Simulation time 356063796710 ps
CPU time 220.12 seconds
Started Jun 29 06:43:16 PM PDT 24
Finished Jun 29 06:46:57 PM PDT 24
Peak memory 201884 kb
Host smart-c0a4215d-16ae-4bfe-a625-e3d4803d5f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749896738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1749896738
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3146000917
Short name T728
Test name
Test status
Simulation time 164112776393 ps
CPU time 387.26 seconds
Started Jun 29 06:43:15 PM PDT 24
Finished Jun 29 06:49:42 PM PDT 24
Peak memory 201848 kb
Host smart-00c23ed7-2f0b-4987-9854-b401cc1e26ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146000917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3146000917
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3929869990
Short name T164
Test name
Test status
Simulation time 168025687303 ps
CPU time 337.89 seconds
Started Jun 29 06:43:17 PM PDT 24
Finished Jun 29 06:48:55 PM PDT 24
Peak memory 201956 kb
Host smart-3f55a259-91f3-49d4-91f4-b8be783a1698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929869990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3929869990
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3893252966
Short name T411
Test name
Test status
Simulation time 324405255177 ps
CPU time 356.29 seconds
Started Jun 29 06:43:16 PM PDT 24
Finished Jun 29 06:49:12 PM PDT 24
Peak memory 201864 kb
Host smart-5f55de2c-eaa9-462e-b35c-c9d5eb49bf15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893252966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3893252966
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1314855659
Short name T662
Test name
Test status
Simulation time 205020770715 ps
CPU time 468.09 seconds
Started Jun 29 06:43:20 PM PDT 24
Finished Jun 29 06:51:09 PM PDT 24
Peak memory 201856 kb
Host smart-4650a3a3-befc-4623-8eb7-9666198171a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314855659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1314855659
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2864169880
Short name T564
Test name
Test status
Simulation time 73869668439 ps
CPU time 272.67 seconds
Started Jun 29 06:43:14 PM PDT 24
Finished Jun 29 06:47:47 PM PDT 24
Peak memory 202200 kb
Host smart-7394ed39-1c58-4153-8b2d-1f323b87fda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864169880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2864169880
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2849703275
Short name T587
Test name
Test status
Simulation time 41187371660 ps
CPU time 47.5 seconds
Started Jun 29 06:43:13 PM PDT 24
Finished Jun 29 06:44:01 PM PDT 24
Peak memory 201664 kb
Host smart-ad142267-5487-439b-89f0-961a136ad78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849703275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2849703275
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3017967367
Short name T452
Test name
Test status
Simulation time 3084119971 ps
CPU time 2.54 seconds
Started Jun 29 06:43:16 PM PDT 24
Finished Jun 29 06:43:19 PM PDT 24
Peak memory 201648 kb
Host smart-e0960519-f93e-4abc-ac94-0704328bd4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017967367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3017967367
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.909859972
Short name T576
Test name
Test status
Simulation time 5792491349 ps
CPU time 7.41 seconds
Started Jun 29 06:43:16 PM PDT 24
Finished Jun 29 06:43:24 PM PDT 24
Peak memory 201680 kb
Host smart-9da0284a-47e6-4971-b414-b13424fb9456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909859972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.909859972
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1410734978
Short name T441
Test name
Test status
Simulation time 340845234367 ps
CPU time 90.96 seconds
Started Jun 29 06:43:16 PM PDT 24
Finished Jun 29 06:44:47 PM PDT 24
Peak memory 201812 kb
Host smart-cefc59e9-8205-46a4-b25b-ac809291653c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410734978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1410734978
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1605977385
Short name T18
Test name
Test status
Simulation time 91662769506 ps
CPU time 79.43 seconds
Started Jun 29 06:43:16 PM PDT 24
Finished Jun 29 06:44:36 PM PDT 24
Peak memory 216828 kb
Host smart-4fef1c4f-15da-4dab-a356-2a0e2a281be5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605977385 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1605977385
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.653547305
Short name T449
Test name
Test status
Simulation time 457633779 ps
CPU time 1.66 seconds
Started Jun 29 06:43:20 PM PDT 24
Finished Jun 29 06:43:21 PM PDT 24
Peak memory 201576 kb
Host smart-845fcfa5-4763-4ea4-9926-a94dfdeb13e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653547305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.653547305
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1098000288
Short name T730
Test name
Test status
Simulation time 546447084407 ps
CPU time 1194.68 seconds
Started Jun 29 06:43:22 PM PDT 24
Finished Jun 29 07:03:18 PM PDT 24
Peak memory 201868 kb
Host smart-f42bf2a8-60de-4739-9672-797b4ec34eb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098000288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1098000288
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1375537990
Short name T468
Test name
Test status
Simulation time 161468486824 ps
CPU time 303.53 seconds
Started Jun 29 06:43:23 PM PDT 24
Finished Jun 29 06:48:27 PM PDT 24
Peak memory 201888 kb
Host smart-c86d6e93-6d11-4446-b47e-372468b98bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375537990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1375537990
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4072926489
Short name T140
Test name
Test status
Simulation time 325787543616 ps
CPU time 772.08 seconds
Started Jun 29 06:43:21 PM PDT 24
Finished Jun 29 06:56:14 PM PDT 24
Peak memory 201884 kb
Host smart-5ee7538e-e6c7-42f6-9d13-0bcf549b2406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072926489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4072926489
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2607562219
Short name T505
Test name
Test status
Simulation time 485893481723 ps
CPU time 1003.61 seconds
Started Jun 29 06:43:24 PM PDT 24
Finished Jun 29 07:00:08 PM PDT 24
Peak memory 201908 kb
Host smart-773176ce-ff05-4c64-a264-d2627069d683
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607562219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2607562219
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1589588486
Short name T752
Test name
Test status
Simulation time 164985107832 ps
CPU time 374.47 seconds
Started Jun 29 06:43:20 PM PDT 24
Finished Jun 29 06:49:35 PM PDT 24
Peak memory 201948 kb
Host smart-b661fa07-8d93-4fc5-bfff-67897d763236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589588486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1589588486
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3830112701
Short name T445
Test name
Test status
Simulation time 326748086608 ps
CPU time 793.45 seconds
Started Jun 29 06:43:20 PM PDT 24
Finished Jun 29 06:56:34 PM PDT 24
Peak memory 201852 kb
Host smart-c420bf39-9aba-4c8b-a6ef-217e52925ac5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830112701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3830112701
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1204344795
Short name T781
Test name
Test status
Simulation time 376975159712 ps
CPU time 804.42 seconds
Started Jun 29 06:43:23 PM PDT 24
Finished Jun 29 06:56:48 PM PDT 24
Peak memory 201952 kb
Host smart-32c3d552-9545-458d-ad6d-1f50b5cdf727
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204344795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1204344795
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1735751250
Short name T144
Test name
Test status
Simulation time 193585464430 ps
CPU time 222.65 seconds
Started Jun 29 06:43:21 PM PDT 24
Finished Jun 29 06:47:04 PM PDT 24
Peak memory 201860 kb
Host smart-1231f7d3-b5b4-4513-8421-1e1833586732
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735751250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1735751250
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2820852350
Short name T623
Test name
Test status
Simulation time 129036923889 ps
CPU time 688.88 seconds
Started Jun 29 06:43:20 PM PDT 24
Finished Jun 29 06:54:49 PM PDT 24
Peak memory 202232 kb
Host smart-0ddb08d1-1029-44fd-801b-fe2765c8c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820852350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2820852350
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1841383595
Short name T720
Test name
Test status
Simulation time 27161729337 ps
CPU time 57.17 seconds
Started Jun 29 06:43:23 PM PDT 24
Finished Jun 29 06:44:20 PM PDT 24
Peak memory 201680 kb
Host smart-071e0933-7fd7-4bb1-be12-050a4d171eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841383595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1841383595
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2023352879
Short name T3
Test name
Test status
Simulation time 4936456264 ps
CPU time 3.61 seconds
Started Jun 29 06:43:21 PM PDT 24
Finished Jun 29 06:43:25 PM PDT 24
Peak memory 201680 kb
Host smart-573e6f54-e6a4-4a5c-8317-e4f75e49a996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023352879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2023352879
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.411187215
Short name T418
Test name
Test status
Simulation time 6003491975 ps
CPU time 7.04 seconds
Started Jun 29 06:43:20 PM PDT 24
Finished Jun 29 06:43:27 PM PDT 24
Peak memory 201680 kb
Host smart-1c4ea44e-080e-401b-9025-9c2220b5f1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411187215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.411187215
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.4287171556
Short name T767
Test name
Test status
Simulation time 326857246 ps
CPU time 0.8 seconds
Started Jun 29 06:43:29 PM PDT 24
Finished Jun 29 06:43:30 PM PDT 24
Peak memory 201612 kb
Host smart-7ebd2fa6-097a-4982-a42c-be88d6fd1cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287171556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.4287171556
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2301809170
Short name T266
Test name
Test status
Simulation time 182800635989 ps
CPU time 123.4 seconds
Started Jun 29 06:43:23 PM PDT 24
Finished Jun 29 06:45:26 PM PDT 24
Peak memory 201940 kb
Host smart-f3233837-e12d-4394-8454-e87943ce3a42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301809170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2301809170
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3315626525
Short name T461
Test name
Test status
Simulation time 165121672662 ps
CPU time 175.61 seconds
Started Jun 29 06:43:22 PM PDT 24
Finished Jun 29 06:46:18 PM PDT 24
Peak memory 201888 kb
Host smart-e5838031-6762-433f-9c97-53678abe8836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315626525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3315626525
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.540177042
Short name T156
Test name
Test status
Simulation time 329216673595 ps
CPU time 197.58 seconds
Started Jun 29 06:43:23 PM PDT 24
Finished Jun 29 06:46:41 PM PDT 24
Peak memory 201932 kb
Host smart-c596bfbd-47fa-41fe-91a7-ccfbdb3b0dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540177042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.540177042
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3745510643
Short name T794
Test name
Test status
Simulation time 166979715184 ps
CPU time 411.41 seconds
Started Jun 29 06:43:19 PM PDT 24
Finished Jun 29 06:50:11 PM PDT 24
Peak memory 201852 kb
Host smart-9ee94ddc-3c4e-4989-a2fe-772526a47a0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745510643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3745510643
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1545628716
Short name T322
Test name
Test status
Simulation time 164985020646 ps
CPU time 95.74 seconds
Started Jun 29 06:43:21 PM PDT 24
Finished Jun 29 06:44:57 PM PDT 24
Peak memory 201956 kb
Host smart-e48b0b28-4010-4e9f-a7c6-5cc982126cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545628716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1545628716
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.61440665
Short name T432
Test name
Test status
Simulation time 325740168531 ps
CPU time 189.59 seconds
Started Jun 29 06:43:21 PM PDT 24
Finished Jun 29 06:46:32 PM PDT 24
Peak memory 201852 kb
Host smart-95f060fd-1ad5-4fdf-b37e-34c6fb2c7383
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=61440665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed
.61440665
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.4208924843
Short name T250
Test name
Test status
Simulation time 540343346634 ps
CPU time 1263.69 seconds
Started Jun 29 06:43:23 PM PDT 24
Finished Jun 29 07:04:27 PM PDT 24
Peak memory 201884 kb
Host smart-152badc7-6a85-440f-80c8-4226fe4f0b29
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208924843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.4208924843
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3920249018
Short name T438
Test name
Test status
Simulation time 194112394295 ps
CPU time 426.16 seconds
Started Jun 29 06:43:21 PM PDT 24
Finished Jun 29 06:50:28 PM PDT 24
Peak memory 201852 kb
Host smart-d8cfd621-a0e4-4554-88c9-3cab441b7905
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920249018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3920249018
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1850819601
Short name T709
Test name
Test status
Simulation time 104835390555 ps
CPU time 373.22 seconds
Started Jun 29 06:43:31 PM PDT 24
Finished Jun 29 06:49:45 PM PDT 24
Peak memory 202188 kb
Host smart-a1d6ad22-df7c-4fa7-8530-609a0cbbb596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850819601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1850819601
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1485559483
Short name T194
Test name
Test status
Simulation time 31366660977 ps
CPU time 70.55 seconds
Started Jun 29 06:43:21 PM PDT 24
Finished Jun 29 06:44:32 PM PDT 24
Peak memory 201676 kb
Host smart-b80c5eb8-db09-403e-9b0b-cb611107bb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485559483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1485559483
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2050741685
Short name T389
Test name
Test status
Simulation time 3929351925 ps
CPU time 5.02 seconds
Started Jun 29 06:43:23 PM PDT 24
Finished Jun 29 06:43:28 PM PDT 24
Peak memory 201680 kb
Host smart-4f68b3f8-bfd9-43f5-aad5-07b5efb192db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050741685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2050741685
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2010732468
Short name T454
Test name
Test status
Simulation time 6095020270 ps
CPU time 1.65 seconds
Started Jun 29 06:43:21 PM PDT 24
Finished Jun 29 06:43:23 PM PDT 24
Peak memory 201636 kb
Host smart-02a7ce2e-482a-4086-9fce-9d0c0ce0d7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010732468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2010732468
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2246400340
Short name T502
Test name
Test status
Simulation time 190097331683 ps
CPU time 463.18 seconds
Started Jun 29 06:43:28 PM PDT 24
Finished Jun 29 06:51:11 PM PDT 24
Peak memory 201880 kb
Host smart-aa76aa44-bb06-4173-8b78-d001b5ebd18a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246400340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2246400340
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3117499390
Short name T546
Test name
Test status
Simulation time 437105925 ps
CPU time 1.21 seconds
Started Jun 29 06:43:29 PM PDT 24
Finished Jun 29 06:43:30 PM PDT 24
Peak memory 201644 kb
Host smart-ea35639d-d484-4f80-81d8-9592457cd71f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117499390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3117499390
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2942903280
Short name T719
Test name
Test status
Simulation time 196102477877 ps
CPU time 111.83 seconds
Started Jun 29 06:43:28 PM PDT 24
Finished Jun 29 06:45:20 PM PDT 24
Peak memory 201856 kb
Host smart-df7c528a-0884-4e3b-b170-05106d7d1fce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942903280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2942903280
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1426820895
Short name T716
Test name
Test status
Simulation time 357737658192 ps
CPU time 845.6 seconds
Started Jun 29 06:43:35 PM PDT 24
Finished Jun 29 06:57:41 PM PDT 24
Peak memory 201884 kb
Host smart-e5cab876-bdae-4289-8253-7a2de0141b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426820895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1426820895
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2128301479
Short name T305
Test name
Test status
Simulation time 158702263427 ps
CPU time 348.74 seconds
Started Jun 29 06:43:29 PM PDT 24
Finished Jun 29 06:49:19 PM PDT 24
Peak memory 201940 kb
Host smart-eab3810d-5ddf-494a-83f9-179ea383465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128301479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2128301479
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.970120686
Short name T793
Test name
Test status
Simulation time 326500142124 ps
CPU time 362.43 seconds
Started Jun 29 06:43:28 PM PDT 24
Finished Jun 29 06:49:31 PM PDT 24
Peak memory 201916 kb
Host smart-7b7366b0-ac9a-42e8-a099-524f01517ac0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=970120686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.970120686
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1501362328
Short name T550
Test name
Test status
Simulation time 334219526174 ps
CPU time 624.87 seconds
Started Jun 29 06:43:29 PM PDT 24
Finished Jun 29 06:53:54 PM PDT 24
Peak memory 201888 kb
Host smart-bf4b3283-bd67-45c1-a497-bfac919f3ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501362328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1501362328
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3816319637
Short name T440
Test name
Test status
Simulation time 332334084610 ps
CPU time 793.09 seconds
Started Jun 29 06:43:28 PM PDT 24
Finished Jun 29 06:56:42 PM PDT 24
Peak memory 201760 kb
Host smart-38615120-b83a-401d-861e-b054153c9d94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816319637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3816319637
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1010257914
Short name T210
Test name
Test status
Simulation time 129642587839 ps
CPU time 632.76 seconds
Started Jun 29 06:43:28 PM PDT 24
Finished Jun 29 06:54:01 PM PDT 24
Peak memory 202180 kb
Host smart-95ae8d35-74ad-4c02-9692-8bfb8a5fd701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010257914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1010257914
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.69033548
Short name T404
Test name
Test status
Simulation time 26469790519 ps
CPU time 15.36 seconds
Started Jun 29 06:43:29 PM PDT 24
Finished Jun 29 06:43:45 PM PDT 24
Peak memory 201688 kb
Host smart-edaac174-04a8-4e3e-8452-d122ce76552b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69033548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.69033548
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3849090641
Short name T465
Test name
Test status
Simulation time 4434002240 ps
CPU time 2.85 seconds
Started Jun 29 06:43:31 PM PDT 24
Finished Jun 29 06:43:34 PM PDT 24
Peak memory 201668 kb
Host smart-ff9fe190-4fc9-4d87-a493-c67d274e0689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849090641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3849090641
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3096416031
Short name T551
Test name
Test status
Simulation time 5548652774 ps
CPU time 12.94 seconds
Started Jun 29 06:43:29 PM PDT 24
Finished Jun 29 06:43:43 PM PDT 24
Peak memory 201672 kb
Host smart-fab1e410-209e-41c0-a359-5707d0a57a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096416031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3096416031
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2783550800
Short name T398
Test name
Test status
Simulation time 6937655873 ps
CPU time 4.83 seconds
Started Jun 29 06:43:29 PM PDT 24
Finished Jun 29 06:43:34 PM PDT 24
Peak memory 201680 kb
Host smart-26d7b687-120b-49e5-8899-c13e40ab7821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783550800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2783550800
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1243169031
Short name T630
Test name
Test status
Simulation time 105788499235 ps
CPU time 22.36 seconds
Started Jun 29 06:43:29 PM PDT 24
Finished Jun 29 06:43:52 PM PDT 24
Peak memory 202020 kb
Host smart-bb93ac49-afb8-4d09-a9c8-c37beca01992
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243169031 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1243169031
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3192856430
Short name T392
Test name
Test status
Simulation time 435015800 ps
CPU time 1.05 seconds
Started Jun 29 06:43:36 PM PDT 24
Finished Jun 29 06:43:37 PM PDT 24
Peak memory 201640 kb
Host smart-26117663-f9a4-4f9e-b6ea-fdca45596880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192856430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3192856430
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.663056706
Short name T299
Test name
Test status
Simulation time 531237470551 ps
CPU time 1194.37 seconds
Started Jun 29 06:43:38 PM PDT 24
Finished Jun 29 07:03:33 PM PDT 24
Peak memory 201920 kb
Host smart-d66fd434-e614-448c-a906-be5d9aaa3930
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663056706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.663056706
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3389117005
Short name T46
Test name
Test status
Simulation time 326198087612 ps
CPU time 397.59 seconds
Started Jun 29 06:43:39 PM PDT 24
Finished Jun 29 06:50:17 PM PDT 24
Peak memory 201876 kb
Host smart-3cfd96dd-ab4a-4a9a-a78c-667450ffadc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389117005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3389117005
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.223806812
Short name T323
Test name
Test status
Simulation time 159243882777 ps
CPU time 254.54 seconds
Started Jun 29 06:43:41 PM PDT 24
Finished Jun 29 06:47:56 PM PDT 24
Peak memory 201832 kb
Host smart-1842ee9a-dced-4db7-bae9-5569f0c8f62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223806812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.223806812
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.160798487
Short name T743
Test name
Test status
Simulation time 162889645806 ps
CPU time 79.72 seconds
Started Jun 29 06:43:35 PM PDT 24
Finished Jun 29 06:44:55 PM PDT 24
Peak memory 201852 kb
Host smart-b68c7d7b-efaf-4bfa-bbfc-c7317c23010d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=160798487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.160798487
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2365137972
Short name T153
Test name
Test status
Simulation time 495205448418 ps
CPU time 1033.52 seconds
Started Jun 29 06:43:36 PM PDT 24
Finished Jun 29 07:00:50 PM PDT 24
Peak memory 201892 kb
Host smart-5aa6071c-84bb-468d-9c93-be542761d659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365137972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2365137972
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3031914594
Short name T647
Test name
Test status
Simulation time 487781221183 ps
CPU time 1152.66 seconds
Started Jun 29 06:43:38 PM PDT 24
Finished Jun 29 07:02:51 PM PDT 24
Peak memory 201856 kb
Host smart-bac0e8fb-0317-481a-84a3-bc724722bc15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031914594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3031914594
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.707139438
Short name T240
Test name
Test status
Simulation time 359926503610 ps
CPU time 812.31 seconds
Started Jun 29 06:43:40 PM PDT 24
Finished Jun 29 06:57:12 PM PDT 24
Peak memory 201576 kb
Host smart-28652e97-6135-4c72-965b-db86972e48ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707139438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.707139438
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3178999062
Short name T769
Test name
Test status
Simulation time 585183227658 ps
CPU time 109.53 seconds
Started Jun 29 06:43:36 PM PDT 24
Finished Jun 29 06:45:26 PM PDT 24
Peak memory 201856 kb
Host smart-26243186-71ed-4e3d-9f17-dce36d63a353
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178999062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3178999062
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.107349208
Short name T572
Test name
Test status
Simulation time 78022123066 ps
CPU time 283.37 seconds
Started Jun 29 06:43:37 PM PDT 24
Finished Jun 29 06:48:21 PM PDT 24
Peak memory 202196 kb
Host smart-5d5c94a8-23dd-429d-8fb0-c6bd668b772e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107349208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.107349208
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.48325580
Short name T617
Test name
Test status
Simulation time 25984921240 ps
CPU time 53.33 seconds
Started Jun 29 06:43:36 PM PDT 24
Finished Jun 29 06:44:30 PM PDT 24
Peak memory 201676 kb
Host smart-d339a0ec-0e38-466f-9828-8d501d21f7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48325580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.48325580
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1915971829
Short name T42
Test name
Test status
Simulation time 2872771434 ps
CPU time 2.32 seconds
Started Jun 29 06:43:37 PM PDT 24
Finished Jun 29 06:43:40 PM PDT 24
Peak memory 201692 kb
Host smart-279985b4-e816-4752-9b20-046a14bd28ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915971829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1915971829
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2203115811
Short name T715
Test name
Test status
Simulation time 5871599047 ps
CPU time 8.3 seconds
Started Jun 29 06:43:29 PM PDT 24
Finished Jun 29 06:43:38 PM PDT 24
Peak memory 201672 kb
Host smart-3024d7ca-78f7-43f0-887f-1eb045b2e666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203115811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2203115811
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1770684526
Short name T346
Test name
Test status
Simulation time 177429997929 ps
CPU time 131.85 seconds
Started Jun 29 06:43:40 PM PDT 24
Finished Jun 29 06:45:52 PM PDT 24
Peak memory 201640 kb
Host smart-b9418c5c-6ee1-4db6-8563-47daf152192a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770684526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1770684526
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3821846675
Short name T94
Test name
Test status
Simulation time 125848549661 ps
CPU time 223.88 seconds
Started Jun 29 06:43:36 PM PDT 24
Finished Jun 29 06:47:20 PM PDT 24
Peak memory 218760 kb
Host smart-73202aef-ca56-4834-b92a-e2580781642c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821846675 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3821846675
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1118001409
Short name T400
Test name
Test status
Simulation time 496562958 ps
CPU time 1.36 seconds
Started Jun 29 06:42:05 PM PDT 24
Finished Jun 29 06:42:07 PM PDT 24
Peak memory 201628 kb
Host smart-5e0be47f-c3e8-4d5d-820d-4b98105d4d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118001409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1118001409
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1614454731
Short name T263
Test name
Test status
Simulation time 161854495901 ps
CPU time 97.04 seconds
Started Jun 29 06:42:06 PM PDT 24
Finished Jun 29 06:43:43 PM PDT 24
Peak memory 201856 kb
Host smart-8f08a537-f113-47c9-a7dd-6e76719750a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614454731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1614454731
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3247926883
Short name T330
Test name
Test status
Simulation time 169359086466 ps
CPU time 199.92 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:45:12 PM PDT 24
Peak memory 201960 kb
Host smart-fd4e122f-cba6-47f1-a915-5bb1122b87e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247926883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3247926883
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1589031612
Short name T297
Test name
Test status
Simulation time 325562300270 ps
CPU time 195.53 seconds
Started Jun 29 06:42:12 PM PDT 24
Finished Jun 29 06:45:28 PM PDT 24
Peak memory 201860 kb
Host smart-22614278-4588-4959-9039-338c67646c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589031612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1589031612
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.136528315
Short name T669
Test name
Test status
Simulation time 506034135426 ps
CPU time 553.32 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:51:06 PM PDT 24
Peak memory 201836 kb
Host smart-8a863c49-7c99-4d74-a977-fb79ea430445
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=136528315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.136528315
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1977000212
Short name T128
Test name
Test status
Simulation time 489977615569 ps
CPU time 284.05 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:46:39 PM PDT 24
Peak memory 201876 kb
Host smart-5c91ba11-287e-45b5-9f89-c81c6d61f604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977000212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1977000212
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2068570950
Short name T620
Test name
Test status
Simulation time 493709365124 ps
CPU time 111.5 seconds
Started Jun 29 06:41:59 PM PDT 24
Finished Jun 29 06:43:52 PM PDT 24
Peak memory 201856 kb
Host smart-9abc85f7-a3c8-42bb-abbb-f60cb5925493
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068570950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2068570950
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3239431961
Short name T500
Test name
Test status
Simulation time 232304517253 ps
CPU time 415.63 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:48:52 PM PDT 24
Peak memory 201884 kb
Host smart-fa783dad-9a35-4f9e-b422-b61313e32618
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239431961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3239431961
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1782142054
Short name T644
Test name
Test status
Simulation time 198832844937 ps
CPU time 228.55 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:45:45 PM PDT 24
Peak memory 201836 kb
Host smart-d2499706-0b37-4d73-9bf9-e9d0d6a07b62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782142054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1782142054
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1448908224
Short name T58
Test name
Test status
Simulation time 138939958101 ps
CPU time 553.68 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:51:08 PM PDT 24
Peak memory 202104 kb
Host smart-79312377-3d15-4a61-95ad-965623866593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448908224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1448908224
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1437333340
Short name T376
Test name
Test status
Simulation time 26890344289 ps
CPU time 30.77 seconds
Started Jun 29 06:41:50 PM PDT 24
Finished Jun 29 06:42:22 PM PDT 24
Peak memory 201696 kb
Host smart-6121af79-c61a-4339-b1fe-919983f6440d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437333340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1437333340
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.484803115
Short name T750
Test name
Test status
Simulation time 3847330192 ps
CPU time 9.76 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:42:05 PM PDT 24
Peak memory 201684 kb
Host smart-7f88abb6-66cd-476d-a795-237be28490a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484803115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.484803115
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2608806716
Short name T82
Test name
Test status
Simulation time 7844360647 ps
CPU time 9.25 seconds
Started Jun 29 06:41:48 PM PDT 24
Finished Jun 29 06:41:58 PM PDT 24
Peak memory 217112 kb
Host smart-d71413cb-264c-4637-84b8-7ee209b93693
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608806716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2608806716
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2977676909
Short name T527
Test name
Test status
Simulation time 5876071272 ps
CPU time 2.36 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:42:00 PM PDT 24
Peak memory 201696 kb
Host smart-6a6ec6b3-80f8-4ce3-9799-424d05a0f6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977676909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2977676909
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1466814764
Short name T211
Test name
Test status
Simulation time 257077514358 ps
CPU time 553.11 seconds
Started Jun 29 06:42:09 PM PDT 24
Finished Jun 29 06:51:22 PM PDT 24
Peak memory 202192 kb
Host smart-a2b07c6d-c66b-4541-b84d-5f7afeae8d2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466814764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1466814764
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3758225714
Short name T422
Test name
Test status
Simulation time 290418212 ps
CPU time 1.08 seconds
Started Jun 29 06:43:45 PM PDT 24
Finished Jun 29 06:43:47 PM PDT 24
Peak memory 201628 kb
Host smart-50c4832f-4ef9-4721-8a24-c5f288abbd9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758225714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3758225714
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1660210608
Short name T759
Test name
Test status
Simulation time 347570292402 ps
CPU time 387.33 seconds
Started Jun 29 06:43:45 PM PDT 24
Finished Jun 29 06:50:13 PM PDT 24
Peak memory 201868 kb
Host smart-2905fbee-c4e3-4412-b8ce-6a3021a38702
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660210608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1660210608
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.908517955
Short name T294
Test name
Test status
Simulation time 165305368817 ps
CPU time 397.92 seconds
Started Jun 29 06:43:46 PM PDT 24
Finished Jun 29 06:50:24 PM PDT 24
Peak memory 201944 kb
Host smart-f9a81e8f-f07b-43f8-8901-3d636e745095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908517955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.908517955
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2187847519
Short name T533
Test name
Test status
Simulation time 167289072872 ps
CPU time 73.43 seconds
Started Jun 29 06:43:45 PM PDT 24
Finished Jun 29 06:44:58 PM PDT 24
Peak memory 201904 kb
Host smart-868d86dd-4c05-439c-a1fc-10d444980ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187847519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2187847519
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.703067265
Short name T165
Test name
Test status
Simulation time 329682907203 ps
CPU time 418.18 seconds
Started Jun 29 06:43:44 PM PDT 24
Finished Jun 29 06:50:43 PM PDT 24
Peak memory 201852 kb
Host smart-7be9da4a-8195-482e-a25b-39162d27562e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=703067265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.703067265
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1435994839
Short name T684
Test name
Test status
Simulation time 319243546294 ps
CPU time 776.48 seconds
Started Jun 29 06:43:37 PM PDT 24
Finished Jun 29 06:56:34 PM PDT 24
Peak memory 201892 kb
Host smart-950a4484-7481-4f4c-8c3e-ecd5561edfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435994839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1435994839
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2542751500
Short name T777
Test name
Test status
Simulation time 162534206143 ps
CPU time 48.97 seconds
Started Jun 29 06:43:40 PM PDT 24
Finished Jun 29 06:44:29 PM PDT 24
Peak memory 201880 kb
Host smart-36c3b620-97e8-4f86-ac2e-6f54f06ab2d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542751500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2542751500
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1823104308
Short name T47
Test name
Test status
Simulation time 467181297643 ps
CPU time 1103.03 seconds
Started Jun 29 06:43:48 PM PDT 24
Finished Jun 29 07:02:12 PM PDT 24
Peak memory 201708 kb
Host smart-ed70bf95-d5a2-4532-8fab-5634acd93fa2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823104308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1823104308
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4016071866
Short name T598
Test name
Test status
Simulation time 203811849916 ps
CPU time 391.89 seconds
Started Jun 29 06:43:46 PM PDT 24
Finished Jun 29 06:50:18 PM PDT 24
Peak memory 201912 kb
Host smart-821a98be-ba10-4a97-9114-25f83f11329a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016071866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4016071866
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1898761789
Short name T203
Test name
Test status
Simulation time 70226877295 ps
CPU time 396.18 seconds
Started Jun 29 06:43:45 PM PDT 24
Finished Jun 29 06:50:21 PM PDT 24
Peak memory 202200 kb
Host smart-89f4c6bf-8f84-4e15-8002-c53b4e9c3619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898761789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1898761789
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3663411994
Short name T424
Test name
Test status
Simulation time 35245451998 ps
CPU time 20.92 seconds
Started Jun 29 06:43:44 PM PDT 24
Finished Jun 29 06:44:06 PM PDT 24
Peak memory 201640 kb
Host smart-178f0c70-95f6-4aa9-ab80-312c22912d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663411994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3663411994
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3999957446
Short name T508
Test name
Test status
Simulation time 3577212794 ps
CPU time 5.84 seconds
Started Jun 29 06:43:48 PM PDT 24
Finished Jun 29 06:43:54 PM PDT 24
Peak memory 201516 kb
Host smart-451ef645-d057-439c-8097-eb5751ec5d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999957446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3999957446
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1544031210
Short name T494
Test name
Test status
Simulation time 6002214330 ps
CPU time 13.58 seconds
Started Jun 29 06:43:37 PM PDT 24
Finished Jun 29 06:43:51 PM PDT 24
Peak memory 201672 kb
Host smart-5b922d96-0ec7-41b6-847b-21a4d4a172e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544031210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1544031210
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2692920627
Short name T765
Test name
Test status
Simulation time 163489463258 ps
CPU time 345.99 seconds
Started Jun 29 06:43:45 PM PDT 24
Finished Jun 29 06:49:31 PM PDT 24
Peak memory 201924 kb
Host smart-e32e82ad-e853-4dbe-bf6f-14e9f8d84083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692920627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2692920627
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.705238698
Short name T89
Test name
Test status
Simulation time 447320033 ps
CPU time 1.67 seconds
Started Jun 29 06:44:00 PM PDT 24
Finished Jun 29 06:44:02 PM PDT 24
Peak memory 201588 kb
Host smart-432cfb34-c1ec-4e87-8210-7af5837271b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705238698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.705238698
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2620526920
Short name T601
Test name
Test status
Simulation time 185639144204 ps
CPU time 380.35 seconds
Started Jun 29 06:43:54 PM PDT 24
Finished Jun 29 06:50:15 PM PDT 24
Peak memory 201872 kb
Host smart-43ada406-4c4f-4f28-a0fe-5df83da7f150
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620526920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2620526920
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3280018551
Short name T172
Test name
Test status
Simulation time 494311936416 ps
CPU time 969.6 seconds
Started Jun 29 06:43:52 PM PDT 24
Finished Jun 29 07:00:02 PM PDT 24
Peak memory 201904 kb
Host smart-fdd2ca2e-30ed-46ac-9280-aad725e78248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280018551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3280018551
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3757700163
Short name T166
Test name
Test status
Simulation time 161754215766 ps
CPU time 104.81 seconds
Started Jun 29 06:43:51 PM PDT 24
Finished Jun 29 06:45:37 PM PDT 24
Peak memory 201864 kb
Host smart-3dfd58e3-eb47-4ce5-b614-f501b1346a18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757700163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3757700163
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2788962668
Short name T548
Test name
Test status
Simulation time 493538236387 ps
CPU time 196.47 seconds
Started Jun 29 06:43:48 PM PDT 24
Finished Jun 29 06:47:05 PM PDT 24
Peak memory 201888 kb
Host smart-464c7220-35f7-47d0-ae7c-eb1c7b2adcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788962668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2788962668
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.374223994
Short name T443
Test name
Test status
Simulation time 487855943537 ps
CPU time 549.44 seconds
Started Jun 29 06:43:51 PM PDT 24
Finished Jun 29 06:53:01 PM PDT 24
Peak memory 201848 kb
Host smart-40d6d017-ba6e-4d7d-a2ea-fbe2b60620f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=374223994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.374223994
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1761977349
Short name T687
Test name
Test status
Simulation time 391641563386 ps
CPU time 439.81 seconds
Started Jun 29 06:43:55 PM PDT 24
Finished Jun 29 06:51:15 PM PDT 24
Peak memory 201828 kb
Host smart-9a8e4938-692b-44be-8c6b-63906816ceda
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761977349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1761977349
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2926638748
Short name T721
Test name
Test status
Simulation time 88162195624 ps
CPU time 446.61 seconds
Started Jun 29 06:43:57 PM PDT 24
Finished Jun 29 06:51:24 PM PDT 24
Peak memory 202196 kb
Host smart-31699e37-1696-4b24-9d96-dcd3f278ec6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926638748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2926638748
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1741857808
Short name T725
Test name
Test status
Simulation time 23833089253 ps
CPU time 37.93 seconds
Started Jun 29 06:43:52 PM PDT 24
Finished Jun 29 06:44:31 PM PDT 24
Peak memory 201688 kb
Host smart-069e2bef-79d1-461e-9552-e4ce787086ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741857808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1741857808
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.4109699488
Short name T516
Test name
Test status
Simulation time 4092710988 ps
CPU time 9.75 seconds
Started Jun 29 06:43:51 PM PDT 24
Finished Jun 29 06:44:01 PM PDT 24
Peak memory 201676 kb
Host smart-44a332ca-e584-43b2-9cf3-50adaaa0cf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109699488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.4109699488
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1287076504
Short name T517
Test name
Test status
Simulation time 5883611850 ps
CPU time 2.03 seconds
Started Jun 29 06:43:46 PM PDT 24
Finished Jun 29 06:43:48 PM PDT 24
Peak memory 201908 kb
Host smart-0d81650f-5cb0-43c9-b292-3c814955e89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287076504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1287076504
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1723138667
Short name T561
Test name
Test status
Simulation time 497843747054 ps
CPU time 380.17 seconds
Started Jun 29 06:44:04 PM PDT 24
Finished Jun 29 06:50:25 PM PDT 24
Peak memory 201876 kb
Host smart-2db39582-1fc4-404f-bbc6-25bc086d2727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723138667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1723138667
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.721721980
Short name T626
Test name
Test status
Simulation time 258066380772 ps
CPU time 147.92 seconds
Started Jun 29 06:43:53 PM PDT 24
Finished Jun 29 06:46:21 PM PDT 24
Peak memory 210232 kb
Host smart-77db2e94-13d3-4b88-9e43-60dbfbc7313d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721721980 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.721721980
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.950990075
Short name T645
Test name
Test status
Simulation time 420920651 ps
CPU time 0.87 seconds
Started Jun 29 06:44:03 PM PDT 24
Finished Jun 29 06:44:04 PM PDT 24
Peak memory 201616 kb
Host smart-b482b2b9-1e5c-4922-9e55-f26caf0cb815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950990075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.950990075
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2533312383
Short name T575
Test name
Test status
Simulation time 331323278845 ps
CPU time 170.6 seconds
Started Jun 29 06:44:00 PM PDT 24
Finished Jun 29 06:46:51 PM PDT 24
Peak memory 201848 kb
Host smart-aba7bb0a-b502-4a00-a800-b941b7fece4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533312383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2533312383
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3830627386
Short name T795
Test name
Test status
Simulation time 508277562625 ps
CPU time 1236.49 seconds
Started Jun 29 06:43:58 PM PDT 24
Finished Jun 29 07:04:35 PM PDT 24
Peak memory 201960 kb
Host smart-bf071a7d-9c6f-4a26-8fa2-2297652c56ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830627386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3830627386
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2500209994
Short name T336
Test name
Test status
Simulation time 160175660331 ps
CPU time 109.61 seconds
Started Jun 29 06:44:00 PM PDT 24
Finished Jun 29 06:45:50 PM PDT 24
Peak memory 201872 kb
Host smart-194e8c70-ba13-4c11-bb93-a2d2237164fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500209994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2500209994
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3596952930
Short name T784
Test name
Test status
Simulation time 490094711475 ps
CPU time 606.14 seconds
Started Jun 29 06:44:04 PM PDT 24
Finished Jun 29 06:54:10 PM PDT 24
Peak memory 201824 kb
Host smart-c6c5264a-4587-4438-988e-3520bfbe39c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596952930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3596952930
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2282330043
Short name T369
Test name
Test status
Simulation time 162116948405 ps
CPU time 339.46 seconds
Started Jun 29 06:44:01 PM PDT 24
Finished Jun 29 06:49:41 PM PDT 24
Peak memory 201816 kb
Host smart-5c787d1f-405c-4343-869b-ee2ba8bcc54b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282330043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2282330043
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3590337571
Short name T501
Test name
Test status
Simulation time 183025717399 ps
CPU time 98.34 seconds
Started Jun 29 06:44:04 PM PDT 24
Finished Jun 29 06:45:43 PM PDT 24
Peak memory 201832 kb
Host smart-cb2838de-4ea8-43d9-8db4-63ac30d44303
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590337571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3590337571
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3321145285
Short name T710
Test name
Test status
Simulation time 396407610716 ps
CPU time 979.33 seconds
Started Jun 29 06:44:02 PM PDT 24
Finished Jun 29 07:00:22 PM PDT 24
Peak memory 201920 kb
Host smart-0c3d9b53-ec69-4d97-9e2f-f993caca3785
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321145285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3321145285
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1455859234
Short name T217
Test name
Test status
Simulation time 137646760181 ps
CPU time 484.29 seconds
Started Jun 29 06:44:01 PM PDT 24
Finished Jun 29 06:52:06 PM PDT 24
Peak memory 202260 kb
Host smart-e0193808-67a5-439a-8f84-eab8f72e3415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455859234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1455859234
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.60922602
Short name T507
Test name
Test status
Simulation time 45030784720 ps
CPU time 24.47 seconds
Started Jun 29 06:44:01 PM PDT 24
Finished Jun 29 06:44:26 PM PDT 24
Peak memory 201636 kb
Host smart-bd6527e8-5213-4519-86fa-6060f1e2feaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60922602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.60922602
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1438933664
Short name T522
Test name
Test status
Simulation time 5287113848 ps
CPU time 6.73 seconds
Started Jun 29 06:44:01 PM PDT 24
Finished Jun 29 06:44:08 PM PDT 24
Peak memory 201676 kb
Host smart-9a538aca-a165-40dd-88bf-078364a1f6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438933664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1438933664
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2000106763
Short name T102
Test name
Test status
Simulation time 5883527891 ps
CPU time 4.26 seconds
Started Jun 29 06:44:00 PM PDT 24
Finished Jun 29 06:44:04 PM PDT 24
Peak memory 201672 kb
Host smart-d7bad34a-f8e5-4eed-9d68-294d245819ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000106763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2000106763
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.945491568
Short name T11
Test name
Test status
Simulation time 369806837788 ps
CPU time 777.33 seconds
Started Jun 29 06:44:02 PM PDT 24
Finished Jun 29 06:56:59 PM PDT 24
Peak memory 201880 kb
Host smart-b04f0132-ab9d-40ef-a633-fdbfa56229be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945491568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
945491568
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2497195552
Short name T105
Test name
Test status
Simulation time 441172085506 ps
CPU time 299.75 seconds
Started Jun 29 06:44:01 PM PDT 24
Finished Jun 29 06:49:01 PM PDT 24
Peak memory 218316 kb
Host smart-5cf94ab6-3f79-43a3-9c65-26cdf54ae69e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497195552 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2497195552
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4274871360
Short name T556
Test name
Test status
Simulation time 307685580 ps
CPU time 0.81 seconds
Started Jun 29 06:44:11 PM PDT 24
Finished Jun 29 06:44:12 PM PDT 24
Peak memory 201528 kb
Host smart-e07cbced-e9ac-4e98-bc01-4a60fc567a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274871360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4274871360
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.413302239
Short name T245
Test name
Test status
Simulation time 163830412590 ps
CPU time 164.94 seconds
Started Jun 29 06:44:11 PM PDT 24
Finished Jun 29 06:46:56 PM PDT 24
Peak memory 201924 kb
Host smart-17987b3f-099e-455e-a980-3f04b1342461
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413302239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.413302239
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.803482227
Short name T338
Test name
Test status
Simulation time 433488695714 ps
CPU time 832.4 seconds
Started Jun 29 06:44:09 PM PDT 24
Finished Jun 29 06:58:02 PM PDT 24
Peak memory 201900 kb
Host smart-404cc141-9b19-45f7-91b3-7b9bf18d21e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803482227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.803482227
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3747012868
Short name T324
Test name
Test status
Simulation time 328329421443 ps
CPU time 679.29 seconds
Started Jun 29 06:44:00 PM PDT 24
Finished Jun 29 06:55:19 PM PDT 24
Peak memory 201868 kb
Host smart-d3c684fd-1831-4c46-b6f0-27264bd7da7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747012868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3747012868
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1586281214
Short name T29
Test name
Test status
Simulation time 166020778706 ps
CPU time 398.88 seconds
Started Jun 29 06:43:59 PM PDT 24
Finished Jun 29 06:50:38 PM PDT 24
Peak memory 201836 kb
Host smart-9590f8d7-6554-4463-afa2-75cf067b50e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586281214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1586281214
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1008563897
Short name T685
Test name
Test status
Simulation time 168447709352 ps
CPU time 196.2 seconds
Started Jun 29 06:44:01 PM PDT 24
Finished Jun 29 06:47:17 PM PDT 24
Peak memory 201892 kb
Host smart-fa4806e2-a878-4b72-ba0e-2e7179ee7ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008563897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1008563897
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1298441418
Short name T589
Test name
Test status
Simulation time 509196361847 ps
CPU time 204.16 seconds
Started Jun 29 06:44:01 PM PDT 24
Finished Jun 29 06:47:26 PM PDT 24
Peak memory 201852 kb
Host smart-d189aae9-75fa-4ef7-81eb-7f8c949ba459
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298441418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1298441418
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.691816893
Short name T790
Test name
Test status
Simulation time 578572947032 ps
CPU time 195.55 seconds
Started Jun 29 06:44:10 PM PDT 24
Finished Jun 29 06:47:26 PM PDT 24
Peak memory 201876 kb
Host smart-d360a408-282a-4d4b-8576-b25b08d49e45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691816893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.691816893
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.774852014
Short name T667
Test name
Test status
Simulation time 609554759973 ps
CPU time 1412.34 seconds
Started Jun 29 06:44:09 PM PDT 24
Finished Jun 29 07:07:42 PM PDT 24
Peak memory 201876 kb
Host smart-c46364ec-3e5e-457d-979e-43fa58a49cf6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774852014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.774852014
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1848192650
Short name T216
Test name
Test status
Simulation time 81761661515 ps
CPU time 511.93 seconds
Started Jun 29 06:44:11 PM PDT 24
Finished Jun 29 06:52:43 PM PDT 24
Peak memory 202236 kb
Host smart-f8e63133-1c6d-486e-8ed7-ca8e2d3c70e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848192650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1848192650
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1205280198
Short name T195
Test name
Test status
Simulation time 32571261374 ps
CPU time 74.76 seconds
Started Jun 29 06:44:12 PM PDT 24
Finished Jun 29 06:45:27 PM PDT 24
Peak memory 201664 kb
Host smart-1735d28e-9f6c-467b-9914-6f929c03cc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205280198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1205280198
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3299742606
Short name T788
Test name
Test status
Simulation time 3137041744 ps
CPU time 8.02 seconds
Started Jun 29 06:44:12 PM PDT 24
Finished Jun 29 06:44:21 PM PDT 24
Peak memory 201692 kb
Host smart-7f7eb1bc-b443-4e6f-8868-b587a9b66aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299742606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3299742606
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2127129671
Short name T778
Test name
Test status
Simulation time 5606380295 ps
CPU time 4.27 seconds
Started Jun 29 06:43:59 PM PDT 24
Finished Jun 29 06:44:04 PM PDT 24
Peak memory 201672 kb
Host smart-044db62e-2280-464a-8e6d-6601373e4882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127129671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2127129671
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.4190284127
Short name T787
Test name
Test status
Simulation time 459730907850 ps
CPU time 902.73 seconds
Started Jun 29 06:44:09 PM PDT 24
Finished Jun 29 06:59:12 PM PDT 24
Peak memory 210376 kb
Host smart-1477fe86-b0e1-40db-ac9a-2bae4c0220c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190284127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.4190284127
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2837007667
Short name T608
Test name
Test status
Simulation time 272558720328 ps
CPU time 162.31 seconds
Started Jun 29 06:44:10 PM PDT 24
Finished Jun 29 06:46:52 PM PDT 24
Peak memory 212312 kb
Host smart-03c52ac5-4d1c-46fa-8018-5e5bde59881f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837007667 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2837007667
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1931810977
Short name T559
Test name
Test status
Simulation time 349854489 ps
CPU time 0.8 seconds
Started Jun 29 06:44:24 PM PDT 24
Finished Jun 29 06:44:25 PM PDT 24
Peak memory 201628 kb
Host smart-0af20257-d47c-44a7-93d0-e2df3dda921f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931810977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1931810977
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.510374238
Short name T557
Test name
Test status
Simulation time 178266203208 ps
CPU time 60.4 seconds
Started Jun 29 06:44:18 PM PDT 24
Finished Jun 29 06:45:19 PM PDT 24
Peak memory 201868 kb
Host smart-df49e4ad-a51b-470a-b057-58c679a19322
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510374238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.510374238
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2228204368
Short name T185
Test name
Test status
Simulation time 333482741419 ps
CPU time 408.07 seconds
Started Jun 29 06:44:17 PM PDT 24
Finished Jun 29 06:51:06 PM PDT 24
Peak memory 201888 kb
Host smart-77f80384-ded4-4b4d-b986-347f5c86fef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228204368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2228204368
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.373256639
Short name T314
Test name
Test status
Simulation time 326732601530 ps
CPU time 704.42 seconds
Started Jun 29 06:44:18 PM PDT 24
Finished Jun 29 06:56:03 PM PDT 24
Peak memory 201896 kb
Host smart-e9c335fd-4c65-485d-bdc3-44a78089be8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373256639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.373256639
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.902301589
Short name T419
Test name
Test status
Simulation time 483125683180 ps
CPU time 361.82 seconds
Started Jun 29 06:44:18 PM PDT 24
Finished Jun 29 06:50:20 PM PDT 24
Peak memory 201860 kb
Host smart-870c10e7-0ed1-4f4a-9e6c-8827f7bf4f31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=902301589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.902301589
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.349760856
Short name T30
Test name
Test status
Simulation time 489995024743 ps
CPU time 557.34 seconds
Started Jun 29 06:44:10 PM PDT 24
Finished Jun 29 06:53:28 PM PDT 24
Peak memory 201932 kb
Host smart-4c9b60e8-4fa9-44d3-bd93-a2cbc65c9077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349760856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.349760856
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.224869487
Short name T611
Test name
Test status
Simulation time 164042993770 ps
CPU time 110.61 seconds
Started Jun 29 06:44:16 PM PDT 24
Finished Jun 29 06:46:07 PM PDT 24
Peak memory 201864 kb
Host smart-03c94f57-b35d-4c6e-be73-ebad5a18107a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=224869487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.224869487
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.4183196244
Short name T87
Test name
Test status
Simulation time 390940686800 ps
CPU time 925.28 seconds
Started Jun 29 06:44:18 PM PDT 24
Finished Jun 29 06:59:43 PM PDT 24
Peak memory 201900 kb
Host smart-c2fa9053-2341-459a-b4ed-cace5b3a74f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183196244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.4183196244
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.88694369
Short name T729
Test name
Test status
Simulation time 98007294396 ps
CPU time 542.07 seconds
Started Jun 29 06:44:17 PM PDT 24
Finished Jun 29 06:53:20 PM PDT 24
Peak memory 202200 kb
Host smart-6d1c7003-0b04-42f1-96d6-d8557602d8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88694369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.88694369
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2655995713
Short name T402
Test name
Test status
Simulation time 35372951203 ps
CPU time 72.3 seconds
Started Jun 29 06:44:17 PM PDT 24
Finished Jun 29 06:45:30 PM PDT 24
Peak memory 201672 kb
Host smart-b08652a8-02af-41fc-881d-2d78874f5af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655995713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2655995713
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1544082286
Short name T183
Test name
Test status
Simulation time 5162345767 ps
CPU time 6.56 seconds
Started Jun 29 06:44:19 PM PDT 24
Finished Jun 29 06:44:26 PM PDT 24
Peak memory 201672 kb
Host smart-ac2c1938-7534-4fbe-b1ef-50fcb078cca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544082286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1544082286
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.904671366
Short name T383
Test name
Test status
Simulation time 5649673720 ps
CPU time 7.08 seconds
Started Jun 29 06:44:11 PM PDT 24
Finished Jun 29 06:44:18 PM PDT 24
Peak memory 201648 kb
Host smart-b72c3806-d994-4a48-8b2a-56c0f31fadcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904671366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.904671366
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3774647043
Short name T262
Test name
Test status
Simulation time 382134085478 ps
CPU time 818.73 seconds
Started Jun 29 06:44:18 PM PDT 24
Finished Jun 29 06:57:58 PM PDT 24
Peak memory 201916 kb
Host smart-f5c41243-078f-4a56-971c-a5a440b4cad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774647043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3774647043
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3873229082
Short name T16
Test name
Test status
Simulation time 62366284504 ps
CPU time 104.04 seconds
Started Jun 29 06:44:18 PM PDT 24
Finished Jun 29 06:46:03 PM PDT 24
Peak memory 210504 kb
Host smart-34bf62ff-9085-4012-b780-031aa8a15747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873229082 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3873229082
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.508618816
Short name T532
Test name
Test status
Simulation time 315540083 ps
CPU time 0.99 seconds
Started Jun 29 06:44:29 PM PDT 24
Finished Jun 29 06:44:30 PM PDT 24
Peak memory 201576 kb
Host smart-85b1003f-e948-4f30-9c0d-0853dac05644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508618816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.508618816
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.984134933
Short name T157
Test name
Test status
Simulation time 349001020052 ps
CPU time 135.12 seconds
Started Jun 29 06:44:26 PM PDT 24
Finished Jun 29 06:46:41 PM PDT 24
Peak memory 201932 kb
Host smart-9fd9dfa2-9b8e-44f8-b5d9-062a07a61baf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984134933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.984134933
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1064713069
Short name T100
Test name
Test status
Simulation time 167398171099 ps
CPU time 116.41 seconds
Started Jun 29 06:44:27 PM PDT 24
Finished Jun 29 06:46:24 PM PDT 24
Peak memory 201948 kb
Host smart-8ce72ef8-b3d0-4783-978a-35284f6cab50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064713069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1064713069
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.801387048
Short name T306
Test name
Test status
Simulation time 494974730100 ps
CPU time 927.61 seconds
Started Jun 29 06:44:25 PM PDT 24
Finished Jun 29 06:59:53 PM PDT 24
Peak memory 201860 kb
Host smart-f578246d-8a83-4f08-bc00-651931f907f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801387048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.801387048
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2835188425
Short name T408
Test name
Test status
Simulation time 338000089551 ps
CPU time 388.52 seconds
Started Jun 29 06:44:27 PM PDT 24
Finished Jun 29 06:50:56 PM PDT 24
Peak memory 201836 kb
Host smart-55bcbb5d-0859-4fbc-a8ea-d3216cb24f6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835188425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2835188425
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3604532725
Short name T138
Test name
Test status
Simulation time 497238251085 ps
CPU time 181.51 seconds
Started Jun 29 06:44:17 PM PDT 24
Finished Jun 29 06:47:19 PM PDT 24
Peak memory 201876 kb
Host smart-f6f53175-fba7-432d-aac0-7ea78202edc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604532725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3604532725
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2529313740
Short name T374
Test name
Test status
Simulation time 494173575811 ps
CPU time 431.51 seconds
Started Jun 29 06:44:26 PM PDT 24
Finished Jun 29 06:51:38 PM PDT 24
Peak memory 201852 kb
Host smart-44973b19-fa89-4f07-ba81-4a6f285c4cd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529313740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2529313740
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.397203514
Short name T596
Test name
Test status
Simulation time 169688129196 ps
CPU time 108.55 seconds
Started Jun 29 06:44:26 PM PDT 24
Finished Jun 29 06:46:15 PM PDT 24
Peak memory 201896 kb
Host smart-df0eba68-64bf-4a40-a8f6-5a88e02a1833
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397203514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.397203514
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2153238888
Short name T196
Test name
Test status
Simulation time 205057414498 ps
CPU time 292.76 seconds
Started Jun 29 06:44:27 PM PDT 24
Finished Jun 29 06:49:20 PM PDT 24
Peak memory 201836 kb
Host smart-ca1cd01a-89d7-4ba1-9c1c-f991312fd977
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153238888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2153238888
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3407377556
Short name T57
Test name
Test status
Simulation time 114423452329 ps
CPU time 634.16 seconds
Started Jun 29 06:44:26 PM PDT 24
Finished Jun 29 06:55:00 PM PDT 24
Peak memory 202228 kb
Host smart-80266a0f-150e-4b63-a666-30a3c2dc0767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407377556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3407377556
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2854797424
Short name T604
Test name
Test status
Simulation time 47133866563 ps
CPU time 26.42 seconds
Started Jun 29 06:44:27 PM PDT 24
Finished Jun 29 06:44:54 PM PDT 24
Peak memory 201680 kb
Host smart-bcd5c09c-3297-40d0-8955-ad7b8540d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854797424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2854797424
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2052876731
Short name T756
Test name
Test status
Simulation time 5424068282 ps
CPU time 4.27 seconds
Started Jun 29 06:44:27 PM PDT 24
Finished Jun 29 06:44:31 PM PDT 24
Peak memory 201692 kb
Host smart-e9c50e27-554d-487e-884b-647270caaa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052876731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2052876731
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.576971904
Short name T746
Test name
Test status
Simulation time 5927190638 ps
CPU time 13.36 seconds
Started Jun 29 06:44:18 PM PDT 24
Finished Jun 29 06:44:32 PM PDT 24
Peak memory 201588 kb
Host smart-07090743-0d7c-4cb6-ae3f-f2c44b21fa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576971904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.576971904
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2233748751
Short name T311
Test name
Test status
Simulation time 506862550485 ps
CPU time 326.55 seconds
Started Jun 29 06:44:27 PM PDT 24
Finished Jun 29 06:49:54 PM PDT 24
Peak memory 201864 kb
Host smart-b06828d4-8a37-47f5-b7b1-b01f16a6a6be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233748751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2233748751
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.431824749
Short name T577
Test name
Test status
Simulation time 585003178 ps
CPU time 0.67 seconds
Started Jun 29 06:44:43 PM PDT 24
Finished Jun 29 06:44:43 PM PDT 24
Peak memory 201624 kb
Host smart-b1c11902-5f29-4799-833d-de41336ea249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431824749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.431824749
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.906965398
Short name T4
Test name
Test status
Simulation time 163567846554 ps
CPU time 374.53 seconds
Started Jun 29 06:44:36 PM PDT 24
Finished Jun 29 06:50:51 PM PDT 24
Peak memory 201868 kb
Host smart-0bfa28b6-4782-4a3d-ae60-cf8ce55de2b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906965398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.906965398
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.849940757
Short name T318
Test name
Test status
Simulation time 161978374461 ps
CPU time 71.52 seconds
Started Jun 29 06:44:37 PM PDT 24
Finished Jun 29 06:45:48 PM PDT 24
Peak memory 201852 kb
Host smart-1f16bcf1-7739-41a5-ac4f-404293472304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849940757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.849940757
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.679568230
Short name T187
Test name
Test status
Simulation time 331801388294 ps
CPU time 189.74 seconds
Started Jun 29 06:44:35 PM PDT 24
Finished Jun 29 06:47:45 PM PDT 24
Peak memory 201864 kb
Host smart-d7909627-c7cc-4ea5-a138-04c3e69def2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679568230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.679568230
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1196073107
Short name T439
Test name
Test status
Simulation time 331469961124 ps
CPU time 216.05 seconds
Started Jun 29 06:44:35 PM PDT 24
Finished Jun 29 06:48:11 PM PDT 24
Peak memory 201840 kb
Host smart-cfc57f9e-2b2c-47e5-9829-91191dfacbdb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196073107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1196073107
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.70435837
Short name T129
Test name
Test status
Simulation time 325453198442 ps
CPU time 772.28 seconds
Started Jun 29 06:44:27 PM PDT 24
Finished Jun 29 06:57:20 PM PDT 24
Peak memory 202148 kb
Host smart-c7e0b484-82cc-42cf-8738-4efd1fdecf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70435837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.70435837
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2470628590
Short name T451
Test name
Test status
Simulation time 492375323483 ps
CPU time 292.09 seconds
Started Jun 29 06:44:34 PM PDT 24
Finished Jun 29 06:49:27 PM PDT 24
Peak memory 201832 kb
Host smart-749fe3df-c3b4-4aeb-8037-b473cb1453e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470628590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2470628590
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2671097982
Short name T226
Test name
Test status
Simulation time 587032633176 ps
CPU time 613.93 seconds
Started Jun 29 06:44:35 PM PDT 24
Finished Jun 29 06:54:49 PM PDT 24
Peak memory 201932 kb
Host smart-558e7aab-2827-4562-b35d-5390a40ba5fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671097982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2671097982
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.4215635444
Short name T460
Test name
Test status
Simulation time 195317572438 ps
CPU time 169.97 seconds
Started Jun 29 06:44:34 PM PDT 24
Finished Jun 29 06:47:24 PM PDT 24
Peak memory 201844 kb
Host smart-d2c9a322-0358-4cef-91ad-d8d18aaa3a61
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215635444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.4215635444
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3211111415
Short name T415
Test name
Test status
Simulation time 22787769823 ps
CPU time 7.81 seconds
Started Jun 29 06:44:35 PM PDT 24
Finished Jun 29 06:44:43 PM PDT 24
Peak memory 201584 kb
Host smart-e5ef1de7-e382-403e-8003-4b8413d65f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211111415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3211111415
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2039671943
Short name T447
Test name
Test status
Simulation time 5411071332 ps
CPU time 4.31 seconds
Started Jun 29 06:44:35 PM PDT 24
Finished Jun 29 06:44:40 PM PDT 24
Peak memory 201692 kb
Host smart-3ff057d1-f797-4094-90a3-615f833f65df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039671943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2039671943
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1147183124
Short name T462
Test name
Test status
Simulation time 5746203053 ps
CPU time 4.64 seconds
Started Jun 29 06:44:25 PM PDT 24
Finished Jun 29 06:44:30 PM PDT 24
Peak memory 201672 kb
Host smart-8f7872f0-d66e-429a-ab32-b00d0b48a08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147183124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1147183124
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3980711642
Short name T34
Test name
Test status
Simulation time 338960333659 ps
CPU time 182.62 seconds
Started Jun 29 06:44:46 PM PDT 24
Finished Jun 29 06:47:49 PM PDT 24
Peak memory 201832 kb
Host smart-fa2ab5fd-0e5b-47d9-9f4e-19ea8dfab354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980711642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3980711642
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2704441429
Short name T335
Test name
Test status
Simulation time 29794085046 ps
CPU time 50.26 seconds
Started Jun 29 06:44:44 PM PDT 24
Finished Jun 29 06:45:34 PM PDT 24
Peak memory 210260 kb
Host smart-8b30c68a-081f-4834-a615-305d506ddc65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704441429 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2704441429
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.4119022969
Short name T682
Test name
Test status
Simulation time 462685775 ps
CPU time 1.13 seconds
Started Jun 29 06:44:52 PM PDT 24
Finished Jun 29 06:44:53 PM PDT 24
Peak memory 201628 kb
Host smart-556500b0-9799-43cd-9053-e894c64ba7dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119022969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.4119022969
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2203807526
Short name T293
Test name
Test status
Simulation time 578449590748 ps
CPU time 41.97 seconds
Started Jun 29 06:44:44 PM PDT 24
Finished Jun 29 06:45:27 PM PDT 24
Peak memory 201840 kb
Host smart-c897bde6-d19d-4c87-a96e-8f0a824233a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203807526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2203807526
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.214238690
Short name T565
Test name
Test status
Simulation time 181512224628 ps
CPU time 455.99 seconds
Started Jun 29 06:44:42 PM PDT 24
Finished Jun 29 06:52:18 PM PDT 24
Peak memory 201876 kb
Host smart-90971af2-766a-407f-a87d-8d9095c20854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214238690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.214238690
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1066733328
Short name T574
Test name
Test status
Simulation time 331434928196 ps
CPU time 807 seconds
Started Jun 29 06:44:41 PM PDT 24
Finished Jun 29 06:58:09 PM PDT 24
Peak memory 201928 kb
Host smart-010bb842-59c0-4da6-9be6-96de4a3d64a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066733328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1066733328
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.717182293
Short name T503
Test name
Test status
Simulation time 164907462813 ps
CPU time 110.61 seconds
Started Jun 29 06:44:42 PM PDT 24
Finished Jun 29 06:46:33 PM PDT 24
Peak memory 201848 kb
Host smart-02627b7b-0e40-411f-968a-22cad30f03bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=717182293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.717182293
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.81241467
Short name T761
Test name
Test status
Simulation time 166411305906 ps
CPU time 375.19 seconds
Started Jun 29 06:44:42 PM PDT 24
Finished Jun 29 06:50:58 PM PDT 24
Peak memory 201892 kb
Host smart-7ace69cc-7150-4f7e-9360-c30078fcf572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81241467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.81241467
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.370955737
Short name T360
Test name
Test status
Simulation time 479742753851 ps
CPU time 290.17 seconds
Started Jun 29 06:44:41 PM PDT 24
Finished Jun 29 06:49:31 PM PDT 24
Peak memory 201860 kb
Host smart-ed942f61-6842-422a-8454-b7c6d70d1456
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=370955737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.370955737
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3517451147
Short name T633
Test name
Test status
Simulation time 194213673466 ps
CPU time 112.08 seconds
Started Jun 29 06:44:41 PM PDT 24
Finished Jun 29 06:46:33 PM PDT 24
Peak memory 201860 kb
Host smart-3b7b10e5-e693-4e20-8631-bb96d10817d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517451147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3517451147
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.277955570
Short name T353
Test name
Test status
Simulation time 74752921604 ps
CPU time 417.79 seconds
Started Jun 29 06:44:43 PM PDT 24
Finished Jun 29 06:51:41 PM PDT 24
Peak memory 202240 kb
Host smart-f488259f-1df4-4893-90bb-908e6f461a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277955570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.277955570
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.267822888
Short name T513
Test name
Test status
Simulation time 25915753125 ps
CPU time 14.49 seconds
Started Jun 29 06:44:40 PM PDT 24
Finished Jun 29 06:44:55 PM PDT 24
Peak memory 201636 kb
Host smart-5b29b813-bf27-4134-b2c8-4440d74e19e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267822888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.267822888
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.988216724
Short name T41
Test name
Test status
Simulation time 4900281924 ps
CPU time 3.65 seconds
Started Jun 29 06:44:42 PM PDT 24
Finished Jun 29 06:44:46 PM PDT 24
Peak memory 201688 kb
Host smart-22fc657b-5a4a-472f-a7ac-2ea3c1a03534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988216724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.988216724
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.418055337
Short name T370
Test name
Test status
Simulation time 5701771993 ps
CPU time 12.71 seconds
Started Jun 29 06:44:44 PM PDT 24
Finished Jun 29 06:44:57 PM PDT 24
Peak memory 201668 kb
Host smart-eb8a9888-78d6-4a2b-bf85-a97c95b7ccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418055337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.418055337
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1027021071
Short name T488
Test name
Test status
Simulation time 81568567879 ps
CPU time 295.32 seconds
Started Jun 29 06:44:56 PM PDT 24
Finished Jun 29 06:49:51 PM PDT 24
Peak memory 202144 kb
Host smart-7ddf6b0b-a6f2-4a7c-a536-1977403bedac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027021071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1027021071
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3609329120
Short name T37
Test name
Test status
Simulation time 222706190330 ps
CPU time 246.79 seconds
Started Jun 29 06:44:56 PM PDT 24
Finished Jun 29 06:49:03 PM PDT 24
Peak memory 217924 kb
Host smart-1307e1ec-b7a7-4284-a0b4-66b56836f6fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609329120 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3609329120
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2035475521
Short name T395
Test name
Test status
Simulation time 362103737 ps
CPU time 1.39 seconds
Started Jun 29 06:45:00 PM PDT 24
Finished Jun 29 06:45:01 PM PDT 24
Peak memory 201580 kb
Host smart-2e1b7f38-3444-4b1c-8b97-cf7a9ac0b53f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035475521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2035475521
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3377643248
Short name T658
Test name
Test status
Simulation time 164951998044 ps
CPU time 10.11 seconds
Started Jun 29 06:44:57 PM PDT 24
Finished Jun 29 06:45:08 PM PDT 24
Peak memory 201840 kb
Host smart-e24901c8-3429-4893-9f2e-ccbf4ceb0496
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377643248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3377643248
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2025828380
Short name T239
Test name
Test status
Simulation time 521344602255 ps
CPU time 153.89 seconds
Started Jun 29 06:44:58 PM PDT 24
Finished Jun 29 06:47:32 PM PDT 24
Peak memory 201880 kb
Host smart-0db79193-fb9a-4252-a3c9-13b0ba898e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025828380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2025828380
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2792721790
Short name T171
Test name
Test status
Simulation time 491560356153 ps
CPU time 1215.26 seconds
Started Jun 29 06:44:55 PM PDT 24
Finished Jun 29 07:05:11 PM PDT 24
Peak memory 201852 kb
Host smart-cddaee54-9ad3-486a-87d6-7e2a7224d3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792721790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2792721790
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2673327961
Short name T427
Test name
Test status
Simulation time 162558288365 ps
CPU time 101.82 seconds
Started Jun 29 06:44:52 PM PDT 24
Finished Jun 29 06:46:34 PM PDT 24
Peak memory 201760 kb
Host smart-82c7f79d-c43e-4a46-8a25-4ff5edb6c0f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673327961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2673327961
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2192168498
Short name T701
Test name
Test status
Simulation time 163773277882 ps
CPU time 361.53 seconds
Started Jun 29 06:44:51 PM PDT 24
Finished Jun 29 06:50:53 PM PDT 24
Peak memory 201952 kb
Host smart-495d5feb-707f-4232-82a9-f8a87b0ef65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192168498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2192168498
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.161936299
Short name T739
Test name
Test status
Simulation time 503564582674 ps
CPU time 766.43 seconds
Started Jun 29 06:44:49 PM PDT 24
Finished Jun 29 06:57:36 PM PDT 24
Peak memory 201852 kb
Host smart-cb82876f-a6c0-471e-8637-63655ba8abca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=161936299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.161936299
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1071522593
Short name T199
Test name
Test status
Simulation time 436523902248 ps
CPU time 901.91 seconds
Started Jun 29 06:44:59 PM PDT 24
Finished Jun 29 07:00:01 PM PDT 24
Peak memory 201948 kb
Host smart-868a50e7-cca9-4a8c-a372-aad1fc3940fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071522593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1071522593
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.356266754
Short name T528
Test name
Test status
Simulation time 396688073244 ps
CPU time 317.91 seconds
Started Jun 29 06:44:57 PM PDT 24
Finished Jun 29 06:50:16 PM PDT 24
Peak memory 201844 kb
Host smart-09b6a5e5-31cb-45ed-b1ae-fe4d714b41bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356266754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.356266754
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3193468345
Short name T696
Test name
Test status
Simulation time 108379045721 ps
CPU time 361.33 seconds
Started Jun 29 06:44:56 PM PDT 24
Finished Jun 29 06:50:58 PM PDT 24
Peak memory 202200 kb
Host smart-c1cf267b-476a-40ec-aa77-fa77ba86c00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193468345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3193468345
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3814674385
Short name T529
Test name
Test status
Simulation time 25041018298 ps
CPU time 14.84 seconds
Started Jun 29 06:44:57 PM PDT 24
Finished Jun 29 06:45:12 PM PDT 24
Peak memory 201648 kb
Host smart-79347649-2c84-46ef-b14e-604647727262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814674385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3814674385
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3821000838
Short name T388
Test name
Test status
Simulation time 3002946695 ps
CPU time 7.47 seconds
Started Jun 29 06:44:57 PM PDT 24
Finished Jun 29 06:45:05 PM PDT 24
Peak memory 201676 kb
Host smart-7a65424f-78e1-4948-9a45-7abc0e4eaf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821000838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3821000838
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2393988105
Short name T433
Test name
Test status
Simulation time 5722946290 ps
CPU time 7.28 seconds
Started Jun 29 06:44:52 PM PDT 24
Finished Jun 29 06:44:59 PM PDT 24
Peak memory 201632 kb
Host smart-582cd8c5-f8ab-4b71-97a9-312beff8ad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393988105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2393988105
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.812729941
Short name T563
Test name
Test status
Simulation time 56213168907 ps
CPU time 30.42 seconds
Started Jun 29 06:44:56 PM PDT 24
Finished Jun 29 06:45:27 PM PDT 24
Peak memory 201680 kb
Host smart-86a9abb4-2355-4f40-9283-dc3cb7e94e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812729941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
812729941
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.85212653
Short name T675
Test name
Test status
Simulation time 205435354039 ps
CPU time 117.03 seconds
Started Jun 29 06:44:58 PM PDT 24
Finished Jun 29 06:46:55 PM PDT 24
Peak memory 210192 kb
Host smart-4c56a31e-99e3-4d08-ac75-17158792e3ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85212653 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.85212653
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3436310933
Short name T625
Test name
Test status
Simulation time 540877253 ps
CPU time 1.18 seconds
Started Jun 29 06:45:05 PM PDT 24
Finished Jun 29 06:45:07 PM PDT 24
Peak memory 201600 kb
Host smart-4ff7b39c-ca18-47b6-bc13-43ce8cc7a85d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436310933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3436310933
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2610691124
Short name T615
Test name
Test status
Simulation time 161231798709 ps
CPU time 374.97 seconds
Started Jun 29 06:45:04 PM PDT 24
Finished Jun 29 06:51:19 PM PDT 24
Peak memory 201836 kb
Host smart-e8b3bca8-6246-47bd-9584-c9010fe4d2e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610691124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2610691124
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2295552612
Short name T446
Test name
Test status
Simulation time 164888981374 ps
CPU time 365.21 seconds
Started Jun 29 06:45:07 PM PDT 24
Finished Jun 29 06:51:13 PM PDT 24
Peak memory 201936 kb
Host smart-46117e58-de3c-4277-ae73-6819036fec0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295552612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2295552612
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1512279513
Short name T475
Test name
Test status
Simulation time 494863242453 ps
CPU time 303.5 seconds
Started Jun 29 06:45:07 PM PDT 24
Finished Jun 29 06:50:11 PM PDT 24
Peak memory 201812 kb
Host smart-d74e01d8-82f8-4534-9023-6ac0a9df6db3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512279513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1512279513
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3517114322
Short name T560
Test name
Test status
Simulation time 494515145233 ps
CPU time 817.93 seconds
Started Jun 29 06:45:05 PM PDT 24
Finished Jun 29 06:58:44 PM PDT 24
Peak memory 201888 kb
Host smart-7dc6fdfd-34a3-404d-929b-6250de602f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517114322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3517114322
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3047459385
Short name T412
Test name
Test status
Simulation time 167616584681 ps
CPU time 203.58 seconds
Started Jun 29 06:45:06 PM PDT 24
Finished Jun 29 06:48:30 PM PDT 24
Peak memory 201848 kb
Host smart-0d8b6325-6720-4ee0-a21e-3f5aa1ecb2c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047459385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3047459385
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2849689339
Short name T702
Test name
Test status
Simulation time 347432256569 ps
CPU time 787.03 seconds
Started Jun 29 06:45:07 PM PDT 24
Finished Jun 29 06:58:14 PM PDT 24
Peak memory 201936 kb
Host smart-3db36f11-2190-4034-bc0d-442abd288768
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849689339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2849689339
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3428091259
Short name T179
Test name
Test status
Simulation time 601554663248 ps
CPU time 1285.28 seconds
Started Jun 29 06:45:06 PM PDT 24
Finished Jun 29 07:06:32 PM PDT 24
Peak memory 201860 kb
Host smart-1d8058a8-9d15-4490-9db7-338fdd45f55a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428091259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3428091259
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3890720709
Short name T497
Test name
Test status
Simulation time 104447026110 ps
CPU time 367.96 seconds
Started Jun 29 06:45:05 PM PDT 24
Finished Jun 29 06:51:13 PM PDT 24
Peak memory 202112 kb
Host smart-85ee19c5-d5a5-4852-a973-c20459ba51b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890720709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3890720709
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1532787784
Short name T27
Test name
Test status
Simulation time 28066704040 ps
CPU time 13.22 seconds
Started Jun 29 06:45:04 PM PDT 24
Finished Jun 29 06:45:18 PM PDT 24
Peak memory 201680 kb
Host smart-1b9a7a17-2b4f-4ae0-a535-e7fb518542b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532787784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1532787784
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1827923674
Short name T24
Test name
Test status
Simulation time 4210063602 ps
CPU time 11.35 seconds
Started Jun 29 06:45:06 PM PDT 24
Finished Jun 29 06:45:18 PM PDT 24
Peak memory 201684 kb
Host smart-309e0a07-e15e-45de-922f-aceba56b21df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827923674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1827923674
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.894249827
Short name T693
Test name
Test status
Simulation time 5826196402 ps
CPU time 7.41 seconds
Started Jun 29 06:44:59 PM PDT 24
Finished Jun 29 06:45:07 PM PDT 24
Peak memory 201636 kb
Host smart-d0cb42ae-4316-4892-a58e-50678d8b28be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894249827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.894249827
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1649322130
Short name T33
Test name
Test status
Simulation time 244382024161 ps
CPU time 355.57 seconds
Started Jun 29 06:45:05 PM PDT 24
Finished Jun 29 06:51:01 PM PDT 24
Peak memory 201932 kb
Host smart-fd3bc931-48ac-4863-b46a-99d5a8d03ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649322130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1649322130
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.4113506781
Short name T651
Test name
Test status
Simulation time 157122598212 ps
CPU time 44.07 seconds
Started Jun 29 06:45:04 PM PDT 24
Finished Jun 29 06:45:48 PM PDT 24
Peak memory 202008 kb
Host smart-45e6070b-3ac6-4156-9b84-1dfac86dba96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113506781 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.4113506781
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1594802810
Short name T506
Test name
Test status
Simulation time 518772155 ps
CPU time 1.88 seconds
Started Jun 29 06:42:15 PM PDT 24
Finished Jun 29 06:42:17 PM PDT 24
Peak memory 201628 kb
Host smart-2cfe6826-3731-4529-9ddc-6f2abd34db26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594802810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1594802810
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.454641492
Short name T174
Test name
Test status
Simulation time 537668641965 ps
CPU time 152.65 seconds
Started Jun 29 06:41:50 PM PDT 24
Finished Jun 29 06:44:23 PM PDT 24
Peak memory 201864 kb
Host smart-11e71ab6-0068-443f-8455-6223883faf7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454641492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.454641492
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1403467939
Short name T52
Test name
Test status
Simulation time 187510350229 ps
CPU time 160.11 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:44:32 PM PDT 24
Peak memory 201840 kb
Host smart-6431f972-2f83-4a50-954f-fa7683bcb4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403467939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1403467939
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3954856598
Short name T10
Test name
Test status
Simulation time 161239078725 ps
CPU time 85.52 seconds
Started Jun 29 06:41:52 PM PDT 24
Finished Jun 29 06:43:19 PM PDT 24
Peak memory 201840 kb
Host smart-46a5e782-848b-4711-ad36-301306208b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954856598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3954856598
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3437302921
Short name T143
Test name
Test status
Simulation time 170171831488 ps
CPU time 359.75 seconds
Started Jun 29 06:42:16 PM PDT 24
Finished Jun 29 06:48:16 PM PDT 24
Peak memory 201840 kb
Host smart-f03c849f-0e7b-496a-9d54-0cffe3bdbd0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437302921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3437302921
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3449221458
Short name T467
Test name
Test status
Simulation time 325199424405 ps
CPU time 316.32 seconds
Started Jun 29 06:41:58 PM PDT 24
Finished Jun 29 06:47:16 PM PDT 24
Peak memory 201940 kb
Host smart-973243d8-9947-4d92-98d9-8e1e738fba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449221458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3449221458
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.478598534
Short name T624
Test name
Test status
Simulation time 330469710600 ps
CPU time 134.84 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:44:12 PM PDT 24
Peak memory 201864 kb
Host smart-926e727b-b1f5-4503-95a4-912482fcb57f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=478598534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.478598534
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.166500167
Short name T189
Test name
Test status
Simulation time 525124018276 ps
CPU time 356.21 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:47:53 PM PDT 24
Peak memory 201880 kb
Host smart-a96b5dc7-11dd-4f5a-94e4-ed1ff05501f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166500167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.166500167
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2822428282
Short name T365
Test name
Test status
Simulation time 201182038153 ps
CPU time 128.74 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:44:06 PM PDT 24
Peak memory 201852 kb
Host smart-7d12857b-cc41-4337-8d4b-237cd47c9735
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822428282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2822428282
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3165255428
Short name T584
Test name
Test status
Simulation time 79341477866 ps
CPU time 427.71 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:49:05 PM PDT 24
Peak memory 202240 kb
Host smart-f25ddb3c-49a5-4d38-896b-f72662590211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165255428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3165255428
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1684247607
Short name T358
Test name
Test status
Simulation time 37434601073 ps
CPU time 92.8 seconds
Started Jun 29 06:41:48 PM PDT 24
Finished Jun 29 06:43:22 PM PDT 24
Peak memory 201668 kb
Host smart-677f8a16-44c5-4031-a509-65553b1e86dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684247607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1684247607
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.465144032
Short name T736
Test name
Test status
Simulation time 5977020777 ps
CPU time 5.79 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:42:05 PM PDT 24
Peak memory 201680 kb
Host smart-3d5d73e2-6cc3-451f-8b0d-3d4589b26cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465144032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.465144032
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.698476991
Short name T646
Test name
Test status
Simulation time 5739874401 ps
CPU time 4.63 seconds
Started Jun 29 06:42:02 PM PDT 24
Finished Jun 29 06:42:07 PM PDT 24
Peak memory 201632 kb
Host smart-5e10bbae-237d-4cfa-ac75-03b9591b0b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698476991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.698476991
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1703316973
Short name T312
Test name
Test status
Simulation time 313764028304 ps
CPU time 999.09 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:58:35 PM PDT 24
Peak memory 210372 kb
Host smart-57df868c-3f17-49b1-8349-6e48146a2f3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703316973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1703316973
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3861295964
Short name T21
Test name
Test status
Simulation time 23569005859 ps
CPU time 52.24 seconds
Started Jun 29 06:42:04 PM PDT 24
Finished Jun 29 06:42:57 PM PDT 24
Peak memory 210256 kb
Host smart-e97f5189-3c54-49bf-9851-4e685e89b089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861295964 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3861295964
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1633221137
Short name T428
Test name
Test status
Simulation time 445871147 ps
CPU time 1.69 seconds
Started Jun 29 06:42:01 PM PDT 24
Finished Jun 29 06:42:03 PM PDT 24
Peak memory 201628 kb
Host smart-9801f261-a586-4283-949a-5fc2720c9eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633221137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1633221137
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3485937510
Short name T534
Test name
Test status
Simulation time 327049543652 ps
CPU time 570.37 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:51:22 PM PDT 24
Peak memory 201824 kb
Host smart-db0c4df4-59b6-48c0-a81b-b4d31d9e23a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485937510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3485937510
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.620519182
Short name T593
Test name
Test status
Simulation time 188860557069 ps
CPU time 420.5 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:48:53 PM PDT 24
Peak memory 201888 kb
Host smart-bf1479e9-ccbc-4cd7-afe1-b20da560cf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620519182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.620519182
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1144457751
Short name T622
Test name
Test status
Simulation time 164714806587 ps
CPU time 397.99 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:48:34 PM PDT 24
Peak memory 201844 kb
Host smart-8fdbb4af-7458-484a-9c43-93365bdffb84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144457751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1144457751
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1934191073
Short name T309
Test name
Test status
Simulation time 168088839295 ps
CPU time 383.62 seconds
Started Jun 29 06:42:19 PM PDT 24
Finished Jun 29 06:48:43 PM PDT 24
Peak memory 201932 kb
Host smart-4a1372f9-4b3b-46a6-b67b-1fcafc13adc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934191073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1934191073
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2606157871
Short name T660
Test name
Test status
Simulation time 329081370742 ps
CPU time 387.51 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:48:24 PM PDT 24
Peak memory 201804 kb
Host smart-1a66e8e6-fe74-4595-af20-0375b2d6c70e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606157871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2606157871
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1903160379
Short name T748
Test name
Test status
Simulation time 339307198678 ps
CPU time 311.07 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:47:03 PM PDT 24
Peak memory 201828 kb
Host smart-a5d6c245-073c-479b-96f6-81f30b7b4778
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903160379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1903160379
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.423092330
Short name T597
Test name
Test status
Simulation time 397691608053 ps
CPU time 937.24 seconds
Started Jun 29 06:41:51 PM PDT 24
Finished Jun 29 06:57:30 PM PDT 24
Peak memory 201856 kb
Host smart-fef9ee12-8e0a-4523-8934-a4344de77817
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423092330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.423092330
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.973558210
Short name T599
Test name
Test status
Simulation time 73401383170 ps
CPU time 402.4 seconds
Started Jun 29 06:42:09 PM PDT 24
Finished Jun 29 06:48:51 PM PDT 24
Peak memory 202192 kb
Host smart-496d5c7b-0bdd-4e67-919e-5e9a508c655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973558210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.973558210
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1348482673
Short name T724
Test name
Test status
Simulation time 42204562528 ps
CPU time 24.75 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:42:21 PM PDT 24
Peak memory 201672 kb
Host smart-f5361d97-c919-4462-8c21-d9758fd2214a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348482673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1348482673
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3707150561
Short name T742
Test name
Test status
Simulation time 4544074867 ps
CPU time 11.47 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:42:08 PM PDT 24
Peak memory 201680 kb
Host smart-0c2e10ea-1bc3-43b0-8925-710e2ff273a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707150561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3707150561
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1266108114
Short name T396
Test name
Test status
Simulation time 6030904773 ps
CPU time 5.92 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:42:03 PM PDT 24
Peak memory 201680 kb
Host smart-a0fd000a-671f-43b2-b58e-c20ca7a0f66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266108114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1266108114
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.660883519
Short name T265
Test name
Test status
Simulation time 55554202599 ps
CPU time 113.78 seconds
Started Jun 29 06:41:55 PM PDT 24
Finished Jun 29 06:43:51 PM PDT 24
Peak memory 210256 kb
Host smart-3d278ca9-196b-4681-816e-a6bb8c8aa9ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660883519 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.660883519
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.269907961
Short name T490
Test name
Test status
Simulation time 307417736 ps
CPU time 0.83 seconds
Started Jun 29 06:42:02 PM PDT 24
Finished Jun 29 06:42:03 PM PDT 24
Peak memory 201632 kb
Host smart-61c9aade-f605-4813-bd71-c0983779edfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269907961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.269907961
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1231924627
Short name T727
Test name
Test status
Simulation time 503863724710 ps
CPU time 97.01 seconds
Started Jun 29 06:41:46 PM PDT 24
Finished Jun 29 06:43:24 PM PDT 24
Peak memory 201868 kb
Host smart-774436a9-1b79-4c02-a29d-35daf8a1b33e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231924627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1231924627
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2081964798
Short name T463
Test name
Test status
Simulation time 324574989738 ps
CPU time 200.62 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:45:15 PM PDT 24
Peak memory 201804 kb
Host smart-d7bf1cd9-fc0b-495a-b182-7e978d080661
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081964798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2081964798
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2826254373
Short name T771
Test name
Test status
Simulation time 331081224866 ps
CPU time 747.4 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:54:27 PM PDT 24
Peak memory 201848 kb
Host smart-c78e345d-5907-4102-883a-ef3027d66d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826254373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2826254373
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3632100738
Short name T600
Test name
Test status
Simulation time 496299726159 ps
CPU time 526.07 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:50:40 PM PDT 24
Peak memory 201828 kb
Host smart-1ed81a1a-290d-40f5-8465-b42baeb26b44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632100738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3632100738
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.193640480
Short name T328
Test name
Test status
Simulation time 529003945933 ps
CPU time 501.58 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:50:16 PM PDT 24
Peak memory 201924 kb
Host smart-55719c65-7b86-43bb-9688-9e4918b30d17
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193640480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.193640480
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1097728690
Short name T375
Test name
Test status
Simulation time 589772951219 ps
CPU time 692.39 seconds
Started Jun 29 06:42:14 PM PDT 24
Finished Jun 29 06:53:47 PM PDT 24
Peak memory 201836 kb
Host smart-fa3dc3f0-d36b-4deb-ade4-245d5faf2eee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097728690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1097728690
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.497006171
Short name T448
Test name
Test status
Simulation time 129118295499 ps
CPU time 430.3 seconds
Started Jun 29 06:42:11 PM PDT 24
Finished Jun 29 06:49:21 PM PDT 24
Peak memory 202196 kb
Host smart-c50e40c5-5110-4678-b43f-832a28fe93ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497006171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.497006171
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4045912524
Short name T768
Test name
Test status
Simulation time 32288054648 ps
CPU time 21.38 seconds
Started Jun 29 06:42:06 PM PDT 24
Finished Jun 29 06:42:27 PM PDT 24
Peak memory 201680 kb
Host smart-9304805a-664e-426f-9e22-efc2fd3634ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045912524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4045912524
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2203434689
Short name T436
Test name
Test status
Simulation time 3642426300 ps
CPU time 8.65 seconds
Started Jun 29 06:41:52 PM PDT 24
Finished Jun 29 06:42:02 PM PDT 24
Peak memory 201692 kb
Host smart-4d901798-30a2-4610-8732-a25cc7fb5643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203434689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2203434689
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3482881877
Short name T356
Test name
Test status
Simulation time 5783341102 ps
CPU time 12.7 seconds
Started Jun 29 06:41:52 PM PDT 24
Finished Jun 29 06:42:06 PM PDT 24
Peak memory 201676 kb
Host smart-44d1bd4c-7111-4596-8f9a-3513c73709dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482881877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3482881877
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3281719667
Short name T456
Test name
Test status
Simulation time 108122453982 ps
CPU time 337.67 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:47:37 PM PDT 24
Peak memory 202092 kb
Host smart-eda35b85-a2f0-493a-9f53-479990210f83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281719667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3281719667
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3148199754
Short name T19
Test name
Test status
Simulation time 24933711235 ps
CPU time 55.07 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:42:54 PM PDT 24
Peak memory 201888 kb
Host smart-8bf11c21-9e67-42dc-bbbf-b5f39eef1fae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148199754 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3148199754
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4158990086
Short name T747
Test name
Test status
Simulation time 302289960 ps
CPU time 1.3 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:41:56 PM PDT 24
Peak memory 201628 kb
Host smart-fde307c5-1632-441f-b7ee-71ff17fc994f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158990086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4158990086
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3321918735
Short name T244
Test name
Test status
Simulation time 169775905137 ps
CPU time 61.27 seconds
Started Jun 29 06:42:00 PM PDT 24
Finished Jun 29 06:43:02 PM PDT 24
Peak memory 201840 kb
Host smart-f5e0bbff-989c-471a-88d8-ed4339065828
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321918735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3321918735
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.782755677
Short name T13
Test name
Test status
Simulation time 330623035715 ps
CPU time 702.7 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:53:40 PM PDT 24
Peak memory 201872 kb
Host smart-3adb882f-6c6b-432a-83d3-796d1541add1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782755677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.782755677
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3790282622
Short name T193
Test name
Test status
Simulation time 325837789450 ps
CPU time 738.2 seconds
Started Jun 29 06:42:04 PM PDT 24
Finished Jun 29 06:54:22 PM PDT 24
Peak memory 201876 kb
Host smart-23bc0a31-6ec5-4676-8549-a07c97537d79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790282622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3790282622
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3361739413
Short name T629
Test name
Test status
Simulation time 482183759056 ps
CPU time 1017.14 seconds
Started Jun 29 06:42:01 PM PDT 24
Finished Jun 29 06:58:59 PM PDT 24
Peak memory 201876 kb
Host smart-9c634eb4-8801-43c6-bf62-2c9f9a52a730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361739413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3361739413
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2983610443
Short name T420
Test name
Test status
Simulation time 492150411273 ps
CPU time 108.8 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:43:44 PM PDT 24
Peak memory 201868 kb
Host smart-37d091cb-34ad-4e25-ae46-51d63ac5b131
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983610443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2983610443
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3906763471
Short name T53
Test name
Test status
Simulation time 348236648873 ps
CPU time 774.18 seconds
Started Jun 29 06:41:50 PM PDT 24
Finished Jun 29 06:54:45 PM PDT 24
Peak memory 201892 kb
Host smart-0c7be60c-f47f-4407-8b2a-353d6972bd08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906763471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3906763471
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1338912619
Short name T409
Test name
Test status
Simulation time 409363501034 ps
CPU time 206.55 seconds
Started Jun 29 06:41:56 PM PDT 24
Finished Jun 29 06:45:25 PM PDT 24
Peak memory 201868 kb
Host smart-a8b62e2a-a5bd-4fc8-97e0-b4e8bad84d71
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338912619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1338912619
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1592917380
Short name T54
Test name
Test status
Simulation time 94455815484 ps
CPU time 527.24 seconds
Started Jun 29 06:41:56 PM PDT 24
Finished Jun 29 06:50:49 PM PDT 24
Peak memory 202196 kb
Host smart-2872c2c8-06d3-4cc7-b31b-78b1bef999d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592917380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1592917380
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.180204424
Short name T509
Test name
Test status
Simulation time 39765128090 ps
CPU time 85.47 seconds
Started Jun 29 06:42:13 PM PDT 24
Finished Jun 29 06:43:39 PM PDT 24
Peak memory 201656 kb
Host smart-992655df-2522-4a44-a9ee-b29379915cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180204424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.180204424
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.81778447
Short name T621
Test name
Test status
Simulation time 3911615243 ps
CPU time 9.59 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:42:06 PM PDT 24
Peak memory 201632 kb
Host smart-1067c7b3-1823-4178-8c0f-5f2b151d3741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81778447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.81778447
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3195284399
Short name T558
Test name
Test status
Simulation time 6131504451 ps
CPU time 15.06 seconds
Started Jun 29 06:41:52 PM PDT 24
Finished Jun 29 06:42:08 PM PDT 24
Peak memory 201692 kb
Host smart-2bec2761-9843-474b-ac00-d8cece1c6e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195284399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3195284399
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3394510015
Short name T26
Test name
Test status
Simulation time 201213309971 ps
CPU time 122.06 seconds
Started Jun 29 06:42:27 PM PDT 24
Finished Jun 29 06:44:30 PM PDT 24
Peak memory 201876 kb
Host smart-55ad2b95-a0fe-4bb9-b2e6-5a403278e743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394510015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3394510015
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3292427194
Short name T236
Test name
Test status
Simulation time 65428343899 ps
CPU time 29.37 seconds
Started Jun 29 06:42:06 PM PDT 24
Finished Jun 29 06:42:36 PM PDT 24
Peak memory 210496 kb
Host smart-3a57dfdf-9f13-4170-93a0-ba0b3ed4c79b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292427194 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3292427194
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2991839609
Short name T450
Test name
Test status
Simulation time 343346344 ps
CPU time 1.43 seconds
Started Jun 29 06:42:09 PM PDT 24
Finished Jun 29 06:42:11 PM PDT 24
Peak memory 201628 kb
Host smart-12b4c2e0-4879-4d47-824e-d3afba574d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991839609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2991839609
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.122687094
Short name T267
Test name
Test status
Simulation time 164866975515 ps
CPU time 164.24 seconds
Started Jun 29 06:42:02 PM PDT 24
Finished Jun 29 06:44:47 PM PDT 24
Peak memory 201920 kb
Host smart-6c21d7b9-c549-408d-84c9-b69e419c162d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122687094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.122687094
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1478311234
Short name T654
Test name
Test status
Simulation time 325067722697 ps
CPU time 758.77 seconds
Started Jun 29 06:42:16 PM PDT 24
Finished Jun 29 06:54:56 PM PDT 24
Peak memory 201868 kb
Host smart-d19e397e-de92-4fff-a5c6-15cb8d89ea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478311234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1478311234
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1136873936
Short name T133
Test name
Test status
Simulation time 483005624431 ps
CPU time 1088.31 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 07:00:08 PM PDT 24
Peak memory 201848 kb
Host smart-bba8cf17-8c45-4b68-9c29-ec4ae2ab78df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136873936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1136873936
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3441433140
Short name T256
Test name
Test status
Simulation time 490688742571 ps
CPU time 587.98 seconds
Started Jun 29 06:42:20 PM PDT 24
Finished Jun 29 06:52:09 PM PDT 24
Peak memory 201924 kb
Host smart-dc67620a-d8d7-4a25-8475-4932db51c966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441433140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3441433140
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2692433096
Short name T616
Test name
Test status
Simulation time 164674233759 ps
CPU time 357.84 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:47:52 PM PDT 24
Peak memory 201832 kb
Host smart-eb5e437f-ef22-42f4-82af-6e717af1f60c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692433096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2692433096
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2103743778
Short name T249
Test name
Test status
Simulation time 361355183267 ps
CPU time 95.88 seconds
Started Jun 29 06:41:57 PM PDT 24
Finished Jun 29 06:43:35 PM PDT 24
Peak memory 201900 kb
Host smart-32b95291-a3a5-4b25-886c-569a1500482b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103743778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2103743778
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.833308179
Short name T384
Test name
Test status
Simulation time 398655294206 ps
CPU time 211.58 seconds
Started Jun 29 06:41:56 PM PDT 24
Finished Jun 29 06:45:30 PM PDT 24
Peak memory 201844 kb
Host smart-c74f0e82-74fa-472e-901e-4583f7675836
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833308179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.833308179
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4038627226
Short name T359
Test name
Test status
Simulation time 37684735942 ps
CPU time 88.96 seconds
Started Jun 29 06:41:54 PM PDT 24
Finished Jun 29 06:43:26 PM PDT 24
Peak memory 201676 kb
Host smart-b20d0c82-6349-4dd1-845f-8428a9d317b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038627226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4038627226
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.888463972
Short name T377
Test name
Test status
Simulation time 3228351876 ps
CPU time 2.36 seconds
Started Jun 29 06:41:56 PM PDT 24
Finished Jun 29 06:42:01 PM PDT 24
Peak memory 201680 kb
Host smart-34e23a0f-55f2-41de-8487-ab96024e6a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888463972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.888463972
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3016095473
Short name T430
Test name
Test status
Simulation time 5614018113 ps
CPU time 3.77 seconds
Started Jun 29 06:41:53 PM PDT 24
Finished Jun 29 06:41:58 PM PDT 24
Peak memory 201672 kb
Host smart-ba1b600f-6005-4d86-951b-cf34d241ec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016095473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3016095473
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2717580691
Short name T255
Test name
Test status
Simulation time 487701657527 ps
CPU time 280.59 seconds
Started Jun 29 06:42:16 PM PDT 24
Finished Jun 29 06:46:57 PM PDT 24
Peak memory 201840 kb
Host smart-3def0f44-6cf0-4b65-b0c7-e4c3e72e7687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717580691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2717580691
Directory /workspace/9.adc_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%