Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6641	1			T3	43		T8	6		T61	20
testmodes[AdcCtrlTestmodeNormal]	5408	1			T1	3		T2	2		T3	53
testmodes[AdcCtrlTestmodeLowpower]	5515	1			T2	1		T3	38		T4	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3501	1			T3	15		T8	2		T61	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1751	1			T3	17		T8	4		T44	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1278	1			T3	11		T44	1		T53	17
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1726	1			T3	18		T8	4		T53	18
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1965	1			T1	2		T2	1		T3	20
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1380	1			T3	14		T53	20		T71	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1305	1			T3	10		T44	2		T53	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1361	1			T2	1		T3	16		T4	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2599	1			T3	12		T4	1		T9	1