Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22506

1

T1

3

T2

51

T3

134

auto[ADC_CTRL_FILTER_COND_OUT]

3366

1

T1

21

T5

1

T7

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19823

1

T1

7

T2

6

T3

134

auto[1]

6049

1

T1

17

T2

45

T4

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	67	1			T53	9		T32	14		T150	16
values[1]	809	1			T5	1		T10	1		T57	9
values[2]	681	1			T1	7		T6	15		T9	12
values[3]	579	1			T38	11		T170	1		T151	7
values[4]	802	1			T1	3		T4	9		T10	9
values[5]	730	1			T4	16		T7	9		T52	12
values[6]	646	1			T9	2		T120	7		T62	1
values[7]	669	1			T4	31		T161	1		T152	18
values[8]	748	1			T2	19		T7	13		T153	11
values[9]	3536	1			T1	14		T2	32		T7	4
minimum	16605	1			T3	134		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	936	1			T5	1		T6	15		T10	1
values[1]	672	1			T1	7		T9	12		T10	12
values[2]	621	1			T4	9		T38	11		T170	1
values[3]	746	1			T1	3		T4	16		T7	9
values[4]	797	1			T52	12		T152	56		T120	7
values[5]	702	1			T9	2		T152	18		T45	8
values[6]	2711	1			T4	31		T7	13		T11	2
values[7]	758	1			T2	13		T56	1		T41	31
values[8]	1016	1			T1	14		T2	6		T56	1
values[9]	270	1			T2	32		T7	4		T170	1
minimum	16643	1			T3	134		T8	14		T61	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	1		T53	9		T57	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T5	1		T10	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T40	1		T108	1		T49	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T9	12		T10	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	6		T38	5		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T170	1		T214	1		T157	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	1		T4	9		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T44	6		T64	1		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T152	17		T120	1		T151	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T52	1		T152	12		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T9	2		T152	11		T66	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T45	6		T62	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1490	1			T4	16		T7	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T161	1		T215	22		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T2	1		T71	4		T154	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T56	1		T41	16		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T2	3		T56	1		T38	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	1		T161	1		T116	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T2	16		T170	1		T150	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T7	1		T216	14		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16489	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T218	1		T219	1		T220	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	14		T57	8		T32	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T71	1		T150	8		T119	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T108	20		T221	1		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T1	6		T123	12		T167	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T4	3		T38	6		T123	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T214	13		T13	3		T222	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	2		T4	7		T7	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T44	2		T64	11		T47	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T152	18		T120	6		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T52	11		T152	9		T123	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T152	7		T66	11		T50	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T45	2		T223	9		T192	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	904	1			T4	15		T7	12		T43	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T108	10		T48	1		T31	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	12		T71	2		T154	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T41	15		T150	4		T119	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T2	3		T38	15		T62	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	13		T116	3		T224	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T2	16		T150	9		T225	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T7	3		T217	15		T226	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T64	1		T45	4		T120	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T218	14		T219	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T53	9		T32	1		T128	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T150	8		T227	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T57	1		T108	1		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	1		T10	1		T119	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	1		T40	1		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	1		T9	12		T10	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T38	5		T123	1		T66	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T170	1		T151	7		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T1	1		T4	6		T10	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T44	6		T64	1		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	9		T7	1		T71	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T52	1		T152	12		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	2		T120	1		T66	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T62	1		T154	1		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	16		T152	11		T228	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T161	1		T45	6		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	4		T7	1		T109	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T153	11		T150	3		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1887	1			T2	16		T11	2		T60	38
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T1	1		T7	1		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T32	13		T30	1		T229	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T150	8		T227	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T57	8		T108	20		T51	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T119	9		T167	20		T59	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T6	14		T159	7		T173	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	6		T71	1		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T38	6		T123	2		T230	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T47	3		T13	3		T222	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	2		T4	3		T152	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T44	2		T64	11		T214	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T4	7		T7	8		T71	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T52	11		T152	9		T173	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T120	6		T66	14		T50	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T123	15		T223	9		T192	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	15		T152	7		T66	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T45	2		T48	1		T31	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	15		T7	12		T109	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T150	4		T108	10		T48	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1134	1			T2	16		T38	15		T43	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	13		T7	3		T41	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T6	15		T53	1		T57	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	1		T10	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T40	1		T108	21		T49	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	7		T9	1		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	4		T38	7		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T170	1		T214	14		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T1	3		T4	8		T7	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T44	7		T64	12		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T152	19		T120	7		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T52	12		T152	10		T123	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	1		T152	8		T66	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T45	5		T62	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T4	16		T7	13		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T161	1		T215	1		T108	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	13		T71	3		T154	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T56	1		T41	16		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T2	4		T56	1		T38	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	14		T161	1		T116	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T2	17		T170	1		T150	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T7	4		T216	1		T217	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16607	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T218	15		T219	10		T220	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T53	8		T51	4		T159	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T150	7		T119	14		T30	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T221	1		T96	14		T231	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	11		T10	11		T151	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T4	5		T38	4		T172	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T157	11		T13	3		T194	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	8		T10	8		T71	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T44	1		T47	3		T190	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T152	16		T151	7		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T152	11		T173	9		T232	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	1		T152	10		T66	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T45	3		T192	12		T233	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T4	15		T60	35		T39	35
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T215	21		T48	2		T157	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T71	3		T154	12		T163	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T41	15		T153	10		T150	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T2	2		T38	2		T62	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T224	9		T158	7		T58	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T2	15		T150	15		T225	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T216	13		T188	10		T226	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T220	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T53	1		T32	14		T128	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T150	9		T227	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T57	9		T108	21		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	1		T10	1		T119	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	15		T40	1		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	7		T9	1		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T38	7		T123	3		T66	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T170	1		T151	1		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T1	3		T4	4		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T44	7		T64	12		T214	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	8		T7	9		T71	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T52	12		T152	10		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	1		T120	7		T66	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T62	1		T154	1		T123	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T4	16		T152	8		T228	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T161	1		T45	5		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	17		T7	13		T109	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T153	1		T150	5		T108	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1510	1			T2	17		T11	2		T60	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T1	14		T7	4		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T53	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T150	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T51	4		T190	15		T175	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T119	14		T167	19		T59	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T172	7		T159	2		T234	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	11		T10	11		T30	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T38	4		T230	7		T231	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T151	6		T47	3		T235	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	5		T10	8		T152	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T44	1		T190	17		T194	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	8		T71	9		T151	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T152	11		T236	9		T173	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T9	1		T50	2		T237	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T192	12		T233	11		T166	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T4	15		T152	10		T66	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T45	3		T215	21		T48	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T2	2		T163	15		T238	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T153	10		T150	2		T48	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1511	1			T2	15		T60	35		T38	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T41	15		T114	18		T119	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21991

1

T1

14

T3

134

T4

47

auto[ADC_CTRL_FILTER_COND_OUT]

3881

1

T1

10

T2

51

T4

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19751

1

T1

10

T2

6

T3

134

auto[1]

6121

1

T1

14

T2

45

T4

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	317	1			T2	6		T7	9		T152	35
values[0]	3	1			T227	3		-	-		-	-
values[1]	568	1			T56	1		T41	31		T170	1
values[2]	647	1			T2	32		T7	4		T9	2
values[3]	881	1			T1	7		T4	9		T53	9
values[4]	886	1			T4	31		T9	12		T10	9
values[5]	2747	1			T1	14		T6	15		T7	13
values[6]	790	1			T5	1		T170	1		T150	7
values[7]	938	1			T52	12		T38	18		T161	1
values[8]	650	1			T10	12		T40	1		T71	14
values[9]	840	1			T1	3		T2	13		T4	16
minimum	16605	1			T3	134		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	570	1			T2	32		T56	1		T41	31
values[1]	627	1			T7	4		T9	2		T56	1
values[2]	959	1			T1	7		T4	40		T10	9
values[3]	2845	1			T9	12		T11	2		T12	1
values[4]	807	1			T1	14		T5	1		T6	15
values[5]	646	1			T161	1		T170	1		T150	7
values[6]	818	1			T52	12		T38	18		T40	1
values[7]	774	1			T10	12		T71	16		T153	11
values[8]	910	1			T1	3		T2	19		T4	16
values[9]	109	1			T7	9		T116	4		T174	3
minimum	16807	1			T3	134		T8	14		T61	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T56	1		T170	1		T119	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	16		T41	16		T30	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T56	1		T57	1		T45	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	1		T9	2		T71	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	16		T10	9		T62	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T1	1		T4	6		T53	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1467	1			T11	2		T60	38		T54	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T9	12		T12	1		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T36	1		T228	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T5	1		T6	1		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T170	1		T150	3		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T161	1		T223	1		T172	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T152	11		T119	15		T151	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T52	1		T38	3		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T71	11		T153	11		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	12		T64	1		T66	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T4	9		T10	1		T44	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	1		T2	4		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T7	1		T116	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T16	3		T239	15		T240	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16545	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T155	10		T241	1		T242	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T119	4		T230	12		T227	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T2	16		T41	15		T30	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T57	8		T45	2		T176	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	3		T71	2		T108	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	15		T62	5		T173	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	6		T4	3		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	837	1			T43	7		T169	27		T243	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T38	6		T152	9		T150	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	13		T174	12		T193	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	14		T7	12		T156	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T150	4		T47	3		T109	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T244	8		T167	20		T245	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T152	7		T119	9		T13	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T52	11		T38	15		T108	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T71	5		T120	6		T154	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T64	11		T31	11		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	7		T44	2		T150	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	2		T2	15		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T7	8		T116	3		T174	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T16	2		T240	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T64	1		T45	4		T120	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T155	12		T242	12		T246	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T7	1		T108	1		T26	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T2	3		T152	17		T151	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T227	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T56	1		T170	1		T119	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T41	16		T155	10		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T56	1		T57	1		T45	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	16		T7	1		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T62	3		T176	13		T234	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T1	1		T4	6		T53	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	16		T10	9		T119	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T9	12		T12	1		T152	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1469	1			T1	1		T11	2		T60	38
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T6	1		T7	1		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T170	1		T150	3		T47	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	1		T156	13		T172	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T152	11		T119	15		T151	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T52	1		T38	3		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T71	10		T120	1		T154	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	12		T40	1		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T4	9		T10	1		T44	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T2	1		T32	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T7	8		T174	2		T231	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T2	3		T152	18		T247	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T227	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T119	4		T123	2		T231	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T41	15		T155	12		T192	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T57	8		T45	2		T230	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	16		T7	3		T71	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T62	5		T176	11		T173	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	6		T4	3		T46	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T4	15		T119	3		T109	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T152	9		T150	9		T48	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	845	1			T1	13		T43	7		T169	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	14		T7	12		T38	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T150	4		T47	3		T109	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T156	8		T167	20		T245	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T152	7		T119	9		T123	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T52	11		T38	15		T108	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T71	4		T120	6		T154	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T31	11		T158	2		T230	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T4	7		T44	2		T71	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	2		T2	12		T32	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1