Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22236

1

T1

10

T2

32

T3

134

auto[ADC_CTRL_FILTER_COND_OUT]

3636

1

T1

14

T2

19

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19498

1

T1

3

T3

132

T4

9

auto[1]

6374

1

T1

21

T2

51

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	480	1			T3	2		T53	2		T41	31
values[0]	77	1			T6	15		T164	1		T58	13
values[1]	554	1			T2	6		T215	22		T47	8
values[2]	3081	1			T2	13		T4	16		T7	13
values[3]	602	1			T10	1		T71	6		T153	11
values[4]	565	1			T5	1		T150	25		T46	7
values[5]	855	1			T7	4		T9	12		T12	1
values[6]	786	1			T2	32		T10	12		T44	8
values[7]	780	1			T1	7		T40	1		T161	1
values[8]	576	1			T4	31		T7	9		T10	9
values[9]	1325	1			T1	17		T4	9		T9	2
minimum	16191	1			T3	132		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	922	1			T2	6		T6	15		T7	13
values[1]	2848	1			T2	13		T4	16		T11	2
values[2]	690	1			T10	1		T71	6		T45	8
values[3]	592	1			T5	1		T7	4		T152	18
values[4]	875	1			T2	32		T9	12		T10	12
values[5]	795	1			T44	8		T38	18		T40	1
values[6]	679	1			T1	7		T57	9		T40	1
values[7]	747	1			T1	3		T4	31		T7	9
values[8]	880	1			T1	14		T9	2		T56	1
values[9]	230	1			T4	9		T41	31		T114	19
minimum	16614	1			T3	134		T8	14		T61	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T7	1		T53	9		T150	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	3		T6	1		T52	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T4	9		T11	2		T60	38
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	1		T56	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T10	1		T71	4		T45	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T46	5		T116	1		T151	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T5	1		T7	1		T152	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T150	16		T119	4		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T2	16		T10	12		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	12		T150	8		T123	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T44	6		T40	1		T223	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T38	3		T161	1		T152	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T57	1		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T172	8		T244	1		T51	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	1		T4	16		T10	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	1		T161	1		T119	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	2		T38	5		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	1		T56	1		T71	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T4	6		T273	1		T267	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T41	16		T114	19		T151	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T59	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T7	12		T150	4		T47	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T2	3		T6	14		T52	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	888	1			T4	7		T43	7		T152	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	12		T155	12		T109	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T71	2		T45	2		T154	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T46	2		T116	3		T229	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T7	3		T152	7		T224	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T150	9		T119	3		T109	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	16		T32	13		T71	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T150	8		T123	27		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T44	2		T223	9		T192	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T38	15		T152	18		T62	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	6		T57	8		T64	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T51	14		T174	2		T324	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	2		T4	15		T119	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	8		T119	4		T108	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T38	6		T66	14		T13	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	13		T71	4		T108	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T4	3		T267	10		T325	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T41	15		T292	12		T326	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T59	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	416	1			T3	2		T53	2		T63	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T41	16		T158	8		T230	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T164	1		T309	6		T327	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T6	1		T58	10		T328	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T47	5		T128	2		T223	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	3		T215	22		T48	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T4	9		T7	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	1		T52	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	1		T71	4		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T153	11		T116	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	1		T66	1		T224	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T150	16		T46	5		T119	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T7	1		T12	1		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	12		T150	8		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	16		T10	12		T44	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T38	3		T62	3		T123	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T40	1		T64	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T161	1		T152	17		T151	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	16		T10	9		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	1		T119	3		T172	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T1	1		T4	6		T9	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T1	1		T56	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16074	1			T3	132		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T41	15		T158	3		T230	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T309	5		T329	5		T319	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T6	14		T58	3		T328	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T47	3		T163	13		T50	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T2	3		T48	1		T247	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T4	7		T7	12		T43	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	12		T52	11		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T71	2		T120	6		T154	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T116	3		T193	7		T330	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T224	4		T159	7		T195	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T150	9		T46	2		T119	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	3		T32	13		T71	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T150	8		T123	2		T167	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	16		T44	2		T66	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T38	15		T62	5		T123	27
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	6		T64	11		T250	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T152	18		T192	17		T51	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	15		T57	8		T119	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T7	8		T119	4		T196	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T1	2		T4	3		T38	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T1	13		T71	4		T108	30
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T7	13		T53	1		T150	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	4		T6	15		T52	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T4	8		T11	2		T60	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T2	13		T56	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	1		T71	3		T45	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T46	5		T116	4		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	1		T7	4		T152	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T150	10		T119	4		T109	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T2	17		T10	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	1		T150	9		T123	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T44	7		T40	1		T223	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T38	16		T161	1		T152	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	7		T57	9		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T172	1		T244	1		T51	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	3		T4	16		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	9		T161	1		T119	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T9	1		T38	7		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T1	14		T56	1		T71	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T4	4		T273	1		T267	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T41	16		T114	1		T151	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T59	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T53	8		T150	2		T47	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	2		T215	21		T48	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T4	8		T60	35		T39	35
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T153	10		T155	9		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T71	3		T45	3		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T46	2		T151	7		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T152	10		T224	9		T159	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T150	15		T119	3		T176	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	15		T10	11		T66	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T9	11		T150	7		T172	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T44	1		T26	13		T28	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T38	2		T152	16		T62	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T261	14		T250	9		T186	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T172	7		T51	4		T234	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	15		T10	8		T119	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T119	2		T156	12		T248	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	1		T38	4		T13	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T71	9		T176	11		T172	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T4	5		T325	12		T331	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T41	15		T114	18		T151	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T59	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	416	1			T3	2		T53	2		T63	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T41	16		T158	4		T230	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T164	1		T309	7		T327	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T6	15		T58	10		T328	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T47	5		T128	2		T223	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T2	4		T215	1		T48	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T4	8		T7	13		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	13		T52	12		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	1		T71	3		T120	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T153	1		T116	4		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T66	1		T224	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T150	10		T46	5		T119	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	4		T12	1		T32	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	1		T150	9		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	17		T10	1		T44	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T38	16		T62	6		T123	29
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	7		T40	1		T64	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T161	1		T152	19		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	16		T10	1		T57	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	9		T119	5		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T1	3		T4	4		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	415	1			T1	14		T56	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16191	1			T3	132		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T41	15		T158	7		T230	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T309	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T58	3		T328	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T47	3		T163	15		T28	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T2	2		T215	21		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T4	8		T60	35		T53	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T155	9		T30	11		T31	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T71	3		T154	12		T48	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T153	10		T236	10		T281	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T224	9		T159	2		T190	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T150	15		T46	2		T119	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T152	10		T26	13		T262	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	11		T150	7		T167	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	15		T10	11		T44	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T38	2		T62	2		T172	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T260	10		T261	14		T250	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T152	16		T151	2		T192	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	15		T10	8		T119	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T119	2		T172	7		T234	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	5		T9	1		T38	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T71	9		T114	18		T151	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12