Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22426

1

T1

3

T2

51

T3

134

auto[ADC_CTRL_FILTER_COND_OUT]

3446

1

T1

21

T5

1

T7

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19780

1

T1

7

T2

6

T3

134

auto[1]

6092

1

T1

17

T2

45

T4

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	285	1			T2	32		T7	4		T56	1
values[0]	25	1			T150	16		T128	1		T280	5
values[1]	796	1			T5	1		T10	1		T53	9
values[2]	753	1			T1	7		T6	15		T9	12
values[3]	521	1			T38	11		T170	1		T123	3
values[4]	795	1			T1	3		T4	9		T10	9
values[5]	756	1			T4	16		T7	9		T52	12
values[6]	650	1			T9	2		T152	18		T120	7
values[7]	669	1			T4	31		T161	1		T45	8
values[8]	802	1			T2	19		T7	13		T41	31
values[9]	3215	1			T1	14		T11	2		T60	38
minimum	16605	1			T3	134		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	832	1			T5	1		T6	15		T10	1
values[1]	645	1			T1	7		T9	12		T10	12
values[2]	559	1			T4	9		T38	11		T170	1
values[3]	767	1			T1	3		T7	9		T10	9
values[4]	785	1			T4	16		T52	12		T152	56
values[5]	692	1			T9	2		T152	18		T45	8
values[6]	2747	1			T4	31		T11	2		T60	38
values[7]	728	1			T2	19		T7	13		T56	1
values[8]	1109	1			T1	14		T56	1		T38	18
values[9]	210	1			T2	32		T7	4		T170	1
minimum	16798	1			T3	134		T8	14		T61	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	1		T53	9		T57	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	1		T10	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T40	1		T108	1		T49	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	1		T9	12		T10	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	6		T38	5		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T170	1		T214	1		T157	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T7	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	9		T64	1		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T4	9		T152	17		T151	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T52	1		T152	12		T223	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T152	11		T120	1		T50	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	2		T45	6		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1481	1			T4	16		T11	2		T60	38
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T161	1		T215	22		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T2	4		T7	1		T71	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T56	1		T41	16		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T56	1		T38	3		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T1	1		T161	1		T116	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T2	16		T170	1		T150	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T7	1		T332	1		T333	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16546	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T245	1		T292	14		T334	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	14		T57	8		T229	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T71	1		T150	8		T119	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T108	20		T159	7		T221	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	6		T123	12		T167	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T4	3		T38	6		T123	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T214	13		T13	3		T222	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	2		T7	8		T44	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T64	11		T47	3		T192	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	7		T152	18		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T52	11		T152	9		T173	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T152	7		T120	6		T50	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T45	2		T123	15		T66	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	896	1			T4	15		T43	7		T169	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T108	10		T48	1		T31	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	15		T7	12		T71	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T41	15		T150	4		T119	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T38	15		T62	5		T109	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	13		T116	3		T224	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T2	16		T150	9		T225	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T7	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T32	13		T64	1		T45	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T245	7		T292	12		T334	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	16		T56	1		T38	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T7	1		T261	15		T250	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T128	1		T280	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T150	8		T227	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T53	9		T57	1		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	1		T10	1		T119	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	1		T40	1		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	1		T9	12		T10	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T38	5		T123	1		T66	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T170	1		T128	1		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	1		T4	6		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	9		T64	1		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	9		T7	1		T152	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T52	1		T152	12		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T152	11		T120	1		T66	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	2		T62	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T4	16		T228	2		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T161	1		T45	6		T215	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	4		T7	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T41	16		T153	11		T150	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1705	1			T11	2		T60	38		T54	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T1	1		T56	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T2	16		T38	15		T150	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T7	3		T250	2		T195	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T280	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T150	8		T227	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T57	8		T32	13		T30	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T119	9		T167	20		T59	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	14		T108	20		T159	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	6		T71	1		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T38	6		T123	2		T230	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T214	13		T13	3		T222	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	2		T4	3		T44	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T64	11		T47	3		T192	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T4	7		T7	8		T152	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T52	11		T152	9		T173	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T152	7		T120	6		T66	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T123	15		T223	9		T192	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	15		T310	9		T174	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T45	2		T48	1		T66	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	15		T7	12		T163	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T41	15		T150	4		T108	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T43	7		T71	2		T169	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	13		T116	3		T119	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	15		T53	1		T57	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T10	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T40	1		T108	21		T49	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	7		T9	1		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	4		T38	7		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T170	1		T214	14		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T1	3		T7	9		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	1		T64	12		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	8		T152	19		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T52	12		T152	10		T223	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T152	8		T120	7		T50	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	1		T45	5		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T4	16		T11	2		T60	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T161	1		T215	1		T108	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	17		T7	13		T71	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T56	1		T41	16		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T56	1		T38	16		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T1	14		T161	1		T116	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T2	17		T170	1		T150	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T7	4		T332	1		T333	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16680	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T245	8		T292	13		T334	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T53	8		T234	2		T173	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T150	7		T119	14		T30	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T159	2		T221	1		T96	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	11		T10	11		T151	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T4	5		T38	4		T172	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T157	11		T13	3		T194	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T44	1		T71	9		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	8		T47	3		T190	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	8		T152	16		T151	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T152	11		T173	9		T232	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T152	10		T50	2		T273	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	1		T45	3		T66	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T4	15		T60	35		T39	35
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T215	21		T48	2		T172	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	2		T71	3		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T41	15		T153	10		T150	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T38	2		T62	2		T151	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T224	9		T158	7		T58	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T2	15		T150	15		T28	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T51	4		T190	15		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T292	13		T180	13		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T2	17		T56	1		T38	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T7	4		T261	1		T250	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T128	1		T280	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T150	9		T227	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T53	1		T57	9		T32	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	1		T10	1		T119	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	15		T40	1		T108	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	7		T9	1		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T38	7		T123	3		T66	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T170	1		T128	1		T214	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T1	3		T4	4		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	1		T64	12		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	8		T7	9		T152	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T52	12		T152	10		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T152	8		T120	7		T66	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	1		T62	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	16		T228	2		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T161	1		T45	5		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	17		T7	13		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T41	16		T153	1		T150	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T11	2		T60	3		T54	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T1	14		T56	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T2	15		T38	2		T150	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T261	14		T250	3		T188	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T150	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T53	8		T51	4		T190	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T119	14		T167	19		T59	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T172	7		T159	2		T234	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	11		T10	11		T151	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T38	4		T230	7		T286	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T235	3		T157	11		T13	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	5		T44	1		T71	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	8		T47	3		T190	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	8		T152	16		T151	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T152	11		T173	9		T175	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T152	10		T50	2		T237	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	1		T192	12		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	15		T172	6		T164	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T45	3		T215	21		T48	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	2		T163	15		T272	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T41	15		T153	10		T150	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T60	35		T39	35		T71	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T114	18		T119	2		T224	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12