Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21953

1

T1

14

T3

134

T4

47

auto[ADC_CTRL_FILTER_COND_OUT]

3919

1

T1

10

T2

51

T4

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19696

1

T1

10

T2

6

T3

134

auto[1]

6176

1

T1

14

T2

45

T4

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	69	1			T174	3		T239	15		T240	22
values[0]	32	1			T227	3		T242	25		T335	3
values[1]	562	1			T56	1		T41	31		T170	1
values[2]	643	1			T2	32		T7	4		T9	2
values[3]	857	1			T1	7		T4	9		T53	9
values[4]	980	1			T4	31		T7	13		T9	12
values[5]	2628	1			T1	14		T6	15		T11	2
values[6]	830	1			T5	1		T36	1		T150	7
values[7]	823	1			T52	12		T38	18		T161	1
values[8]	781	1			T10	12		T40	2		T119	24
values[9]	1062	1			T1	3		T2	19		T4	16
minimum	16605	1			T3	134		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	788	1			T2	32		T56	1		T41	31
values[1]	511	1			T7	4		T9	2		T56	1
values[2]	978	1			T1	7		T4	40		T10	9
values[3]	2803	1			T9	12		T11	2		T12	1
values[4]	909	1			T1	14		T5	1		T6	15
values[5]	686	1			T161	1		T170	1		T150	7
values[6]	802	1			T52	12		T38	18		T40	1
values[7]	784	1			T10	12		T71	16		T153	11
values[8]	791	1			T1	3		T2	19		T7	9
values[9]	193	1			T4	16		T116	4		T26	14
minimum	16627	1			T3	134		T8	14		T61	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T56	1		T170	1		T119	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	16		T41	16		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T56	1		T57	1		T45	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	1		T9	2		T71	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T4	16		T10	9		T62	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T1	1		T4	6		T53	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T11	2		T60	38		T54	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T9	12		T12	1		T152	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	1		T36	1		T228	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T5	1		T6	1		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T170	1		T150	3		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T161	1		T223	1		T172	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T152	11		T119	15		T151	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T52	1		T38	3		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T71	11		T153	11		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	12		T64	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	1		T10	1		T44	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	1		T2	4		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T4	9		T116	1		T26	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T260	11		T232	10		T177	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T155	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T119	4		T123	2		T230	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	16		T41	15		T108	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T57	8		T45	2		T174	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	3		T71	2		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T4	15		T62	5		T176	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	6		T4	3		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	844	1			T43	7		T169	27		T243	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T152	9		T150	9		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	13		T58	3		T174	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	14		T7	12		T38	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T150	4		T47	3		T109	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T244	8		T167	20		T245	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T152	7		T119	9		T13	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T52	11		T38	15		T108	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T71	5		T120	6		T154	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T64	11		T123	12		T31	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	8		T44	2		T150	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	2		T2	15		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T4	7		T116	3		T174	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T232	9		T16	2		T336	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T155	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T174	1		T337	17		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T239	15		T240	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T227	2		T335	1		T338	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T242	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T56	1		T170	1		T119	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T41	16		T155	10		T30	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T57	1		T45	6		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	16		T7	1		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T56	1		T62	3		T176	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T1	1		T4	6		T53	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	16		T10	9		T119	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T7	1		T9	12		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1455	1			T1	1		T11	2		T60	38
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	1		T38	5		T151	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T36	1		T150	3		T47	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	1		T156	13		T172	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T152	11		T151	3		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T52	1		T38	3		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T119	15		T120	1		T154	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	12		T40	2		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T4	9		T7	1		T10	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	1		T2	4		T32	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T174	2		T337	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T240	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T227	1		T335	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T242	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T119	4		T123	2		T231	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T41	15		T155	12		T30	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T57	8		T45	2		T280	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	16		T7	3		T108	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T62	5		T176	11		T173	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	6		T4	3		T71	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	15		T119	3		T109	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	12		T152	9		T150	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	797	1			T1	13		T43	7		T169	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	14		T38	6		T159	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T150	4		T47	3		T109	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T156	8		T167	20		T245	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T152	7		T123	15		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T52	11		T38	15		T108	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T119	9		T120	6		T154	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T31	11		T158	2		T230	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T4	7		T7	8		T44	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	2		T2	15		T32	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T56	1		T170	1		T119	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	17		T41	16		T108	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T56	1		T57	9		T45	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	4		T9	1		T71	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T4	16		T10	1		T62	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T1	7		T4	4		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T11	2		T60	3		T54	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	1		T12	1		T152	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	14		T36	1		T228	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T5	1		T6	15		T7	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T170	1		T150	5		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T161	1		T223	1		T172	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T152	8		T119	10		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T52	12		T38	16		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T71	7		T153	1		T120	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	1		T64	12		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	9		T10	1		T44	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T1	3		T2	17		T32	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T4	8		T116	4		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T260	1		T232	10		T177	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T155	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T119	2		T235	3		T230	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	15		T41	15		T30	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T45	3		T234	2		T339	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T9	1		T71	3		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	15		T10	8		T62	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T4	5		T53	8		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T60	35		T39	35		T171	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	11		T152	11		T150	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T58	3		T179	12		T249	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T38	4		T151	6		T215	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T150	2		T47	3		T224	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T172	13		T167	13		T250	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T152	10		T119	14		T151	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T38	2		T157	4		T236	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T71	9		T153	10		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	11		T31	13		T230	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T44	1		T150	7		T272	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	2		T152	16		T114	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T4	8		T26	13		T28	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T260	10		T232	9		T177	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T155	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T174	3		T337	13		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T239	1		T240	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T227	3		T335	3		T338	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T242	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T56	1		T170	1		T119	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T41	16		T155	13		T30	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T57	9		T45	5		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	17		T7	4		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T56	1		T62	6		T176	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T1	7		T4	4		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T4	16		T10	1		T119	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T7	13		T9	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1113	1			T1	14		T11	2		T60	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	15		T38	7		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T36	1		T150	5		T47	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T5	1		T156	9		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T152	8		T151	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T52	12		T38	16		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T119	10		T120	7		T154	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	1		T40	2		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T4	8		T7	9		T10	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T1	3		T2	17		T32	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T337	16		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T239	14		T240	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T242	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T119	2		T259	7		T254	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T41	15		T155	9		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T45	3		T235	3		T280	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T2	15		T9	1		T48	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T62	2		T176	12		T234	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T4	5		T53	8		T71	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	15		T10	8		T119	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T9	11		T152	11		T150	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T60	35		T39	35		T171	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T38	4		T151	6		T215	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T150	2		T47	3		T51	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T156	12		T172	6		T167	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T152	10		T151	2		T224	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T38	2		T172	7		T157	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T119	14		T154	12		T172	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	11		T31	13		T158	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T4	8		T44	1		T71	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	2		T152	16		T114	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12