Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22165

1

T2

32

T3

134

T4

56

auto[ADC_CTRL_FILTER_COND_OUT]

3707

1

T1

24

T2

19

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T1

24

T2

32

T3

132

auto[1]

6107

1

T2

19

T3

2

T4

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	632	1			T3	2		T53	2		T38	11
values[0]	30	1			T164	1		T309	11		T327	1
values[1]	677	1			T2	6		T6	15		T52	12
values[2]	2921	1			T2	13		T4	16		T7	13
values[3]	650	1			T10	1		T71	6		T153	11
values[4]	645	1			T5	1		T152	18		T150	25
values[5]	839	1			T7	4		T9	12		T10	12
values[6]	788	1			T2	32		T38	18		T62	8
values[7]	703	1			T1	7		T44	8		T40	1
values[8]	599	1			T4	31		T7	9		T10	9
values[9]	1197	1			T1	17		T4	9		T9	2
minimum	16191	1			T3	132		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	766	1			T2	6		T6	15		T7	13
values[1]	2881	1			T2	13		T4	16		T11	2
values[2]	661	1			T10	1		T71	6		T46	7
values[3]	643	1			T5	1		T7	4		T32	14
values[4]	811	1			T2	32		T9	12		T10	12
values[5]	769	1			T44	8		T38	18		T40	1
values[6]	755	1			T1	7		T57	9		T40	1
values[7]	722	1			T1	3		T4	31		T7	9
values[8]	955	1			T1	14		T4	9		T9	2
values[9]	175	1			T41	31		T114	19		T157	12
minimum	16734	1			T3	134		T8	14		T61	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T7	1		T53	9		T150	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	3		T6	1		T52	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T4	9		T11	2		T60	38
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	1		T170	1		T155	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	1		T151	8		T154	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T71	4		T46	5		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	1		T7	1		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T152	11		T150	16		T119	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T2	16		T10	12		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	12		T150	8		T123	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T44	6		T40	1		T152	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T38	3		T161	1		T62	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T40	1		T64	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T1	1		T57	1		T172	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	16		T10	9		T119	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	1		T7	1		T119	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T4	6		T9	2		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T1	1		T56	1		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T157	12		T273	1		T267	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T41	16		T114	19		T158	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16536	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T223	1		T58	10		T272	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T7	12		T150	4		T47	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T2	3		T6	14		T52	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	911	1			T4	7		T43	7		T152	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	12		T155	12		T30	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T154	2		T280	14		T340	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T71	2		T46	2		T116	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	3		T32	13		T224	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T152	7		T150	9		T119	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	16		T71	1		T66	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T150	8		T123	27		T310	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T44	2		T152	18		T223	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T38	15		T62	5		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T64	11		T299	3		T250	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	6		T57	8		T51	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	15		T119	9		T159	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	2		T7	8		T119	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	3		T66	14		T13	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	13		T38	6		T71	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T267	10		T325	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T41	15		T158	3		T326	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T64	1		T45	4		T120	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T58	3		T309	5		T16	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	438	1			T3	2		T53	2		T63	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T38	5		T41	16		T176	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T164	1		T327	1		T319	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T309	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T47	5		T128	2		T163	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T2	3		T6	1		T52	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T4	9		T7	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	1		T170	1		T155	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T10	1		T153	11		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T71	4		T116	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	1		T151	8		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T152	11		T150	16		T46	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T7	1		T10	12		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	12		T150	8		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	16		T126	1		T66	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T38	3		T62	3		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T44	6		T40	1		T152	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	1		T161	1		T151	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	16		T10	9		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	1		T57	1		T119	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T4	6		T9	2		T228	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T1	2		T56	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16074	1			T3	132		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T13	3		T166	8		T269	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T38	6		T41	15		T176	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T319	12		T328	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T309	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T47	3		T163	13		T244	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T2	3		T6	14		T52	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T4	7		T7	12		T43	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	12		T155	12		T30	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T120	6		T154	2		T48	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T71	2		T116	3		T178	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T224	4		T340	1		T300	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T152	7		T150	9		T46	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	3		T32	13		T71	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T150	8		T123	2		T310	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	16		T66	11		T223	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T38	15		T62	5		T123	27
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T44	2		T152	18		T64	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	6		T51	14		T250	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	15		T119	9		T159	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	8		T57	8		T119	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T4	3		T66	14		T31	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T1	15		T71	4		T108	30
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T7	13		T53	1		T150	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T2	4		T6	15		T52	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T4	8		T11	2		T60	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T2	13		T170	1		T155	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	1		T151	1		T154	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T71	3		T46	5		T116	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	1		T7	4		T32	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T152	8		T150	10		T119	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T2	17		T10	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	1		T150	9		T123	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T44	7		T40	1		T152	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T38	16		T161	1		T62	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T40	1		T64	12		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T1	7		T57	9		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	16		T10	1		T119	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	3		T7	9		T119	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T4	4		T9	1		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T1	14		T56	1		T38	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T157	1		T273	1		T267	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T41	16		T114	1		T158	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16654	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T223	1		T58	10		T272	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T53	8		T150	2		T47	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T2	2		T215	21		T48	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T4	8		T60	35		T39	35
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T155	9		T30	11		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T151	7		T154	12		T235	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T71	3		T46	2		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T224	9		T159	2		T294	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T152	10		T150	15		T119	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T2	15		T10	11		T66	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	11		T150	7		T172	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T44	1		T152	16		T192	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T38	2		T62	2		T151	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T28	2		T250	6		T186	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T172	7		T51	4		T234	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	15		T10	8		T119	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T119	2		T156	12		T248	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	5		T9	1		T13	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T38	4		T71	9		T151	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T157	11		T325	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T41	15		T114	18		T158	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T28	17		T341	7		T320	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T58	3		T309	4		T16	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	460	1			T3	2		T53	2		T63	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T38	7		T41	16		T176	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T164	1		T327	1		T319	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T309	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T47	5		T128	2		T163	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T2	4		T6	15		T52	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T4	8		T7	13		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	13		T170	1		T155	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	1		T153	1		T120	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T71	3		T116	4		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	1		T151	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T152	8		T150	10		T46	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T7	4		T10	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	1		T150	9		T123	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	17		T126	1		T66	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T38	16		T62	6		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T44	7		T40	1		T152	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	7		T161	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T4	16		T10	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	9		T57	9		T119	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T4	4		T9	1		T228	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T1	17		T56	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16191	1			T3	132		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T13	3		T166	2		T255	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T38	4		T41	15		T176	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T328	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T309	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T47	3		T163	15		T28	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T2	2		T215	21		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T4	8		T60	35		T53	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T155	9		T30	11		T31	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T153	10		T154	12		T48	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T71	3		T236	10		T272	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T151	7		T224	9		T340	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T152	10		T150	15		T46	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T10	11		T262	4		T159	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T9	11		T150	7		T167	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	15		T66	10		T26	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T38	2		T62	2		T172	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T44	1		T152	16		T28	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T151	2		T172	7		T51	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T4	15		T10	8		T119	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T119	2		T234	2		T248	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	5		T9	1		T157	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T71	9		T114	18		T151	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12