Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22424

1

T1

10

T2

38

T3

134

auto[ADC_CTRL_FILTER_COND_OUT]

3448

1

T1

14

T2

13

T4

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19614

1

T1

7

T3

134

T4

16

auto[1]

6258

1

T1

17

T2

51

T4

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	319	1			T7	4		T53	9		T154	15
values[0]	85	1			T4	31		T59	9		T249	25
values[1]	740	1			T4	16		T9	2		T152	21
values[2]	909	1			T4	9		T9	12		T10	1
values[3]	783	1			T1	17		T2	45		T56	1
values[4]	636	1			T10	12		T57	9		T71	14
values[5]	2761	1			T7	9		T10	9		T11	2
values[6]	481	1			T7	13		T44	8		T40	1
values[7]	926	1			T2	6		T52	12		T38	11
values[8]	561	1			T5	1		T36	1		T38	18
values[9]	1066	1			T1	7		T6	15		T12	1
minimum	16605	1			T3	134		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	831	1			T4	16		T9	2		T150	16
values[1]	816	1			T1	3		T4	9		T9	12
values[2]	765	1			T1	14		T2	45		T56	1
values[3]	2755	1			T10	12		T11	2		T60	38
values[4]	562	1			T7	22		T10	9		T56	1
values[5]	630	1			T44	8		T52	12		T40	1
values[6]	795	1			T2	6		T5	1		T38	29
values[7]	802	1			T6	15		T36	1		T150	25
values[8]	884	1			T1	7		T7	4		T12	1
values[9]	161	1			T53	9		T108	1		T172	8
minimum	16871	1			T3	134		T4	31		T8	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T150	8		T278	1		T31	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	9		T9	2		T48	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T4	6		T62	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T9	12		T10	1		T41	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	16		T161	2		T46	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T2	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T11	2		T60	38		T54	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	12		T151	8		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	2		T10	9		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T152	11		T28	18		T272	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T40	1		T152	17		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T44	6		T52	1		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	3		T5	1		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T38	3		T64	1		T119	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	1		T151	7		T155	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T36	1		T150	16		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T1	1		T7	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T32	1		T40	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T53	9		T157	5		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T108	1		T172	8		T261	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16590	1			T3	134		T4	16		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T120	1		T59	4		T160	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T150	8		T31	4		T192	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	7		T48	1		T30	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	2		T4	3		T62	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T41	15		T108	10		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	16		T46	2		T31	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	13		T2	12		T116	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T57	8		T43	7		T71	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T167	12		T230	5		T267	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	20		T71	1		T150	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T152	7		T75	1		T336	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T152	18		T119	9		T109	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T44	2		T52	11		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	3		T38	6		T71	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T38	15		T64	11		T119	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	14		T155	12		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T150	9		T123	15		T310	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	6		T7	3		T154	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T32	13		T176	11		T13	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T308	11		T282	4		T311	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T303	1		T342	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	15		T152	9		T64	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T120	6		T59	5		T175	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T7	1		T53	9		T154	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T108	1		T128	1		T176	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T4	16		T343	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T59	4		T249	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T152	12		T150	8		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	9		T9	2		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T4	6		T62	3		T66	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T9	12		T10	1		T41	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T2	16		T161	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T2	1		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T57	1		T71	10		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	12		T151	8		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T7	1		T10	9		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T152	11		T288	1		T272	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	1		T40	1		T152	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T44	6		T170	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	3		T38	5		T71	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T52	1		T64	1		T119	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T5	1		T114	19		T151	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T36	1		T38	3		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	392	1			T1	1		T6	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T32	1		T40	1		T150	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T7	3		T154	2		T47	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T176	11		T30	10		T268	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T4	15		T343	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T59	5		T249	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T152	9		T150	8		T192	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T4	7		T120	6		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	3		T62	5		T66	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T41	15		T223	9		T247	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	2		T2	16		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	13		T2	12		T116	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T57	8		T71	4		T109	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T66	14		T167	12		T230	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T7	8		T43	7		T71	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T152	7		T267	10		T309	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	12		T152	18		T119	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T44	2		T30	1		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	3		T38	6		T71	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T52	11		T64	11		T119	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T123	12		T193	14		T225	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T38	15		T123	15		T176	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T1	6		T6	14		T155	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T32	13		T150	9		T13	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T150	9		T278	1		T31	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	8		T9	1		T48	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	3		T4	4		T62	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	1		T10	1		T41	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	17		T161	2		T46	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	14		T2	13		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T11	2		T60	3		T54	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T10	1		T151	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T7	22		T10	1		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T152	8		T28	1		T272	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	1		T152	19		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T44	7		T52	12		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	4		T5	1		T38	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T38	16		T64	12		T119	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T6	15		T151	1		T155	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T36	1		T150	10		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T1	7		T7	4		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T32	14		T40	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T53	1		T157	1		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T108	1		T172	1		T261	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T3	134		T4	16		T8	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T120	7		T59	8		T160	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T150	7		T31	2		T192	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	8		T9	1		T48	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	5		T62	2		T151	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	11		T41	15		T172	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T2	15		T46	2		T31	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T172	6		T234	2		T260	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T60	35		T39	35		T71	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	11		T151	7		T26	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	8		T150	2		T236	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T152	10		T28	17		T272	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T152	16		T153	10		T119	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T44	1		T224	9		T158	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	2		T38	4		T71	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T38	2		T119	3		T48	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T151	6		T155	9		T51	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T150	15		T230	12		T174	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T154	12		T215	21		T47	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T176	12		T13	3		T30	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T53	8		T157	4		T194	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T172	7		T261	14		T286	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T4	15		T152	11		T237	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T59	1		T175	8		T96	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T7	4		T53	1		T154	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T108	1		T128	1		T176	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T4	16		T343	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T59	8		T249	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T152	10		T150	9		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	8		T9	1		T120	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T4	4		T62	6		T66	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	1		T10	1		T41	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	3		T2	17		T161	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	14		T2	13		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T57	9		T71	5		T109	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	1		T151	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T7	9		T10	1		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T152	8		T288	1		T272	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	13		T40	1		T152	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T44	7		T170	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	4		T38	7		T71	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T52	12		T64	12		T119	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	1		T114	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T36	1		T38	16		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T1	7		T6	15		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T32	14		T40	1		T150	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T53	8		T154	12		T47	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T176	12		T30	11		T261	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T4	15		T343	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T59	1		T249	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T152	11		T150	7		T192	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	8		T9	1		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	5		T62	2		T66	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	11		T41	15		T172	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	15		T46	2		T151	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T273	7		T260	22		T168	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T71	9		T163	15		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	11		T151	7		T172	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T10	8		T60	35		T39	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T152	10		T272	7		T190	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T152	16		T119	14		T286	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T44	1		T28	17		T224	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	2		T38	4		T71	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T119	3		T48	2		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T114	18		T151	6		T225	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T38	2		T176	11		T230	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T155	9		T215	21		T235	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T150	15		T172	7		T13	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12