Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T56	1		T170	1		T119	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	17		T41	16		T30	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T56	1		T57	9		T45	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	4		T9	1		T71	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T4	16		T10	1		T62	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	7		T4	4		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1147	1			T11	2		T60	3		T54	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T9	1		T12	1		T38	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	14		T36	1		T228	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	1		T6	15		T7	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T170	1		T150	5		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T161	1		T223	1		T172	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T152	8		T119	10		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T52	12		T38	16		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T71	7		T153	1		T120	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	1		T64	12		T66	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T4	8		T10	1		T44	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T1	3		T2	17		T32	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T7	9		T116	4		T174	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T16	3		T239	1		T240	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16667	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T155	13		T241	1		T242	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T119	2		T235	3		T230	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	15		T41	15		T30	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T45	3		T176	12		T234	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T9	1		T71	3		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	15		T10	8		T62	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T4	5		T53	8		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T60	35		T39	35		T171	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T9	11		T38	4		T152	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T248	8		T179	12		T249	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T151	6		T215	21		T156	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T150	2		T47	3		T224	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T172	13		T167	13		T250	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T152	10		T119	14		T151	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	2		T157	4		T236	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T71	9		T153	10		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	11		T31	13		T158	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	8		T44	1		T150	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	2		T152	16		T114	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T251	19		T252	13		T253	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T16	2		T239	14		T240	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T254	10		T255	8		T256	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T155	9		T242	12		T257	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T7	9		T108	1		T26	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T2	4		T152	19		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T227	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T56	1		T170	1		T119	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T41	16		T155	13		T192	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T56	1		T57	9		T45	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	17		T7	4		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T62	6		T176	12		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	7		T4	4		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	16		T10	1		T119	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T9	1		T12	1		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T1	14		T11	2		T60	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	15		T7	13		T38	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T170	1		T150	5		T47	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	1		T156	9		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T152	8		T119	10		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T52	12		T38	16		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T71	5		T120	7		T154	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	1		T40	1		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	8		T10	1		T44	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	3		T2	13		T32	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T26	13		T231	8		T258	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T2	2		T152	16		T151	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T119	2		T259	7		T254	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T41	15		T155	9		T237	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T45	3		T235	3		T230	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	15		T9	1		T71	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T62	2		T176	12		T234	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T4	5		T53	8		T46	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	15		T10	8		T119	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T9	11		T152	11		T150	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1148	1			T60	35		T39	35		T171	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T38	4		T151	6		T215	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T150	2		T47	3		T51	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T156	12		T172	6		T167	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T152	10		T119	14		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T38	2		T172	7		T157	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T71	9		T154	12		T172	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	11		T31	13		T158	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	8		T44	1		T153	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T114	18		T260	10		T261	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12