Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22134

1

T1

3

T2

45

T3

134

auto[ADC_CTRL_FILTER_COND_OUT]

3738

1

T1

21

T2

6

T4

56

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20044

1

T1

24

T2

51

T3

134

auto[1]

5828

1

T4

47

T6

15

T7

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T163	1		T262	7		T263	10
values[0]	39	1			T264	1		T236	10		T230	24
values[1]	797	1			T36	1		T108	21		T128	1
values[2]	783	1			T10	12		T57	9		T38	11
values[3]	754	1			T1	14		T5	1		T56	1
values[4]	644	1			T2	32		T32	14		T40	1
values[5]	664	1			T2	6		T10	9		T12	1
values[6]	688	1			T7	13		T10	1		T71	14
values[7]	689	1			T1	3		T53	9		T56	1
values[8]	2785	1			T2	13		T4	16		T7	9
values[9]	1393	1			T1	7		T4	40		T6	15
minimum	16605	1			T3	134		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	956	1			T57	9		T36	1		T161	1
values[1]	882	1			T10	12		T38	11		T161	1
values[2]	752	1			T5	1		T32	14		T40	1
values[3]	577	1			T1	14		T2	38		T10	9
values[4]	613	1			T12	1		T71	6		T152	35
values[5]	724	1			T7	13		T10	1		T56	1
values[6]	2809	1			T1	3		T4	16		T7	9
values[7]	725	1			T2	13		T4	9		T9	14
values[8]	991	1			T1	7		T4	31		T6	15
values[9]	206	1			T47	8		T108	1		T109	10
minimum	16637	1			T3	134		T8	14		T61	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T36	1		T151	8		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T57	1		T161	1		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T38	5		T161	1		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T10	12		T164	1		T51	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	1		T32	1		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T41	16		T71	1		T119	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	16		T56	1		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	1		T2	3		T10	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T71	4		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T152	17		T64	1		T28	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	1		T56	1		T71	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	1		T119	19		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T1	1		T7	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	9		T150	3		T62	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T2	1		T9	2		T152	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	6		T9	12		T44	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T151	7		T228	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	1		T4	16		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T108	1		T30	12		T262	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T47	5		T109	1		T26	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T236	10		T265	1		T266	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T223	9		T267	14		T268	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T57	8		T108	20		T66	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T38	6		T66	11		T214	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T51	14		T167	12		T250	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T32	13		T46	2		T123	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T41	15		T71	1		T119	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	16		T116	3		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T1	13		T2	3		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T71	2		T109	3		T30	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T152	18		T64	11		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	12		T71	4		T108	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T119	12		T50	2		T192	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T1	2		T7	8		T43	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T4	7		T150	4		T62	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T2	12		T152	9		T150	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	3		T44	2		T192	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T176	11		T269	7		T221	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T1	6		T4	15		T6	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T30	10		T262	2		T174	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T47	3		T109	9		T31	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T266	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T262	5		T263	6		T270	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T163	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T236	10		T230	12		T271	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T36	1		T223	1		T272	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T108	1		T128	1		T66	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T38	5		T40	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T10	12		T57	1		T41	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	1		T56	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T1	1		T119	3		T155	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T2	16		T32	1		T123	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T40	1		T71	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	1		T71	4		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	3		T10	9		T152	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	1		T71	10		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	1		T64	1		T119	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	1		T53	9		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T150	3		T62	4		T13	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1488	1			T2	1		T7	1		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	9		T192	13		T234	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T9	2		T151	10		T154	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T1	1		T4	22		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T262	2		T263	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T230	12		T271	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T223	9		T267	14		T268	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T108	20		T66	14		T247	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T38	6		T66	11		T214	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T57	8		T41	15		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T46	2		T116	3		T273	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	13		T119	4		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	16		T32	13		T123	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T71	1		T123	2		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T71	2		T109	3		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	3		T152	18		T192	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	12		T71	4		T108	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T64	11		T119	12		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	2		T120	6		T237	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T150	4		T62	5		T13	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	899	1			T2	12		T7	8		T43	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	7		T192	17		T173	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T154	2		T176	11		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T1	6		T4	18		T6	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T36	1		T151	1		T223	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T57	9		T161	1		T108	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T38	7		T161	1		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T10	1		T164	1		T51	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	1		T32	14		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T41	16		T71	2		T119	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	17		T56	1		T116	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T1	14		T2	4		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	1		T71	3		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T152	19		T64	12		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	13		T56	1		T71	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	1		T119	14		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T1	3		T7	9		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	8		T150	5		T62	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	13		T9	1		T152	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T4	4		T9	1		T44	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T151	1		T228	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T1	7		T4	16		T6	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T108	1		T30	11		T262	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T47	5		T109	10		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T236	1		T265	1		T266	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T151	7		T272	13		T260	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T247	10		T158	12		T230	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T38	4		T66	10		T273	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	11		T51	4		T167	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T46	2		T114	18		T172	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T41	15		T119	2		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	15		T163	15		T167	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	2		T10	8		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T71	3		T157	11		T167	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T152	16		T28	17		T192	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T71	9		T48	4		T59	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T119	17		T50	2		T164	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T60	35		T53	8		T39	35
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T4	8		T150	2		T62	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	1		T152	11		T150	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	5		T9	11		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T151	6		T176	12		T172	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	15		T38	2		T45	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T30	11		T262	4		T274	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T47	3		T26	13		T31	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T236	9		T266	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T262	3		T263	5		T270	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T163	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T236	1		T230	13		T271	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T36	1		T223	10		T272	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T108	21		T128	1		T66	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T38	7		T40	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	1		T57	9		T41	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	1		T56	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T1	14		T119	5		T155	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	17		T32	14		T123	29
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T40	1		T71	2		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	1		T71	3		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	4		T10	1		T152	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	13		T71	5		T108	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	1		T64	12		T119	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T1	3		T53	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T150	5		T62	7		T13	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T2	13		T7	9		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	8		T192	18		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T9	1		T151	2		T154	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T1	7		T4	20		T6	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T262	4		T263	5		T270	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T236	9		T230	11		T271	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T272	13		T260	10		T186	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T247	10		T158	12		T261	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T38	4		T151	7		T66	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	11		T41	15		T190	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T46	2		T114	18		T273	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T119	2		T155	9		T235	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	15		T163	15		T172	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T272	7		T234	13		T194	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T71	3		T157	11		T167	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	2		T10	8		T152	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T71	9		T48	4		T31	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T119	17		T50	2		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T53	8		T237	9		T173	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T150	2		T62	2		T13	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T60	35		T39	35		T152	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	8		T192	12		T234	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T9	1		T151	8		T154	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T4	20		T9	11		T44	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12