Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22467

1

T2

19

T3

134

T4

31

auto[ADC_CTRL_FILTER_COND_OUT]

3405

1

T1

24

T2

32

T4

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20046

1

T1

24

T2

13

T3

134

auto[1]

5826

1

T2

38

T6

15

T7

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	32	1			T228	1		T223	10		T163	1
values[0]	116	1			T52	12		T40	1		T237	19
values[1]	874	1			T7	4		T9	2		T152	21
values[2]	649	1			T1	3		T7	9		T9	12
values[3]	670	1			T1	14		T152	18		T150	7
values[4]	2669	1			T2	6		T11	2		T60	38
values[5]	697	1			T6	15		T12	1		T44	8
values[6]	705	1			T2	32		T71	2		T46	7
values[7]	613	1			T1	7		T7	13		T56	1
values[8]	799	1			T2	13		T4	16		T10	12
values[9]	1443	1			T4	40		T5	1		T10	10
minimum	16605	1			T3	134		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1030	1			T7	4		T9	14		T52	12
values[1]	753	1			T1	17		T62	8		T109	10
values[2]	588	1			T7	9		T71	6		T152	18
values[3]	2759	1			T2	6		T11	2		T60	38
values[4]	598	1			T6	15		T12	1		T44	8
values[5]	731	1			T1	7		T2	32		T7	13
values[6]	709	1			T4	16		T56	1		T57	9
values[7]	811	1			T2	13		T4	31		T10	12
values[8]	1043	1			T4	9		T10	10		T41	31
values[9]	195	1			T5	1		T170	1		T228	1
minimum	16655	1			T3	134		T8	14		T61	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T9	14		T52	1		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T7	1		T152	12		T153	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T62	3		T128	1		T163	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	2		T109	1		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	1		T152	11		T119	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T71	4		T150	11		T154	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1575	1			T2	3		T11	2		T60	38
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T53	9		T161	1		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T38	3		T155	10		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T6	1		T12	1		T44	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	1		T71	1		T46	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T2	16		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T57	1		T32	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	9		T56	1		T48	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	1		T4	16		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T10	12		T56	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T10	1		T41	16		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T4	6		T10	9		T152	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T170	1		T228	1		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T5	1		T272	8		T269	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16526	1			T3	134		T8	14		T61	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T52	11		T119	4		T176	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	3		T152	9		T119	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T62	5		T163	13		T30	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	15		T109	9		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	8		T152	7		T119	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T71	2		T150	12		T154	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T2	3		T43	7		T71	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T13	3		T192	11		T14	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T38	15		T155	12		T47	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T6	14		T44	2		T38	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	12		T71	1		T46	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T1	6		T2	16		T156	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T57	8		T32	13		T66	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	7		T48	1		T244	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	12		T4	15		T214	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T123	15		T224	4		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T41	15		T109	3		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T4	3		T152	18		T64	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T223	9		T186	12		T231	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T269	7		T230	12		T249	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T64	1		T45	4		T120	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T228	1		T223	1		T163	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T275	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T52	1		T40	1		T237	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T276	8		T277	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T9	2		T119	3		T278	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	1		T152	12		T119	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	1		T9	12		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	1		T153	11		T109	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T152	11		T119	4		T62	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	1		T150	3		T273	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T2	3		T11	2		T60	38
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T161	1		T71	4		T150	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T38	3		T155	10		T215	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	1		T12	1		T44	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T71	1		T46	5		T151	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	16		T172	7		T236	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	1		T57	1		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	1		T56	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	1		T49	6		T172	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T4	9		T10	12		T48	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T4	16		T10	1		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	429	1			T4	6		T5	1		T10	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T223	9		T279	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T275	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T52	11		T237	9		T222	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T276	1		T277	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T119	4		T176	11		T163	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	3		T152	9		T119	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	8		T123	2		T30	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	2		T109	9		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T152	7		T119	3		T62	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T1	13		T150	4		T280	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	904	1			T2	3		T43	7		T71	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T71	2		T150	8		T154	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T38	15		T155	12		T47	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	14		T44	2		T38	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T71	1		T46	2		T192	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T2	16		T174	7		T195	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	12		T57	8		T32	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	6		T250	5		T174	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	12		T58	3		T280	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	7		T48	1		T244	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T4	15		T41	15		T109	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T4	3		T152	18		T64	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T9	2		T52	12		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	4		T152	10		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T62	6		T128	1		T163	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	17		T109	10		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	9		T152	8		T119	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T71	3		T150	14		T154	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T2	4		T11	2		T60	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T53	1		T161	1		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T38	16		T155	13		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	15		T12	1		T44	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	13		T71	2		T46	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	7		T2	17		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T57	9		T32	14		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	8		T56	1		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	13		T4	16		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T10	1		T56	1		T123	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T10	1		T41	16		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T4	4		T10	1		T152	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T170	1		T228	1		T223	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T5	1		T272	1		T269	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16620	1			T3	134		T8	14		T61	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T9	12		T119	2		T176	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T152	11		T153	10		T119	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T62	2		T163	15		T273	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T262	4		T272	13		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T152	10		T119	3		T234	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T71	3		T150	9		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T2	2		T60	35		T39	35
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T53	8		T13	3		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T38	2		T155	9		T47	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T44	1		T38	4		T174	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T46	2		T151	6		T31	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	15		T156	12		T172	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T151	7		T172	7		T157	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T4	8		T48	2		T158	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	15		T172	2		T179	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	11		T157	11		T224	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T41	15		T114	18		T48	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	5		T10	8		T152	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T28	2		T186	11		T196	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T272	7		T230	11		T281	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T282	4		T283	16		T284	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T228	1		T223	10		T163	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T275	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T52	12		T40	1		T237	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T276	8		T277	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T9	1		T119	5		T278	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	4		T152	10		T119	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	9		T9	1		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	3		T153	1		T109	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T152	8		T119	4		T62	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	14		T150	5		T273	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T2	4		T11	2		T60	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T161	1		T71	3		T150	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T38	16		T155	13		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	15		T12	1		T44	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T71	2		T46	5		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	17		T172	1		T236	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	13		T57	9		T32	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	7		T56	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	13		T49	6		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	8		T10	1		T48	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T4	16		T10	1		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	433	1			T4	4		T5	1		T10	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T275	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T237	9		T222	14		T285	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T276	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	1		T119	2		T176	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T152	11		T119	14		T66	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T9	11		T273	7		T51	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T153	10		T262	4		T272	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T152	10		T119	3		T62	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T150	2		T280	1		T221	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T2	2		T60	35		T39	35
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T71	3		T150	7		T154	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T38	2		T155	9		T215	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T44	1		T53	8		T38	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T46	2		T151	6		T28	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	15		T172	6		T236	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T151	7		T31	2		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T261	14		T250	6		T286	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T172	7		T157	4		T26	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	8		T10	11		T48	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T4	15		T41	15		T114	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T4	5		T10	8		T152	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12