Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22322

1

T1

14

T2

6

T3

134

auto[ADC_CTRL_FILTER_COND_OUT]

3550

1

T1

10

T2

45

T4

31

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19686

1

T1

7

T3

134

T4

31

auto[1]

6186

1

T1

17

T2

51

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	263	1			T53	9		T161	1		T162	1
values[0]	16	1			T189	6		T287	8		T206	2
values[1]	577	1			T10	12		T38	18		T40	1
values[2]	2799	1			T1	14		T2	6		T4	16
values[3]	746	1			T5	1		T7	9		T152	35
values[4]	717	1			T2	13		T9	12		T40	1
values[5]	819	1			T36	1		T152	21		T45	8
values[6]	727	1			T7	13		T161	1		T71	6
values[7]	769	1			T4	31		T7	4		T56	1
values[8]	880	1			T2	32		T44	8		T150	25
values[9]	954	1			T1	10		T4	9		T6	15
minimum	16605	1			T3	134		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	622	1			T10	13		T38	18		T40	1
values[1]	2850	1			T1	14		T2	6		T4	16
values[2]	797	1			T5	1		T7	9		T40	1
values[3]	677	1			T2	13		T9	12		T47	8
values[4]	793	1			T7	13		T36	1		T152	21
values[5]	948	1			T4	31		T161	1		T71	6
values[6]	666	1			T2	32		T7	4		T44	8
values[7]	771	1			T1	3		T12	1		T32	14
values[8]	881	1			T1	7		T4	9		T6	15
values[9]	167	1			T10	9		T162	1		T155	22
minimum	16700	1			T3	134		T8	14		T61	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T10	12		T38	3		T71	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	1		T40	1		T151	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T1	1		T2	3		T4	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	2		T56	1		T64	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T71	1		T152	17		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	1		T7	1		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T228	1		T48	1		T288	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T2	1		T9	12		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	1		T36	1		T152	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T120	1		T31	14		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T161	1		T71	4		T152	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T4	16		T119	4		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	1		T44	6		T150	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	16		T56	1		T41	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T32	1		T109	1		T235	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T12	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T4	6		T52	1		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	1		T6	1		T53	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T10	9		T162	1		T190	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T155	10		T264	1		T289	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16530	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T193	1		T242	11		T189	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T38	15		T71	4		T46	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T123	15		T163	13		T192	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T1	13		T2	3		T4	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T64	11		T116	3		T13	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T71	1		T152	18		T154	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	8		T150	8		T109	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T31	4		T229	12		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	12		T47	3		T244	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T7	12		T152	9		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T120	6		T31	11		T269	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T71	2		T152	7		T119	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	15		T119	3		T108	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	3		T44	2		T150	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	16		T41	15		T108	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T32	13		T109	9		T30	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	2		T48	1		T238	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	3		T52	11		T150	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	6		T6	14		T123	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T290	6		T291	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T155	12		T289	12		T254	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T64	1		T45	4		T120	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T193	2		T242	10		T189	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T162	1		T278	1		T214	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T53	9		T161	1		T172	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T189	1		T287	8		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T10	12		T38	3		T71	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T40	1		T151	8		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T1	1		T2	3		T4	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	2		T10	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T152	17		T62	1		T154	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T7	1		T150	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T71	1		T228	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	1		T9	12		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T36	1		T152	12		T45	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T120	1		T244	2		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	1		T161	1		T71	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T119	4		T108	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	1		T150	3		T119	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	16		T56	1		T41	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T44	6		T150	16		T62	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	16		T48	5		T273	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T4	6		T10	9		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T1	2		T6	1		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T214	13		T292	12		T290	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T174	2		T293	10		T180	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T189	5		T206	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T38	15		T71	4		T46	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T123	15		T163	13		T192	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T1	13		T2	3		T4	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T64	11		T13	3		T50	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	18		T154	2		T66	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	8		T150	8		T116	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T71	1		T31	4		T229	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	12		T47	3		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T152	9		T45	2		T223	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T120	6		T244	8		T269	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	12		T71	2		T152	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T119	3		T108	10		T31	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	3		T150	4		T119	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	15		T41	15		T108	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T44	2		T150	9		T62	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	16		T48	1		T273	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	3		T52	11		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	8		T6	14		T155	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	1		T38	16		T71	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	1		T40	1		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T1	14		T2	4		T4	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	1		T56	1		T64	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T71	2		T152	19		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	1		T7	9		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T228	1		T48	1		T288	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	13		T9	1		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T7	13		T36	1		T152	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T120	7		T31	12		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T161	1		T71	3		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T4	16		T119	4		T108	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	4		T44	7		T150	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	17		T56	1		T41	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T32	14		T109	10		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	3		T12	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T4	4		T52	12		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	7		T6	15		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T10	1		T162	1		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T155	13		T264	1		T289	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16626	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T193	3		T242	11		T189	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	11		T38	2		T71	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T151	7		T163	15		T172	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T2	2		T4	8		T60	35
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T9	1		T13	3		T50	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T152	16		T154	12		T59	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T150	7		T114	18		T272	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T28	17		T31	2		T177	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T9	11		T47	3		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T152	11		T45	3		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T31	13		T236	10		T234	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T71	3		T152	10		T119	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T4	15		T119	3		T236	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T44	1		T150	2		T119	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	15		T41	15		T273	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T235	3		T192	13		T247	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T48	2		T28	2		T238	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T4	5		T153	10		T150	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T53	8		T151	2		T156	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T10	8		T190	15		T290	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T155	9		T289	9		T294	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T295	15		T188	11		T296	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T242	10		T287	7		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T162	1		T278	1		T214	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T53	1		T161	1		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T189	6		T287	1		T206	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	1		T38	16		T71	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T40	1		T151	1		T123	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T1	14		T2	4		T4	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	1		T10	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T152	19		T62	1		T154	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T7	9		T150	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T71	2		T228	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	13		T9	1		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T36	1		T152	10		T45	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T120	7		T244	10		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	13		T161	1		T71	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T119	4		T108	11		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	4		T150	5		T119	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	16		T56	1		T41	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T44	7		T150	10		T62	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	17		T48	4		T273	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T4	4		T10	1		T52	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T1	10		T6	15		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T292	13		T175	2		T290	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T53	8		T172	7		T293	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T287	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	11		T38	2		T71	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T151	7		T163	15		T172	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T2	2		T4	8		T60	35
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T9	1		T13	3		T50	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T152	16		T154	12		T176	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T150	7		T114	18		T272	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T28	17		T31	2		T177	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	11		T47	3		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T152	11		T45	3		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T236	10		T250	6		T281	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T71	3		T152	10		T119	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T119	3		T31	13		T236	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T150	2		T119	2		T166	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	15		T41	15		T260	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T44	1		T150	15		T62	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	15		T48	2		T273	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	5		T10	8		T153	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T151	2		T155	9		T156	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12