Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19923

1

T2

51

T3

134

T4

40

auto[ADC_CTRL_FILTER_COND_OUT]

5949

1

T1

24

T4

16

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19905

1

T1

3

T2

45

T3

134

auto[1]

5967

1

T1

21

T2

6

T4

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	238	1			T12	1		T40	1		T172	8
values[0]	43	1			T293	13		T297	30		-	-
values[1]	786	1			T9	12		T71	2		T150	41
values[2]	945	1			T2	32		T4	31		T6	15
values[3]	554	1			T57	9		T40	1		T62	8
values[4]	741	1			T1	3		T44	8		T38	29
values[5]	741	1			T4	16		T5	1		T7	13
values[6]	874	1			T2	13		T7	9		T32	14
values[7]	667	1			T4	9		T7	4		T10	12
values[8]	623	1			T2	6		T10	9		T52	12
values[9]	3055	1			T1	21		T9	2		T10	1
minimum	16605	1			T3	134		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	939	1			T4	31		T9	12		T56	1
values[1]	2818	1			T2	32		T6	15		T11	2
values[2]	580	1			T57	9		T62	8		T154	1
values[3]	702	1			T1	3		T44	8		T38	29
values[4]	716	1			T4	16		T5	1		T53	9
values[5]	992	1			T2	13		T7	26		T32	14
values[6]	526	1			T4	9		T10	12		T56	1
values[7]	717	1			T2	6		T10	9		T52	12
values[8]	921	1			T1	21		T9	2		T10	1
values[9]	73	1			T172	8		T59	9		T230	13
minimum	16888	1			T3	134		T8	14		T61	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	16		T9	12		T71	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T56	1		T152	11		T150	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	16		T6	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1541	1			T11	2		T60	38		T54	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T57	1		T62	3		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T128	1		T264	1		T247	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T38	8		T114	19		T48	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	1		T44	6		T71	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T41	16		T153	11		T119	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	9		T5	1		T53	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T2	1		T7	1		T152	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	2		T32	1		T152	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	6		T10	12		T56	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T161	1		T64	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	3		T10	9		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T176	13		T157	5		T28	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T9	2		T10	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T1	2		T40	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T172	8		T298	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T59	4		T230	8		T299	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16539	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T192	13		T160	1		T293	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	15		T71	1		T150	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T152	7		T150	9		T47	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	16		T6	14		T155	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	950	1			T43	7		T169	27		T243	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T57	8		T62	5		T30	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T247	15		T292	12		T300	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T38	21		T48	1		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	2		T44	2		T71	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T41	15		T119	9		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T4	7		T154	2		T301	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	12		T7	8		T152	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T7	15		T32	13		T152	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T4	3		T71	2		T176	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T64	11		T109	3		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	3		T52	11		T150	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T176	11		T58	3		T173	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T119	3		T108	10		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	19		T120	6		T108	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T298	11		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T59	5		T230	5		T299	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T64	1		T45	4		T116	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T192	17		T293	12		T193	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T12	1		T172	8		T30	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T40	1		T244	1		T234	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T293	1		T297	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	12		T71	1		T150	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T150	16		T47	5		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	16		T4	16		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T56	1		T36	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T57	1		T62	3		T228	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T40	1		T108	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T38	8		T114	19		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	1		T44	6		T71	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T41	16		T153	11		T119	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	9		T5	1		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T2	1		T7	1		T152	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T32	1		T45	6		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	6		T10	12		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	1		T161	1		T152	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	3		T10	9		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T123	1		T278	1		T157	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	2		T10	1		T119	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1666	1			T1	2		T11	2		T60	38
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T30	10		T280	4		T174	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T230	5		T250	5		T302	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T293	12		T297	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T71	1		T150	8		T116	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T150	9		T47	3		T214	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	16		T4	15		T6	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T152	7		T163	13		T192	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T57	8		T62	5		T30	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T178	17		T303	1		T304	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T38	21		T48	1		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T1	2		T44	2		T71	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T41	15		T119	9		T48	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	7		T7	12		T46	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	12		T7	8		T152	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T32	13		T45	2		T109	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T4	3		T176	10		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	3		T152	18		T64	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	3		T52	11		T71	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T123	12		T192	11		T58	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T119	3		T108	10		T30	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1026	1			T1	19		T43	7		T169	27
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	16		T9	1		T71	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T56	1		T152	8		T150	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	17		T6	15		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1284	1			T11	2		T60	3		T54	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T57	9		T62	6		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T128	1		T264	1		T247	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T38	23		T114	1		T48	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	3		T44	7		T71	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T41	16		T153	1		T119	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	8		T5	1		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T2	13		T7	9		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T7	17		T32	14		T152	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T4	4		T10	1		T56	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T161	1		T64	12		T109	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	4		T10	1		T52	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T176	12		T157	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	1		T10	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T1	21		T40	1		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T172	1		T298	12		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T59	8		T230	6		T299	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16674	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T192	18		T160	1		T293	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	15		T9	11		T150	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T152	10		T150	15		T47	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T2	15		T155	9		T273	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1207	1			T60	35		T39	35		T171	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T62	2		T172	2		T224	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T247	10		T260	10		T292	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T38	6		T114	18		T48	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T44	1		T71	9		T46	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T41	15		T153	10		T119	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T4	8		T53	8		T151	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T152	11		T215	21		T235	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T152	16		T45	3		T66	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T4	5		T10	11		T71	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T250	3		T194	4		T259	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	2		T10	8		T150	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T176	12		T157	4		T28	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	1		T119	3		T30	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T156	12		T236	9		T272	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T172	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T59	1		T230	7		T255	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T293	10		T305	4		T301	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T192	12		T306	10		T307	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T12	1		T172	1		T30	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T40	1		T244	1		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T293	13		T297	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	1		T71	2		T150	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T150	10		T47	5		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T2	17		T4	16		T6	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T56	1		T36	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T57	9		T62	6		T228	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	1		T108	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T38	23		T114	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	3		T44	7		T71	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T41	16		T153	1		T119	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	8		T5	1		T7	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T2	13		T7	9		T152	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T32	14		T45	5		T109	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	4		T10	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	4		T161	1		T152	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	4		T10	1		T52	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T123	13		T278	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	1		T10	1		T119	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1393	1			T1	21		T11	2		T60	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T172	7		T30	11		T174	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T234	2		T230	7		T250	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T297	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	11		T150	7		T119	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T150	15		T47	3		T31	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	15		T4	15		T155	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T152	10		T151	6		T163	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T62	2		T172	2		T158	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T260	10		T178	17		T304	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T38	6		T114	18		T48	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T44	1		T71	9		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T41	15		T153	10		T119	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	8		T53	8		T46	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T152	11		T235	3		T26	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T45	3		T159	2		T222	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	5		T10	11		T215	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	16		T66	10		T250	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	2		T10	8		T71	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T157	4		T58	3		T167	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T119	3		T262	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1299	1			T60	35		T39	35		T171	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12