Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22479

1

T1

10

T2

32

T3

134

auto[ADC_CTRL_FILTER_COND_OUT]

3393

1

T1

14

T2

19

T4

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19667

1

T1

7

T3

134

T4

16

auto[1]

6205

1

T1

17

T2

51

T4

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T308	12		T240	8		T20	1
values[0]	49	1			T59	9		T249	25		T306	7
values[1]	743	1			T4	47		T9	2		T152	21
values[2]	977	1			T4	9		T9	12		T10	1
values[3]	712	1			T1	17		T2	45		T56	1
values[4]	670	1			T10	12		T57	9		T71	14
values[5]	2750	1			T7	9		T10	9		T11	2
values[6]	530	1			T7	13		T44	8		T40	1
values[7]	894	1			T2	6		T52	12		T153	11
values[8]	558	1			T5	1		T6	15		T36	1
values[9]	1361	1			T1	7		T7	4		T12	1
minimum	16605	1			T3	134		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1130	1			T4	47		T9	2		T152	21
values[1]	713	1			T1	3		T4	9		T9	12
values[2]	837	1			T1	14		T2	45		T56	1
values[3]	2754	1			T10	12		T11	2		T60	38
values[4]	598	1			T7	22		T10	9		T56	1
values[5]	632	1			T44	8		T52	12		T40	1
values[6]	783	1			T2	6		T5	1		T36	1
values[7]	730	1			T6	15		T150	25		T162	1
values[8]	942	1			T1	7		T7	4		T12	1
values[9]	146	1			T53	9		T108	1		T172	8
minimum	16607	1			T3	134		T8	14		T61	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T4	16		T152	12		T150	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T4	9		T9	2		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T4	6		T41	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	12		T10	1		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T2	16		T161	2		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	1		T2	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1586	1			T10	12		T11	2		T60	38
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T151	8		T48	1		T66	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	2		T10	9		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T71	1		T152	11		T28	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T153	11		T119	15		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T44	6		T52	1		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T38	8		T71	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	3		T36	1		T64	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	1		T162	1		T151	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T150	16		T123	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T1	1		T7	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T32	1		T40	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T53	9		T172	8		T157	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T108	1		T261	15		T286	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16489	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T160	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T4	15		T152	9		T150	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	7		T120	6		T48	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	2		T4	3		T41	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T108	10		T223	9		T273	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	16		T31	11		T229	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	13		T2	12		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T57	8		T43	7		T71	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T230	5		T267	10		T309	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	20		T152	18		T150	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T71	1		T152	7		T221	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T119	9		T109	9		T245	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T44	2		T52	11		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T38	21		T71	2		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	3		T64	11		T119	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	14		T155	12		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T150	9		T123	15		T310	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	6		T7	3		T154	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T32	13		T176	11		T13	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T308	11		T311	1		T240	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T303	1		T282	4		T312	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T308	1		T240	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T20	1		T313	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T59	4		T296	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T249	11		T306	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T4	16		T152	12		T150	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	9		T9	2		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T4	6		T41	16		T62	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T9	12		T10	1		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	1		T2	16		T161	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T2	1		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T10	12		T57	1		T71	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T152	11		T151	8		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T7	1		T10	9		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T71	1		T288	1		T272	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	1		T152	17		T119	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T44	6		T40	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T153	11		T45	6		T236	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T2	3		T52	1		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	1		T6	1		T38	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T36	1		T114	19		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	469	1			T1	1		T7	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T32	1		T40	1		T150	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T308	11		T240	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T59	5		T296	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T249	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	15		T152	9		T150	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T4	7		T120	6		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	3		T41	15		T62	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T223	9		T247	15		T173	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	2		T2	16		T229	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	13		T2	12		T46	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T57	8		T71	4		T109	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T152	7		T66	14		T230	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T7	8		T43	7		T169	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T71	1		T267	10		T221	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	12		T152	18		T119	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T44	2		T48	1		T30	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T45	2		T292	12		T276	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T2	3		T52	11		T64	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	14		T38	21		T71	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T123	15		T176	10		T310	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T1	6		T7	3		T154	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T32	13		T150	9		T176	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T4	16		T152	10		T150	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T4	8		T9	1		T120	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	3		T4	4		T41	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	1		T10	1		T108	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T2	17		T161	2		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	14		T2	13		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T10	1		T11	2		T60	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T151	1		T48	1		T66	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	22		T10	1		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T71	2		T152	8		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T153	1		T119	10		T109	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T44	7		T52	12		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	1		T38	23		T71	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	4		T36	1		T64	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T6	15		T162	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T150	10		T123	16		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T1	7		T7	4		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T32	14		T40	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T53	1		T172	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T108	1		T261	1		T286	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16606	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T160	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T4	15		T152	11		T150	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	8		T9	1		T48	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	5		T41	15		T62	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	11		T172	2		T28	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	15		T172	6		T31	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T46	2		T234	2		T260	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T10	11		T60	35		T39	35
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T151	7		T230	7		T309	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	8		T152	16		T150	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T152	10		T28	17		T272	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T153	10		T119	14		T236	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T44	1		T224	9		T158	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T38	6		T71	3		T45	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	2		T114	18		T119	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T151	6		T155	9		T51	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T150	15		T230	12		T174	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T154	12		T215	21		T47	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T176	12		T235	3		T13	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T53	8		T172	7		T157	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T261	14		T286	20		T282	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T308	12		T240	6		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T20	1		T313	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T59	8		T296	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T249	15		T306	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T4	16		T152	10		T150	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	8		T9	1		T120	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T4	4		T41	16		T62	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	1		T10	1		T223	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	3		T2	17		T161	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	14		T2	13		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	1		T57	9		T71	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T152	8		T151	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T7	9		T10	1		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T71	2		T288	1		T272	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	13		T152	19		T119	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T44	7		T40	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T153	1		T45	5		T236	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T2	4		T52	12		T64	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	1		T6	15		T38	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T36	1		T114	1		T123	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T1	7		T7	4		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T32	14		T40	1		T150	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T240	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T313	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T59	1		T296	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T249	10		T306	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T4	15		T152	11		T150	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T4	8		T9	1		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	5		T41	15		T62	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T9	11		T172	2		T28	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	15		T151	2		T262	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T46	2		T273	7		T260	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T10	11		T71	9		T163	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T152	10		T151	7		T234	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T10	8		T60	35		T39	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T272	7		T190	11		T221	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T152	16		T119	14		T236	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T44	1		T48	2		T28	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T153	10		T45	3		T236	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	2		T119	3		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T38	6		T71	3		T151	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T114	18		T176	11		T230	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T53	8		T154	12		T215	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T150	15		T176	12		T235	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12