Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25872

1

T1

24

T2

51

T3

134

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19948

1

T2

51

T3

134

T4

40

auto[ADC_CTRL_FILTER_COND_OUT]

5924

1

T1

24

T4

16

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19918

1

T1

3

T2

45

T3

134

auto[1]

5954

1

T1

21

T2

6

T4

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21863

1

T1

3

T2

20

T3

134

auto[1]

4009

1

T1

21

T2

31

T4

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T316	1		T242	22		-	-
values[0]	62	1			T293	13		T305	7		T301	11
values[1]	807	1			T9	12		T71	2		T152	18
values[2]	886	1			T2	32		T4	31		T6	15
values[3]	611	1			T62	8		T108	1		T172	3
values[4]	734	1			T1	3		T44	8		T57	9
values[5]	750	1			T4	16		T5	1		T7	13
values[6]	816	1			T2	13		T7	9		T32	14
values[7]	622	1			T4	9		T7	4		T10	12
values[8]	725	1			T2	6		T10	9		T52	12
values[9]	3231	1			T1	21		T9	2		T10	1
minimum	16605	1			T3	134		T8	14		T61	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1166	1			T4	31		T9	12		T56	1
values[1]	2818	1			T2	32		T6	15		T11	2
values[2]	631	1			T57	9		T162	1		T62	8
values[3]	729	1			T1	3		T44	8		T38	29
values[4]	691	1			T4	16		T5	1		T7	13
values[5]	929	1			T2	13		T7	13		T32	14
values[6]	597	1			T10	12		T56	1		T161	1
values[7]	717	1			T2	6		T4	9		T10	9
values[8]	798	1			T1	21		T9	2		T10	1
values[9]	177	1			T108	11		T244	1		T272	8
minimum	16619	1			T3	134		T8	14		T61	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

4299

1

T2

17

T4

28

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T4	16		T9	12		T71	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T56	1		T152	11		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	16		T6	1		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1564	1			T11	2		T60	38		T54	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T57	1		T162	1		T62	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T128	1		T264	1		T247	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T38	8		T114	19		T48	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	1		T44	6		T71	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T53	9		T41	16		T153	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	9		T5	1		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	1		T7	1		T215	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	1		T32	1		T152	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	12		T56	1		T71	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T161	1		T64	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	3		T4	6		T10	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T176	13		T157	5		T28	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	2		T10	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	2		T40	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T108	1		T174	10		T298	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T244	1		T272	8		T59	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T160	1		T293	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	15		T71	1		T150	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T152	7		T150	9		T47	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T2	16		T6	14		T273	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	958	1			T43	7		T169	27		T243	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T57	8		T62	5		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T247	15		T292	12		T303	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T38	21		T48	1		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	2		T44	2		T71	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T41	15		T119	9		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T4	7		T7	12		T154	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	12		T7	8		T267	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T7	3		T32	13		T152	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T71	2		T152	9		T176	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T64	11		T109	3		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	3		T4	3		T52	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T176	11		T58	3		T173	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T119	3		T30	10		T262	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	19		T120	6		T108	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T108	10		T174	7		T298	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T59	5		T299	3		T175	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T293	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T242	14		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T316	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T305	5		T301	6		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T293	1		T297	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	12		T71	1		T150	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T152	11		T150	16		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T2	16		T4	16		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T56	1		T36	1		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T62	3		T172	3		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T108	1		T264	1		T260	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T57	1		T38	8		T41	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	1		T44	6		T71	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T53	9		T153	11		T119	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T4	9		T5	1		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	1		T7	1		T278	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T32	1		T45	6		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	6		T10	12		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	1		T161	1		T152	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	3		T10	9		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T108	1		T123	1		T278	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T9	2		T10	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1722	1			T1	2		T11	2		T60	38
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16488	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T242	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T305	2		T301	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T293	12		T297	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T71	1		T150	8		T116	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T152	7		T150	9		T214	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	16		T4	15		T6	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T47	3		T163	13		T31	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T62	5		T30	1		T158	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T178	17		T303	1		T259	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T57	8		T38	21		T41	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T1	2		T44	2		T71	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T119	9		T48	1		T174	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	7		T7	12		T46	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	12		T7	8		T238	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T32	13		T45	2		T109	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	3		T152	9		T176	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	3		T152	18		T64	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T2	3		T52	11		T71	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T108	20		T123	12		T192	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T119	3		T108	10		T30	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1032	1			T1	19		T43	7		T169	27
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T64	1		T45	4		T120	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T4	16		T9	1		T71	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	405	1			T56	1		T152	8		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	17		T6	15		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1293	1			T11	2		T60	3		T54	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T57	9		T162	1		T62	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T128	1		T264	1		T247	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T38	23		T114	1		T48	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	3		T44	7		T71	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T53	1		T41	16		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	8		T5	1		T7	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	13		T7	9		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T7	4		T32	14		T152	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T10	1		T56	1		T71	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T161	1		T64	12		T109	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	4		T4	4		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T176	12		T157	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	1		T10	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	21		T40	1		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T108	11		T174	8		T298	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T244	1		T272	1		T59	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T160	1		T293	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	15		T9	11		T150	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T152	10		T150	15		T47	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	15		T273	7		T190	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1229	1			T60	35		T39	35		T171	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T62	2		T155	9		T172	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T247	10		T260	10		T292	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T38	6		T114	18		T48	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T44	1		T71	9		T46	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T53	8		T41	15		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T4	8		T151	7		T154	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T215	21		T235	3		T26	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T152	16		T45	3		T66	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T10	11		T71	3		T152	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T250	3		T194	4		T259	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	2		T4	5		T10	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T176	12		T157	4		T28	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	1		T119	3		T172	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T156	12		T236	9		T234	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T174	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T272	7		T59	1		T175	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T242	9		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T316	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T305	3		T301	6		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T293	13		T297	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	1		T71	2		T150	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T152	8		T150	10		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T2	17		T4	16		T6	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T56	1		T36	1		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T62	6		T172	1		T30	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T108	1		T264	1		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T57	9		T38	23		T41	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	3		T44	7		T71	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T53	1		T153	1		T119	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	8		T5	1		T7	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	13		T7	9		T278	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T32	14		T45	5		T109	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	4		T10	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	4		T161	1		T152	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	4		T10	1		T52	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T108	21		T123	13		T278	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T9	1		T10	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1409	1			T1	21		T11	2		T60	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T3	134		T8	14		T61	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T242	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T305	4		T301	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T297	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	11		T150	7		T119	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T152	10		T150	15		T192	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	15		T4	15		T155	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T151	6		T47	3		T163	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T62	2		T172	2		T158	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T260	10		T178	17		T259	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T38	6		T41	15		T114	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T44	1		T71	9		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T53	8		T153	10		T119	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	8		T46	2		T151	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T235	3		T26	13		T28	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T45	3		T222	14		T180	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	5		T10	11		T152	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T152	16		T66	10		T250	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	2		T10	8		T71	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T157	4		T58	3		T167	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	1		T119	3		T172	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1345	1			T60	35		T39	35		T171	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21573

1

T1

24

T2

34

T3

134

auto[1]

auto[0]

4299

1

T2

17

T4

28

T9

12