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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.78 99.07 96.67 100.00 100.00 98.83 98.33 91.56


Total test records in report: 919
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T796 /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1166357003 Jun 30 06:31:03 PM PDT 24 Jun 30 06:53:28 PM PDT 24 596782844476 ps
T797 /workspace/coverage/default/24.adc_ctrl_alert_test.3736317995 Jun 30 06:28:57 PM PDT 24 Jun 30 06:29:00 PM PDT 24 342202429 ps
T220 /workspace/coverage/default/46.adc_ctrl_filters_both.2216451984 Jun 30 06:31:29 PM PDT 24 Jun 30 06:33:52 PM PDT 24 467799005720 ps
T798 /workspace/coverage/default/11.adc_ctrl_clock_gating.616615104 Jun 30 06:28:02 PM PDT 24 Jun 30 06:35:14 PM PDT 24 366027792996 ps
T799 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.683178478 Jun 30 06:19:51 PM PDT 24 Jun 30 06:19:55 PM PDT 24 448644795 ps
T130 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1465591826 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:44 PM PDT 24 533466689 ps
T76 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.634229086 Jun 30 06:19:45 PM PDT 24 Jun 30 06:19:50 PM PDT 24 518229574 ps
T67 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.299982436 Jun 30 06:19:36 PM PDT 24 Jun 30 06:20:58 PM PDT 24 34380552078 ps
T800 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2061956579 Jun 30 06:19:39 PM PDT 24 Jun 30 06:19:45 PM PDT 24 286242283 ps
T801 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1187943768 Jun 30 06:19:53 PM PDT 24 Jun 30 06:19:56 PM PDT 24 320606221 ps
T802 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.519725632 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:55 PM PDT 24 391246837 ps
T144 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2926059867 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:49 PM PDT 24 1120441463 ps
T145 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2987384647 Jun 30 06:19:37 PM PDT 24 Jun 30 06:19:42 PM PDT 24 1126085034 ps
T803 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2442756412 Jun 30 06:19:54 PM PDT 24 Jun 30 06:19:57 PM PDT 24 398991397 ps
T77 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3734826108 Jun 30 06:19:35 PM PDT 24 Jun 30 06:19:38 PM PDT 24 349844367 ps
T139 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.579517239 Jun 30 06:19:35 PM PDT 24 Jun 30 06:19:39 PM PDT 24 493016151 ps
T804 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4251036343 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:55 PM PDT 24 480658490 ps
T70 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4252336928 Jun 30 06:19:50 PM PDT 24 Jun 30 06:19:56 PM PDT 24 1956783749 ps
T146 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.685402748 Jun 30 06:19:34 PM PDT 24 Jun 30 06:19:38 PM PDT 24 1162356312 ps
T805 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2948839529 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:43 PM PDT 24 410674874 ps
T147 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4234596615 Jun 30 06:19:33 PM PDT 24 Jun 30 06:19:37 PM PDT 24 788562590 ps
T84 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.542661003 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:44 PM PDT 24 378914743 ps
T140 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.886502597 Jun 30 06:19:45 PM PDT 24 Jun 30 06:19:48 PM PDT 24 603628392 ps
T72 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2686667415 Jun 30 06:19:47 PM PDT 24 Jun 30 06:20:10 PM PDT 24 8823572555 ps
T131 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2916846919 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:43 PM PDT 24 412530407 ps
T141 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1532177771 Jun 30 06:19:37 PM PDT 24 Jun 30 06:19:47 PM PDT 24 2459580968 ps
T806 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3936084207 Jun 30 06:19:50 PM PDT 24 Jun 30 06:19:53 PM PDT 24 507221933 ps
T807 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3984364158 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:41 PM PDT 24 445531657 ps
T81 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2268467340 Jun 30 06:19:50 PM PDT 24 Jun 30 06:19:55 PM PDT 24 524068509 ps
T87 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.970828220 Jun 30 06:19:39 PM PDT 24 Jun 30 06:19:45 PM PDT 24 569887885 ps
T808 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2707185456 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:40 PM PDT 24 376337409 ps
T132 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2544216542 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:44 PM PDT 24 494115066 ps
T809 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2867061688 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:55 PM PDT 24 366632185 ps
T68 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3567655907 Jun 30 06:19:35 PM PDT 24 Jun 30 06:20:19 PM PDT 24 44977022031 ps
T810 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1889537221 Jun 30 06:19:39 PM PDT 24 Jun 30 06:19:44 PM PDT 24 415845403 ps
T811 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.259156153 Jun 30 06:19:53 PM PDT 24 Jun 30 06:19:56 PM PDT 24 404650746 ps
T812 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1691453444 Jun 30 06:19:57 PM PDT 24 Jun 30 06:20:00 PM PDT 24 399978512 ps
T69 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2835357483 Jun 30 06:19:54 PM PDT 24 Jun 30 06:19:58 PM PDT 24 3180844914 ps
T133 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4104839630 Jun 30 06:19:50 PM PDT 24 Jun 30 06:19:52 PM PDT 24 367210498 ps
T103 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.436046574 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:44 PM PDT 24 669112350 ps
T813 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1904227572 Jun 30 06:19:50 PM PDT 24 Jun 30 06:19:52 PM PDT 24 364627373 ps
T104 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2866119477 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:43 PM PDT 24 431487423 ps
T814 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2788521269 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:55 PM PDT 24 383812772 ps
T815 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3136580722 Jun 30 06:19:55 PM PDT 24 Jun 30 06:19:58 PM PDT 24 403399594 ps
T816 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1162891965 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:55 PM PDT 24 308576256 ps
T105 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4064754533 Jun 30 06:19:49 PM PDT 24 Jun 30 06:19:52 PM PDT 24 809893555 ps
T73 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2985288545 Jun 30 06:19:42 PM PDT 24 Jun 30 06:20:06 PM PDT 24 8567134204 ps
T817 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.876482144 Jun 30 06:19:38 PM PDT 24 Jun 30 06:20:47 PM PDT 24 53019981079 ps
T818 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4050555088 Jun 30 06:19:34 PM PDT 24 Jun 30 06:20:11 PM PDT 24 54121869938 ps
T819 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.593840354 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:40 PM PDT 24 317873146 ps
T74 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3584562180 Jun 30 06:19:44 PM PDT 24 Jun 30 06:20:07 PM PDT 24 8049478735 ps
T820 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4147716644 Jun 30 06:19:55 PM PDT 24 Jun 30 06:19:57 PM PDT 24 370381014 ps
T821 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.871828140 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:55 PM PDT 24 517318184 ps
T822 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1592028589 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:44 PM PDT 24 496018558 ps
T142 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3345741910 Jun 30 06:19:51 PM PDT 24 Jun 30 06:19:57 PM PDT 24 4412976272 ps
T82 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3313573263 Jun 30 06:19:51 PM PDT 24 Jun 30 06:20:00 PM PDT 24 4221626908 ps
T823 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.282048310 Jun 30 06:19:45 PM PDT 24 Jun 30 06:19:49 PM PDT 24 340338579 ps
T143 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2630575330 Jun 30 06:19:49 PM PDT 24 Jun 30 06:19:54 PM PDT 24 4888831894 ps
T824 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3243619020 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:45 PM PDT 24 657980784 ps
T83 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1044224689 Jun 30 06:19:50 PM PDT 24 Jun 30 06:19:56 PM PDT 24 435679819 ps
T825 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.904492845 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:55 PM PDT 24 475254410 ps
T826 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2228925802 Jun 30 06:19:53 PM PDT 24 Jun 30 06:19:56 PM PDT 24 425938329 ps
T827 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2755088910 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:44 PM PDT 24 281298193 ps
T134 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3591671503 Jun 30 06:19:34 PM PDT 24 Jun 30 06:19:38 PM PDT 24 1321162279 ps
T86 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1682036922 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:42 PM PDT 24 374638753 ps
T828 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1470978093 Jun 30 06:19:50 PM PDT 24 Jun 30 06:19:53 PM PDT 24 605018837 ps
T829 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.182845322 Jun 30 06:19:54 PM PDT 24 Jun 30 06:19:58 PM PDT 24 486157620 ps
T350 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.744520474 Jun 30 06:19:54 PM PDT 24 Jun 30 06:20:07 PM PDT 24 4350372666 ps
T830 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2386653033 Jun 30 06:19:41 PM PDT 24 Jun 30 06:19:50 PM PDT 24 1859230801 ps
T347 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4032706043 Jun 30 06:19:35 PM PDT 24 Jun 30 06:19:43 PM PDT 24 10039661999 ps
T831 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1917540463 Jun 30 06:19:35 PM PDT 24 Jun 30 06:19:39 PM PDT 24 611105018 ps
T832 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3106647272 Jun 30 06:19:43 PM PDT 24 Jun 30 06:19:48 PM PDT 24 489376624 ps
T348 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1894647112 Jun 30 06:19:48 PM PDT 24 Jun 30 06:19:59 PM PDT 24 4152945185 ps
T833 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3430002057 Jun 30 06:19:47 PM PDT 24 Jun 30 06:19:53 PM PDT 24 2308955521 ps
T834 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.613642259 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:47 PM PDT 24 9027890145 ps
T835 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3954689527 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:42 PM PDT 24 675809630 ps
T836 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.948638387 Jun 30 06:19:48 PM PDT 24 Jun 30 06:19:50 PM PDT 24 428520195 ps
T837 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2282076864 Jun 30 06:19:37 PM PDT 24 Jun 30 06:19:43 PM PDT 24 488364657 ps
T838 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.176126880 Jun 30 06:19:51 PM PDT 24 Jun 30 06:19:53 PM PDT 24 440390768 ps
T839 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.938255553 Jun 30 06:19:43 PM PDT 24 Jun 30 06:19:48 PM PDT 24 2751729645 ps
T88 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2537252037 Jun 30 06:19:41 PM PDT 24 Jun 30 06:19:49 PM PDT 24 4515568785 ps
T840 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3077613813 Jun 30 06:19:51 PM PDT 24 Jun 30 06:19:54 PM PDT 24 488440099 ps
T841 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1330203683 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:51 PM PDT 24 8222204012 ps
T842 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1466329622 Jun 30 06:19:41 PM PDT 24 Jun 30 06:19:48 PM PDT 24 435253466 ps
T843 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2627663654 Jun 30 06:19:50 PM PDT 24 Jun 30 06:20:03 PM PDT 24 4632101673 ps
T844 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2910699465 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:43 PM PDT 24 2261625255 ps
T845 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.254473104 Jun 30 06:19:42 PM PDT 24 Jun 30 06:19:49 PM PDT 24 595730876 ps
T351 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.999223252 Jun 30 06:19:44 PM PDT 24 Jun 30 06:19:58 PM PDT 24 4452623235 ps
T846 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3757925078 Jun 30 06:19:53 PM PDT 24 Jun 30 06:19:56 PM PDT 24 461574222 ps
T847 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3549580119 Jun 30 06:19:57 PM PDT 24 Jun 30 06:20:00 PM PDT 24 402023126 ps
T848 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.140916780 Jun 30 06:19:48 PM PDT 24 Jun 30 06:19:56 PM PDT 24 4520551968 ps
T849 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2895124740 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:47 PM PDT 24 1916098277 ps
T850 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3010940102 Jun 30 06:19:41 PM PDT 24 Jun 30 06:19:49 PM PDT 24 4943514989 ps
T851 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2495313937 Jun 30 06:19:43 PM PDT 24 Jun 30 06:19:48 PM PDT 24 376340975 ps
T852 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2344052360 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:44 PM PDT 24 526334400 ps
T853 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.351242470 Jun 30 06:19:51 PM PDT 24 Jun 30 06:19:54 PM PDT 24 442925883 ps
T135 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.9482267 Jun 30 06:19:32 PM PDT 24 Jun 30 06:19:34 PM PDT 24 466615905 ps
T854 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.917794180 Jun 30 06:19:49 PM PDT 24 Jun 30 06:19:51 PM PDT 24 381192919 ps
T855 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3184411781 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:41 PM PDT 24 418585448 ps
T856 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1126760563 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:43 PM PDT 24 476426983 ps
T857 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.48484988 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:43 PM PDT 24 1172570647 ps
T858 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2764420726 Jun 30 06:19:41 PM PDT 24 Jun 30 06:19:55 PM PDT 24 4826584585 ps
T859 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3912083416 Jun 30 06:19:45 PM PDT 24 Jun 30 06:19:48 PM PDT 24 374559106 ps
T860 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3045876305 Jun 30 06:19:57 PM PDT 24 Jun 30 06:20:00 PM PDT 24 492618477 ps
T861 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2056107188 Jun 30 06:19:42 PM PDT 24 Jun 30 06:19:47 PM PDT 24 554696164 ps
T862 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.640780437 Jun 30 06:19:41 PM PDT 24 Jun 30 06:19:47 PM PDT 24 749921176 ps
T863 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3756602889 Jun 30 06:19:37 PM PDT 24 Jun 30 06:19:43 PM PDT 24 402813377 ps
T864 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1364147542 Jun 30 06:19:50 PM PDT 24 Jun 30 06:19:54 PM PDT 24 461846787 ps
T865 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3170209139 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:40 PM PDT 24 471934863 ps
T866 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2248667122 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:55 PM PDT 24 357890536 ps
T867 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1607902421 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:55 PM PDT 24 8214957453 ps
T89 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2345674446 Jun 30 06:19:40 PM PDT 24 Jun 30 06:19:50 PM PDT 24 8417847123 ps
T868 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2231935839 Jun 30 06:19:47 PM PDT 24 Jun 30 06:19:50 PM PDT 24 2662675338 ps
T869 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.492184529 Jun 30 06:19:43 PM PDT 24 Jun 30 06:19:48 PM PDT 24 601406205 ps
T870 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1300704085 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:56 PM PDT 24 566182472 ps
T871 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3275642520 Jun 30 06:19:36 PM PDT 24 Jun 30 06:20:08 PM PDT 24 26058322986 ps
T872 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2828411629 Jun 30 06:19:33 PM PDT 24 Jun 30 06:19:41 PM PDT 24 4394988785 ps
T873 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3018947347 Jun 30 06:19:49 PM PDT 24 Jun 30 06:19:52 PM PDT 24 655369825 ps
T874 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3107255210 Jun 30 06:19:45 PM PDT 24 Jun 30 06:19:49 PM PDT 24 609193792 ps
T875 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2911090307 Jun 30 06:19:50 PM PDT 24 Jun 30 06:20:01 PM PDT 24 3162541426 ps
T876 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3549404598 Jun 30 06:19:42 PM PDT 24 Jun 30 06:19:48 PM PDT 24 4725352863 ps
T136 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2122952561 Jun 30 06:19:51 PM PDT 24 Jun 30 06:19:54 PM PDT 24 412340607 ps
T877 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1198530351 Jun 30 06:19:35 PM PDT 24 Jun 30 06:19:42 PM PDT 24 3606258428 ps
T878 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2127176054 Jun 30 06:19:41 PM PDT 24 Jun 30 06:19:45 PM PDT 24 587162304 ps
T879 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2565434353 Jun 30 06:19:35 PM PDT 24 Jun 30 06:19:40 PM PDT 24 630815580 ps
T880 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2431857769 Jun 30 06:19:42 PM PDT 24 Jun 30 06:19:47 PM PDT 24 708901535 ps
T881 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3747514814 Jun 30 06:19:49 PM PDT 24 Jun 30 06:19:51 PM PDT 24 307980360 ps
T882 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.66820584 Jun 30 06:19:51 PM PDT 24 Jun 30 06:19:54 PM PDT 24 364456097 ps
T883 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1462655390 Jun 30 06:19:48 PM PDT 24 Jun 30 06:19:51 PM PDT 24 2373068424 ps
T884 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3390677287 Jun 30 06:19:42 PM PDT 24 Jun 30 06:19:47 PM PDT 24 545701469 ps
T885 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3277095474 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:56 PM PDT 24 419243889 ps
T886 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2050623105 Jun 30 06:19:37 PM PDT 24 Jun 30 06:19:47 PM PDT 24 1393245469 ps
T887 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3103476734 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:41 PM PDT 24 406041350 ps
T888 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.4131049019 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:55 PM PDT 24 296679592 ps
T889 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2488131259 Jun 30 06:19:50 PM PDT 24 Jun 30 06:19:52 PM PDT 24 410414898 ps
T90 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1115941794 Jun 30 06:19:49 PM PDT 24 Jun 30 06:19:56 PM PDT 24 8633966329 ps
T890 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3414347153 Jun 30 06:19:43 PM PDT 24 Jun 30 06:19:47 PM PDT 24 508779182 ps
T891 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3664009515 Jun 30 06:19:56 PM PDT 24 Jun 30 06:19:59 PM PDT 24 407245243 ps
T892 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4233998333 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:42 PM PDT 24 2087878027 ps
T893 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1062765023 Jun 30 06:19:43 PM PDT 24 Jun 30 06:19:53 PM PDT 24 4277660886 ps
T894 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2311001207 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:42 PM PDT 24 2556345711 ps
T349 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1777284956 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:50 PM PDT 24 4133026471 ps
T895 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3385310785 Jun 30 06:19:44 PM PDT 24 Jun 30 06:19:58 PM PDT 24 4244060388 ps
T896 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3655676185 Jun 30 06:19:43 PM PDT 24 Jun 30 06:19:46 PM PDT 24 564596811 ps
T137 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4150378092 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:55 PM PDT 24 423251713 ps
T897 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.76025916 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:40 PM PDT 24 978753881 ps
T898 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.998995101 Jun 30 06:19:51 PM PDT 24 Jun 30 06:19:55 PM PDT 24 531796466 ps
T138 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4160693976 Jun 30 06:19:51 PM PDT 24 Jun 30 06:19:54 PM PDT 24 328216669 ps
T899 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.467040722 Jun 30 06:19:46 PM PDT 24 Jun 30 06:19:49 PM PDT 24 349923213 ps
T900 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1164722502 Jun 30 06:19:58 PM PDT 24 Jun 30 06:20:01 PM PDT 24 515118731 ps
T901 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1495624808 Jun 30 06:19:50 PM PDT 24 Jun 30 06:19:55 PM PDT 24 590894625 ps
T902 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3837819695 Jun 30 06:19:42 PM PDT 24 Jun 30 06:19:46 PM PDT 24 478965147 ps
T903 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.126175979 Jun 30 06:19:44 PM PDT 24 Jun 30 06:19:48 PM PDT 24 569424636 ps
T904 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.789821680 Jun 30 06:19:51 PM PDT 24 Jun 30 06:19:54 PM PDT 24 434080192 ps
T905 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3575761652 Jun 30 06:19:42 PM PDT 24 Jun 30 06:19:46 PM PDT 24 481935201 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1538510471 Jun 30 06:19:33 PM PDT 24 Jun 30 06:19:41 PM PDT 24 1854671422 ps
T907 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.189760019 Jun 30 06:19:44 PM PDT 24 Jun 30 06:20:00 PM PDT 24 4015367070 ps
T908 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3393584304 Jun 30 06:19:40 PM PDT 24 Jun 30 06:19:46 PM PDT 24 428407794 ps
T909 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4194123578 Jun 30 06:19:43 PM PDT 24 Jun 30 06:19:49 PM PDT 24 579989450 ps
T910 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1734164348 Jun 30 06:19:56 PM PDT 24 Jun 30 06:19:58 PM PDT 24 410044462 ps
T911 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.85384776 Jun 30 06:19:46 PM PDT 24 Jun 30 06:19:49 PM PDT 24 533908566 ps
T912 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2513065918 Jun 30 06:19:33 PM PDT 24 Jun 30 06:19:38 PM PDT 24 1326211726 ps
T913 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3991242182 Jun 30 06:19:49 PM PDT 24 Jun 30 06:19:52 PM PDT 24 487944706 ps
T914 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.312608466 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:55 PM PDT 24 407533517 ps
T915 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1251818658 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:41 PM PDT 24 481713103 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2439118126 Jun 30 06:19:39 PM PDT 24 Jun 30 06:19:44 PM PDT 24 404271738 ps
T917 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1293959282 Jun 30 06:19:52 PM PDT 24 Jun 30 06:19:56 PM PDT 24 667600811 ps
T918 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1894582604 Jun 30 06:19:39 PM PDT 24 Jun 30 06:19:44 PM PDT 24 505182151 ps
T919 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3349707729 Jun 30 06:20:00 PM PDT 24 Jun 30 06:20:01 PM PDT 24 302235593 ps

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.524406297
Short name T4
Test name
Test status
Simulation time 573296102226 ps
CPU time 233.28 seconds
Started Jun 30 06:27:26 PM PDT 24
Finished Jun 30 06:31:21 PM PDT 24
Peak memory 201872 kb
Host smart-a6925e8a-8c4e-441d-b6ae-34457e996158
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524406297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.524406297
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.4268309158
Short name T63
Test name
Test status
Simulation time 122932795561 ps
CPU time 602.61 seconds
Started Jun 30 06:28:56 PM PDT 24
Finished Jun 30 06:39:00 PM PDT 24
Peak memory 202276 kb
Host smart-d6fb6466-fdfe-45f2-84c9-cd676b55d862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268309158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.4268309158
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2994897594
Short name T13
Test name
Test status
Simulation time 56503055929 ps
CPU time 110.15 seconds
Started Jun 30 06:27:14 PM PDT 24
Finished Jun 30 06:29:07 PM PDT 24
Peak memory 210812 kb
Host smart-3f036552-e511-47ef-8446-7a794d1339b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994897594 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2994897594
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1173239002
Short name T2
Test name
Test status
Simulation time 535263114577 ps
CPU time 1298.91 seconds
Started Jun 30 06:31:05 PM PDT 24
Finished Jun 30 06:52:45 PM PDT 24
Peak memory 201892 kb
Host smart-59f41e39-83c1-4d99-bb5c-1a91d066041f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173239002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1173239002
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1229943745
Short name T119
Test name
Test status
Simulation time 551375204719 ps
CPU time 71.52 seconds
Started Jun 30 06:29:08 PM PDT 24
Finished Jun 30 06:30:20 PM PDT 24
Peak memory 201836 kb
Host smart-0a1e0c25-7d2e-4fde-9826-45c156c89726
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229943745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1229943745
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4050145987
Short name T71
Test name
Test status
Simulation time 528388577291 ps
CPU time 179.15 seconds
Started Jun 30 06:29:40 PM PDT 24
Finished Jun 30 06:32:40 PM PDT 24
Peak memory 201868 kb
Host smart-5c21f908-c0eb-4b18-942d-efec7510300d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050145987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4050145987
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2929281778
Short name T64
Test name
Test status
Simulation time 198978894710 ps
CPU time 421.84 seconds
Started Jun 30 06:30:54 PM PDT 24
Finished Jun 30 06:37:57 PM PDT 24
Peak memory 201872 kb
Host smart-14968a06-8925-4fb5-bc61-b8ad28bc1d16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929281778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2929281778
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.412407051
Short name T230
Test name
Test status
Simulation time 505367412521 ps
CPU time 309.2 seconds
Started Jun 30 06:29:08 PM PDT 24
Finished Jun 30 06:34:18 PM PDT 24
Peak memory 202036 kb
Host smart-34a60951-0605-4508-8d78-f474898a13b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412407051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.412407051
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.916725016
Short name T47
Test name
Test status
Simulation time 111563949874 ps
CPU time 86.73 seconds
Started Jun 30 06:28:11 PM PDT 24
Finished Jun 30 06:29:42 PM PDT 24
Peak memory 210556 kb
Host smart-a8e1b172-a253-4401-b0da-46bc1f6313cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916725016 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.916725016
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1670609714
Short name T30
Test name
Test status
Simulation time 564592589130 ps
CPU time 50.08 seconds
Started Jun 30 06:28:42 PM PDT 24
Finished Jun 30 06:29:33 PM PDT 24
Peak memory 201856 kb
Host smart-d2323882-c596-44b4-9793-35d0df02c067
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670609714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1670609714
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3284486914
Short name T1
Test name
Test status
Simulation time 492448028019 ps
CPU time 606.99 seconds
Started Jun 30 06:28:01 PM PDT 24
Finished Jun 30 06:38:08 PM PDT 24
Peak memory 201848 kb
Host smart-8ff78a92-e494-45d8-8e69-149d2d5a0536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284486914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3284486914
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.491461995
Short name T66
Test name
Test status
Simulation time 631772896310 ps
CPU time 1867.5 seconds
Started Jun 30 06:28:13 PM PDT 24
Finished Jun 30 06:59:25 PM PDT 24
Peak memory 210456 kb
Host smart-cbfa6c42-9ae6-4fb8-8ee1-a264821c6292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491461995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
491461995
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2102742383
Short name T78
Test name
Test status
Simulation time 4238265663 ps
CPU time 5.56 seconds
Started Jun 30 06:27:22 PM PDT 24
Finished Jun 30 06:27:31 PM PDT 24
Peak memory 217164 kb
Host smart-b71e022e-2146-4465-9276-1dc32a4ca0d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102742383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2102742383
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2268467340
Short name T81
Test name
Test status
Simulation time 524068509 ps
CPU time 3.2 seconds
Started Jun 30 06:19:50 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201704 kb
Host smart-d109adda-85ee-40c1-a910-d70a5cd7255d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268467340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2268467340
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3193251060
Short name T250
Test name
Test status
Simulation time 201712230748 ps
CPU time 175.43 seconds
Started Jun 30 06:28:59 PM PDT 24
Finished Jun 30 06:31:55 PM PDT 24
Peak memory 211548 kb
Host smart-413244a6-cafc-475b-856d-c31ff6748f8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193251060 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3193251060
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.735772762
Short name T151
Test name
Test status
Simulation time 532168611525 ps
CPU time 311.4 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:32:33 PM PDT 24
Peak memory 201864 kb
Host smart-66df6cfd-7c3c-4051-8be4-0fd39391f46b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735772762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.735772762
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.4279178480
Short name T152
Test name
Test status
Simulation time 554680902344 ps
CPU time 330.05 seconds
Started Jun 30 06:28:09 PM PDT 24
Finished Jun 30 06:33:43 PM PDT 24
Peak memory 201952 kb
Host smart-c812e0a2-432a-4f0f-ad53-c7e5ee628a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279178480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.4279178480
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.299982436
Short name T67
Test name
Test status
Simulation time 34380552078 ps
CPU time 78.89 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:20:58 PM PDT 24
Peak memory 201828 kb
Host smart-a0ac2341-48c1-4da2-be4c-9862fb8872ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299982436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.299982436
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.379125735
Short name T108
Test name
Test status
Simulation time 494573731943 ps
CPU time 1181.41 seconds
Started Jun 30 06:28:41 PM PDT 24
Finished Jun 30 06:48:23 PM PDT 24
Peak memory 201872 kb
Host smart-46eb5e7c-ef23-4a86-8553-6f4c7cf7814d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379125735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.379125735
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2777521148
Short name T242
Test name
Test status
Simulation time 527471187813 ps
CPU time 977.95 seconds
Started Jun 30 06:28:50 PM PDT 24
Finished Jun 30 06:45:09 PM PDT 24
Peak memory 201892 kb
Host smart-67659369-84fa-4f30-9992-1647f6956cb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777521148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2777521148
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3380711234
Short name T174
Test name
Test status
Simulation time 793321064220 ps
CPU time 1319.59 seconds
Started Jun 30 06:27:58 PM PDT 24
Finished Jun 30 06:49:59 PM PDT 24
Peak memory 202228 kb
Host smart-219923fd-c9f9-4d52-ac27-22800b44c1b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380711234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3380711234
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.739661547
Short name T272
Test name
Test status
Simulation time 549758016285 ps
CPU time 904.04 seconds
Started Jun 30 06:31:01 PM PDT 24
Finished Jun 30 06:46:06 PM PDT 24
Peak memory 201792 kb
Host smart-ca40ebf2-271b-45f0-8ea3-2c92144ab65b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739661547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.739661547
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.4130915294
Short name T157
Test name
Test status
Simulation time 598377629250 ps
CPU time 1267.92 seconds
Started Jun 30 06:31:32 PM PDT 24
Finished Jun 30 06:52:40 PM PDT 24
Peak memory 201948 kb
Host smart-bc14c71f-2c33-4819-a4da-7d5703bde38b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130915294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.4130915294
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3893618171
Short name T280
Test name
Test status
Simulation time 533771426982 ps
CPU time 1202.63 seconds
Started Jun 30 06:28:53 PM PDT 24
Finished Jun 30 06:48:56 PM PDT 24
Peak memory 201796 kb
Host smart-46afef39-b37b-4311-844e-2558e18f8965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893618171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3893618171
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2391602930
Short name T290
Test name
Test status
Simulation time 347837644170 ps
CPU time 836.04 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:41:19 PM PDT 24
Peak memory 201740 kb
Host smart-59b4e95f-acb4-4711-b86f-090be38b2c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391602930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2391602930
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2314498761
Short name T249
Test name
Test status
Simulation time 374568811150 ps
CPU time 218.1 seconds
Started Jun 30 06:29:32 PM PDT 24
Finished Jun 30 06:33:11 PM PDT 24
Peak memory 201956 kb
Host smart-d32fbfc8-197b-40ad-9334-2b3fae5f486f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314498761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2314498761
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3026747660
Short name T223
Test name
Test status
Simulation time 335522057965 ps
CPU time 386.31 seconds
Started Jun 30 06:30:40 PM PDT 24
Finished Jun 30 06:37:07 PM PDT 24
Peak memory 201912 kb
Host smart-7b830854-bda1-431b-b29b-e77256f55bdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026747660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3026747660
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1723426230
Short name T240
Test name
Test status
Simulation time 524798089669 ps
CPU time 1012.28 seconds
Started Jun 30 06:29:08 PM PDT 24
Finished Jun 30 06:46:01 PM PDT 24
Peak memory 201892 kb
Host smart-55da6e40-3c8c-4d81-ac6a-545feef3d5c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723426230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1723426230
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1525820414
Short name T159
Test name
Test status
Simulation time 510302632533 ps
CPU time 1164.23 seconds
Started Jun 30 06:31:51 PM PDT 24
Finished Jun 30 06:51:15 PM PDT 24
Peak memory 201880 kb
Host smart-97be2431-a1f7-4ef1-b23d-69b60afce13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525820414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1525820414
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.434732960
Short name T417
Test name
Test status
Simulation time 368212492 ps
CPU time 1.48 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 201628 kb
Host smart-c7c45705-c220-48c3-bf5c-1b5c64b853a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434732960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.434732960
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2985288545
Short name T73
Test name
Test status
Simulation time 8567134204 ps
CPU time 20.42 seconds
Started Jun 30 06:19:42 PM PDT 24
Finished Jun 30 06:20:06 PM PDT 24
Peak memory 201816 kb
Host smart-bc305875-5d3f-4341-ba93-a4fc63842e8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985288545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2985288545
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3132392319
Short name T60
Test name
Test status
Simulation time 594678927923 ps
CPU time 1075 seconds
Started Jun 30 06:28:10 PM PDT 24
Finished Jun 30 06:46:09 PM PDT 24
Peak memory 201860 kb
Host smart-57def68b-11db-4981-8cf7-2d270f92d550
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132392319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3132392319
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3022719656
Short name T276
Test name
Test status
Simulation time 86504628910 ps
CPU time 177.81 seconds
Started Jun 30 06:28:37 PM PDT 24
Finished Jun 30 06:31:35 PM PDT 24
Peak memory 210268 kb
Host smart-82bd3eae-fea3-4598-8df9-08a419f98d51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022719656 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3022719656
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.304118766
Short name T293
Test name
Test status
Simulation time 329467116048 ps
CPU time 396.62 seconds
Started Jun 30 06:30:10 PM PDT 24
Finished Jun 30 06:36:47 PM PDT 24
Peak memory 201888 kb
Host smart-a2fbcc66-f114-4fa0-aeb8-72ea96b1e2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304118766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.304118766
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1085549057
Short name T53
Test name
Test status
Simulation time 304997598167 ps
CPU time 1095.57 seconds
Started Jun 30 06:27:52 PM PDT 24
Finished Jun 30 06:46:09 PM PDT 24
Peak memory 202180 kb
Host smart-bef0b4a7-18f6-4d34-8091-259ed23ae089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085549057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1085549057
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1746162413
Short name T163
Test name
Test status
Simulation time 349826619670 ps
CPU time 208.66 seconds
Started Jun 30 06:28:10 PM PDT 24
Finished Jun 30 06:31:42 PM PDT 24
Peak memory 201772 kb
Host smart-edba049b-c8b9-4d39-83b6-b6cc0a1f6ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746162413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1746162413
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2432984655
Short name T309
Test name
Test status
Simulation time 65254510879 ps
CPU time 176.89 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:31:15 PM PDT 24
Peak memory 202592 kb
Host smart-c00a08e0-9508-49d8-a16b-8627f0d20645
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432984655 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2432984655
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3776744842
Short name T227
Test name
Test status
Simulation time 237188392725 ps
CPU time 48.59 seconds
Started Jun 30 06:29:22 PM PDT 24
Finished Jun 30 06:30:11 PM PDT 24
Peak memory 210192 kb
Host smart-7f19e12b-515e-4e76-8961-e3e505285ff3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776744842 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3776744842
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1990776209
Short name T264
Test name
Test status
Simulation time 328632854779 ps
CPU time 739.74 seconds
Started Jun 30 06:27:45 PM PDT 24
Finished Jun 30 06:40:05 PM PDT 24
Peak memory 201884 kb
Host smart-1d7b31f4-ba5e-45a2-91a5-e5b1b4d38fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990776209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1990776209
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2331096077
Short name T59
Test name
Test status
Simulation time 139916105209 ps
CPU time 158.79 seconds
Started Jun 30 06:28:03 PM PDT 24
Finished Jun 30 06:30:45 PM PDT 24
Peak memory 202000 kb
Host smart-636bd97e-e65f-4cb0-93b2-9270e64a67f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331096077 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2331096077
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.374597626
Short name T326
Test name
Test status
Simulation time 324840201897 ps
CPU time 738.49 seconds
Started Jun 30 06:30:49 PM PDT 24
Finished Jun 30 06:43:08 PM PDT 24
Peak memory 201868 kb
Host smart-1bb8e08a-ea07-4953-b759-460f646a3773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374597626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
374597626
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3471068524
Short name T28
Test name
Test status
Simulation time 447572655708 ps
CPU time 515.3 seconds
Started Jun 30 06:27:39 PM PDT 24
Finished Jun 30 06:36:15 PM PDT 24
Peak memory 201880 kb
Host smart-0fbbe380-9673-48b0-9a84-1fcdd09ff82e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471068524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3471068524
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2569990101
Short name T216
Test name
Test status
Simulation time 561934460937 ps
CPU time 633.25 seconds
Started Jun 30 06:30:39 PM PDT 24
Finished Jun 30 06:41:12 PM PDT 24
Peak memory 201948 kb
Host smart-a873a146-b8a4-4390-b0c1-ed78f477e482
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569990101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2569990101
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3063201381
Short name T305
Test name
Test status
Simulation time 331876655589 ps
CPU time 693.71 seconds
Started Jun 30 06:28:50 PM PDT 24
Finished Jun 30 06:40:24 PM PDT 24
Peak memory 201824 kb
Host smart-7b86b18d-2240-4ce5-b9a7-0b28ad65dcfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063201381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3063201381
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.337355750
Short name T222
Test name
Test status
Simulation time 401882069331 ps
CPU time 251.93 seconds
Started Jun 30 06:28:54 PM PDT 24
Finished Jun 30 06:33:07 PM PDT 24
Peak memory 210752 kb
Host smart-d1ba3241-d76a-4aba-8000-271fa5cf79e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337355750 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.337355750
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1230643232
Short name T328
Test name
Test status
Simulation time 62179803723 ps
CPU time 139.35 seconds
Started Jun 30 06:31:02 PM PDT 24
Finished Jun 30 06:33:22 PM PDT 24
Peak memory 210228 kb
Host smart-c023569d-d0be-4b58-be77-df0b8a18a108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230643232 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1230643232
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.476674587
Short name T155
Test name
Test status
Simulation time 175340792082 ps
CPU time 94.99 seconds
Started Jun 30 06:28:06 PM PDT 24
Finished Jun 30 06:29:44 PM PDT 24
Peak memory 201836 kb
Host smart-9bababd7-d291-4feb-ae5a-9c37a4a7ffd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476674587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.476674587
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1425246324
Short name T325
Test name
Test status
Simulation time 376462244747 ps
CPU time 856.32 seconds
Started Jun 30 06:29:23 PM PDT 24
Finished Jun 30 06:43:40 PM PDT 24
Peak memory 201204 kb
Host smart-3dee7f22-214b-4aff-bbbf-7fb5bb44c61a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425246324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1425246324
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2757571755
Short name T189
Test name
Test status
Simulation time 495450371746 ps
CPU time 289.22 seconds
Started Jun 30 06:30:57 PM PDT 24
Finished Jun 30 06:35:47 PM PDT 24
Peak memory 201816 kb
Host smart-f59983dc-bc3f-4e58-a09f-7f5314793395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757571755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2757571755
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2916846919
Short name T131
Test name
Test status
Simulation time 412530407 ps
CPU time 1.08 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:43 PM PDT 24
Peak memory 201480 kb
Host smart-1868aed9-7029-4113-a2f9-6a2bd115ed8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916846919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2916846919
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3757988117
Short name T218
Test name
Test status
Simulation time 328806001378 ps
CPU time 173.26 seconds
Started Jun 30 06:29:56 PM PDT 24
Finished Jun 30 06:32:50 PM PDT 24
Peak memory 201864 kb
Host smart-c7cfed53-f0c1-4e23-9847-238d0ff5754a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757988117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3757988117
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3212202640
Short name T7
Test name
Test status
Simulation time 488680812703 ps
CPU time 300.77 seconds
Started Jun 30 06:29:43 PM PDT 24
Finished Jun 30 06:34:45 PM PDT 24
Peak memory 201904 kb
Host smart-46e3c440-87fd-41e8-b51f-1968fde06672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212202640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3212202640
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3674932669
Short name T265
Test name
Test status
Simulation time 330006247701 ps
CPU time 295.3 seconds
Started Jun 30 06:30:15 PM PDT 24
Finished Jun 30 06:35:11 PM PDT 24
Peak memory 201848 kb
Host smart-2c6409b2-972c-4607-872a-9bcc3182ed39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674932669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3674932669
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3412759498
Short name T263
Test name
Test status
Simulation time 336063257833 ps
CPU time 789.21 seconds
Started Jun 30 06:31:25 PM PDT 24
Finished Jun 30 06:44:35 PM PDT 24
Peak memory 201916 kb
Host smart-e5915602-3757-45b3-92f0-cbeccc3c76d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412759498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3412759498
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1131247381
Short name T311
Test name
Test status
Simulation time 564005665246 ps
CPU time 200.9 seconds
Started Jun 30 06:31:38 PM PDT 24
Finished Jun 30 06:34:59 PM PDT 24
Peak memory 201880 kb
Host smart-b3256675-8f3d-4aec-b860-5cc380398e78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131247381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1131247381
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3726763554
Short name T172
Test name
Test status
Simulation time 533418291593 ps
CPU time 314.17 seconds
Started Jun 30 06:28:02 PM PDT 24
Finished Jun 30 06:33:18 PM PDT 24
Peak memory 201740 kb
Host smart-e796e8e8-82a2-45ea-ab8b-12f3f4507a8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726763554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3726763554
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.481041848
Short name T275
Test name
Test status
Simulation time 430396925495 ps
CPU time 832.71 seconds
Started Jun 30 06:27:49 PM PDT 24
Finished Jun 30 06:41:43 PM PDT 24
Peak memory 201904 kb
Host smart-83a4679d-08f5-4610-85f5-f50c88862b70
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481041848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.481041848
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.259987559
Short name T297
Test name
Test status
Simulation time 195172364872 ps
CPU time 421.76 seconds
Started Jun 30 06:28:26 PM PDT 24
Finished Jun 30 06:35:28 PM PDT 24
Peak memory 201964 kb
Host smart-a3baae20-534b-47bf-9a09-e7fd56199fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259987559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.259987559
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2546917264
Short name T202
Test name
Test status
Simulation time 116849208517 ps
CPU time 577.52 seconds
Started Jun 30 06:28:56 PM PDT 24
Finished Jun 30 06:38:36 PM PDT 24
Peak memory 202164 kb
Host smart-639d9f7a-e615-451b-8c04-f6a50d417293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546917264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2546917264
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3438796562
Short name T236
Test name
Test status
Simulation time 343937633388 ps
CPU time 751.59 seconds
Started Jun 30 06:31:56 PM PDT 24
Finished Jun 30 06:44:28 PM PDT 24
Peak memory 201936 kb
Host smart-c947cc02-7b93-4381-ae36-a6c33b65daab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438796562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3438796562
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2756064598
Short name T313
Test name
Test status
Simulation time 652326602984 ps
CPU time 1527.96 seconds
Started Jun 30 06:27:47 PM PDT 24
Finished Jun 30 06:53:16 PM PDT 24
Peak memory 201912 kb
Host smart-89b0d699-bcc2-4ef5-9f5a-d177e90c0a35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756064598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2756064598
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3725302129
Short name T19
Test name
Test status
Simulation time 54879525788 ps
CPU time 170.17 seconds
Started Jun 30 06:27:49 PM PDT 24
Finished Jun 30 06:30:40 PM PDT 24
Peak memory 210536 kb
Host smart-1dadd19f-63a2-42de-976c-015a6ebb9d41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725302129 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3725302129
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1115941794
Short name T90
Test name
Test status
Simulation time 8633966329 ps
CPU time 5.38 seconds
Started Jun 30 06:19:49 PM PDT 24
Finished Jun 30 06:19:56 PM PDT 24
Peak memory 201760 kb
Host smart-ddd819a7-3618-4a01-82f0-bd4449b575c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115941794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1115941794
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2604921432
Short name T62
Test name
Test status
Simulation time 435655594527 ps
CPU time 349.67 seconds
Started Jun 30 06:27:21 PM PDT 24
Finished Jun 30 06:33:15 PM PDT 24
Peak memory 210380 kb
Host smart-1a0b7c11-25c4-4ee9-b049-86a2f33d0af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604921432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2604921432
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1781511330
Short name T150
Test name
Test status
Simulation time 514388051351 ps
CPU time 312.21 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:33:19 PM PDT 24
Peak memory 201892 kb
Host smart-35df18db-fa27-4da7-9c3c-9dd74f8e73d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781511330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1781511330
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2410085673
Short name T211
Test name
Test status
Simulation time 71074830616 ps
CPU time 226.21 seconds
Started Jun 30 06:28:05 PM PDT 24
Finished Jun 30 06:31:54 PM PDT 24
Peak memory 202208 kb
Host smart-f7c33c6c-4230-420c-979a-3bcb5c59f352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410085673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2410085673
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2449083801
Short name T345
Test name
Test status
Simulation time 110556822071 ps
CPU time 246.63 seconds
Started Jun 30 06:28:16 PM PDT 24
Finished Jun 30 06:32:25 PM PDT 24
Peak memory 210256 kb
Host smart-4651dee8-378e-4be5-8fb1-f2c78134ddfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449083801 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2449083801
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2565522236
Short name T303
Test name
Test status
Simulation time 493480521075 ps
CPU time 775.86 seconds
Started Jun 30 06:28:18 PM PDT 24
Finished Jun 30 06:41:16 PM PDT 24
Peak memory 201840 kb
Host smart-9e39947b-5e69-46fd-a946-ad876f4b472d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565522236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2565522236
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1848997793
Short name T296
Test name
Test status
Simulation time 341178726428 ps
CPU time 195.46 seconds
Started Jun 30 06:28:45 PM PDT 24
Finished Jun 30 06:32:01 PM PDT 24
Peak memory 201840 kb
Host smart-03d50f9b-6933-4c18-9376-e9d72be44936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848997793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1848997793
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.126405439
Short name T314
Test name
Test status
Simulation time 268135704025 ps
CPU time 223.34 seconds
Started Jun 30 06:28:56 PM PDT 24
Finished Jun 30 06:32:41 PM PDT 24
Peak memory 210232 kb
Host smart-4223a455-1936-4567-ba7e-edff4810bb21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126405439 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.126405439
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2088377387
Short name T251
Test name
Test status
Simulation time 365822082635 ps
CPU time 130.41 seconds
Started Jun 30 06:29:49 PM PDT 24
Finished Jun 30 06:31:59 PM PDT 24
Peak memory 201872 kb
Host smart-8e070ebd-9f4c-485b-ba47-3276570e0c1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088377387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2088377387
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1181331312
Short name T316
Test name
Test status
Simulation time 324318012889 ps
CPU time 230.79 seconds
Started Jun 30 06:30:17 PM PDT 24
Finished Jun 30 06:34:08 PM PDT 24
Peak memory 201892 kb
Host smart-a16cfa46-d8cf-4981-9b9b-868bd76e3bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181331312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1181331312
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.403762293
Short name T160
Test name
Test status
Simulation time 493569609696 ps
CPU time 286.31 seconds
Started Jun 30 06:31:39 PM PDT 24
Finished Jun 30 06:36:26 PM PDT 24
Peak memory 201868 kb
Host smart-6168b847-4397-47de-8ce2-4d59ee3517bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403762293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.403762293
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.999223252
Short name T351
Test name
Test status
Simulation time 4452623235 ps
CPU time 11.87 seconds
Started Jun 30 06:19:44 PM PDT 24
Finished Jun 30 06:19:58 PM PDT 24
Peak memory 201848 kb
Host smart-fadc4098-52eb-4201-b02f-97530734b6f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999223252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.999223252
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3350166051
Short name T18
Test name
Test status
Simulation time 217649368853 ps
CPU time 474.45 seconds
Started Jun 30 06:28:02 PM PDT 24
Finished Jun 30 06:35:57 PM PDT 24
Peak memory 210584 kb
Host smart-adb2e1da-ed75-421d-94e1-db036d0da7b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350166051 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3350166051
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1452629361
Short name T292
Test name
Test status
Simulation time 165249485930 ps
CPU time 54.85 seconds
Started Jun 30 06:28:02 PM PDT 24
Finished Jun 30 06:28:59 PM PDT 24
Peak memory 201864 kb
Host smart-2b919977-b825-418a-af99-6ccea3d7d7a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452629361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1452629361
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.919913209
Short name T169
Test name
Test status
Simulation time 494697273447 ps
CPU time 1057.2 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:45:44 PM PDT 24
Peak memory 201844 kb
Host smart-1e7fa12c-e816-49fb-b5fe-b538a1c809e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=919913209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.919913209
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1346902988
Short name T213
Test name
Test status
Simulation time 128389617565 ps
CPU time 711.54 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:40:00 PM PDT 24
Peak memory 202180 kb
Host smart-10b9736e-0f0e-4c11-a8b4-313573bb804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346902988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1346902988
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2016223390
Short name T298
Test name
Test status
Simulation time 490376712053 ps
CPU time 1139.74 seconds
Started Jun 30 06:28:05 PM PDT 24
Finished Jun 30 06:47:08 PM PDT 24
Peak memory 201928 kb
Host smart-ad4f6550-1eb5-490c-b8aa-0d3562caa0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016223390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2016223390
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2202448122
Short name T254
Test name
Test status
Simulation time 169252660329 ps
CPU time 190.55 seconds
Started Jun 30 06:28:08 PM PDT 24
Finished Jun 30 06:31:23 PM PDT 24
Peak memory 201832 kb
Host smart-2ad34217-c077-4cd4-a1f7-c23d9fbb5281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202448122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2202448122
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2359567336
Short name T205
Test name
Test status
Simulation time 98877568016 ps
CPU time 362.15 seconds
Started Jun 30 06:28:05 PM PDT 24
Finished Jun 30 06:34:11 PM PDT 24
Peak memory 202148 kb
Host smart-88bf6893-8e45-4fac-ba75-f5d244bf8d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359567336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2359567336
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3117649081
Short name T283
Test name
Test status
Simulation time 349841117755 ps
CPU time 239.79 seconds
Started Jun 30 06:28:16 PM PDT 24
Finished Jun 30 06:32:19 PM PDT 24
Peak memory 201824 kb
Host smart-cf084efc-4a77-4ae2-bc7f-eda2098676f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117649081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3117649081
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1363073842
Short name T206
Test name
Test status
Simulation time 796391325678 ps
CPU time 1771.93 seconds
Started Jun 30 06:29:02 PM PDT 24
Finished Jun 30 06:58:35 PM PDT 24
Peak memory 210380 kb
Host smart-4c90fe23-a116-4fb0-9298-726184e648b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363073842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1363073842
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.996454505
Short name T319
Test name
Test status
Simulation time 337387314445 ps
CPU time 194.52 seconds
Started Jun 30 06:29:28 PM PDT 24
Finished Jun 30 06:32:43 PM PDT 24
Peak memory 201932 kb
Host smart-2e732341-feb5-40b5-bcd7-33c44ce243d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996454505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.996454505
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1327554252
Short name T207
Test name
Test status
Simulation time 75075229345 ps
CPU time 359.92 seconds
Started Jun 30 06:29:44 PM PDT 24
Finished Jun 30 06:35:44 PM PDT 24
Peak memory 202208 kb
Host smart-585658fa-0147-4665-be9c-a56efd256128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327554252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1327554252
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.430999767
Short name T287
Test name
Test status
Simulation time 366637181393 ps
CPU time 868.11 seconds
Started Jun 30 06:30:10 PM PDT 24
Finished Jun 30 06:44:39 PM PDT 24
Peak memory 201952 kb
Host smart-5c346938-8263-4b7a-b0f4-fe16044410b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430999767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.430999767
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2216451984
Short name T220
Test name
Test status
Simulation time 467799005720 ps
CPU time 141.34 seconds
Started Jun 30 06:31:29 PM PDT 24
Finished Jun 30 06:33:52 PM PDT 24
Peak memory 201896 kb
Host smart-0859588d-c533-47fc-9867-e905642cfd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216451984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2216451984
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.190068538
Short name T266
Test name
Test status
Simulation time 524944638383 ps
CPU time 303.08 seconds
Started Jun 30 06:32:02 PM PDT 24
Finished Jun 30 06:37:06 PM PDT 24
Peak memory 201852 kb
Host smart-77660016-8957-4dec-a0e8-971bf7f2d13f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190068538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.190068538
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1764998033
Short name T337
Test name
Test status
Simulation time 224151103269 ps
CPU time 494.8 seconds
Started Jun 30 06:32:04 PM PDT 24
Finished Jun 30 06:40:19 PM PDT 24
Peak memory 201860 kb
Host smart-4fdee0be-9980-4979-a8ec-d416c0b9a64a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764998033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1764998033
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4234596615
Short name T147
Test name
Test status
Simulation time 788562590 ps
CPU time 2.5 seconds
Started Jun 30 06:19:33 PM PDT 24
Finished Jun 30 06:19:37 PM PDT 24
Peak memory 201728 kb
Host smart-4197208b-470d-446f-b1ec-bbc1d5e0f4b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234596615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.4234596615
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4050555088
Short name T818
Test name
Test status
Simulation time 54121869938 ps
CPU time 35.57 seconds
Started Jun 30 06:19:34 PM PDT 24
Finished Jun 30 06:20:11 PM PDT 24
Peak memory 201756 kb
Host smart-7583dc61-2674-446c-903e-f450345afcb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050555088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4050555088
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3591671503
Short name T134
Test name
Test status
Simulation time 1321162279 ps
CPU time 2.31 seconds
Started Jun 30 06:19:34 PM PDT 24
Finished Jun 30 06:19:38 PM PDT 24
Peak memory 201496 kb
Host smart-b058c5d5-a691-427c-b98f-b81feefb976e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591671503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3591671503
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1126760563
Short name T856
Test name
Test status
Simulation time 476426983 ps
CPU time 1.89 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:43 PM PDT 24
Peak memory 201540 kb
Host smart-ec3f912f-cc47-46ac-bbfe-112463dd131e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126760563 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1126760563
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3103476734
Short name T887
Test name
Test status
Simulation time 406041350 ps
CPU time 1.7 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:41 PM PDT 24
Peak memory 201424 kb
Host smart-3abef3b7-25c0-43eb-9833-9c16ad84b1b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103476734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3103476734
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2707185456
Short name T808
Test name
Test status
Simulation time 376337409 ps
CPU time 0.87 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:40 PM PDT 24
Peak memory 201384 kb
Host smart-2915d6d2-c27c-43e5-84ab-e7d648ba54f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707185456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2707185456
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1538510471
Short name T906
Test name
Test status
Simulation time 1854671422 ps
CPU time 6.48 seconds
Started Jun 30 06:19:33 PM PDT 24
Finished Jun 30 06:19:41 PM PDT 24
Peak memory 201508 kb
Host smart-53a22669-3b87-4546-af3d-c2d8212e6143
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538510471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1538510471
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2565434353
Short name T879
Test name
Test status
Simulation time 630815580 ps
CPU time 2.22 seconds
Started Jun 30 06:19:35 PM PDT 24
Finished Jun 30 06:19:40 PM PDT 24
Peak memory 201656 kb
Host smart-a5ccd83b-a1d9-430f-b835-ea25619941c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565434353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2565434353
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2828411629
Short name T872
Test name
Test status
Simulation time 4394988785 ps
CPU time 6.2 seconds
Started Jun 30 06:19:33 PM PDT 24
Finished Jun 30 06:19:41 PM PDT 24
Peak memory 201820 kb
Host smart-58d74677-02dd-4e13-ab4d-29a0b7f470bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828411629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2828411629
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.685402748
Short name T146
Test name
Test status
Simulation time 1162356312 ps
CPU time 2.98 seconds
Started Jun 30 06:19:34 PM PDT 24
Finished Jun 30 06:19:38 PM PDT 24
Peak memory 201680 kb
Host smart-cd6f8d36-41f9-460a-916f-542bdb8d9585
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685402748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.685402748
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3567655907
Short name T68
Test name
Test status
Simulation time 44977022031 ps
CPU time 41.74 seconds
Started Jun 30 06:19:35 PM PDT 24
Finished Jun 30 06:20:19 PM PDT 24
Peak memory 201820 kb
Host smart-e7a25879-2c25-47cc-b6dc-388972439882
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567655907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3567655907
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.48484988
Short name T857
Test name
Test status
Simulation time 1172570647 ps
CPU time 1.64 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:43 PM PDT 24
Peak memory 201516 kb
Host smart-75ad1f1f-f6e5-4ae7-a668-bddd1584d99f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48484988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_res
et.48484988
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3170209139
Short name T865
Test name
Test status
Simulation time 471934863 ps
CPU time 1.27 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:40 PM PDT 24
Peak memory 201548 kb
Host smart-1a7b7f27-54e8-45a9-baa2-8827794ff96e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170209139 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3170209139
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3984364158
Short name T807
Test name
Test status
Simulation time 445531657 ps
CPU time 0.79 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:41 PM PDT 24
Peak memory 201416 kb
Host smart-5a2e105f-ae9c-4607-aa32-bbeb1085d060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984364158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3984364158
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2910699465
Short name T844
Test name
Test status
Simulation time 2261625255 ps
CPU time 4.23 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:43 PM PDT 24
Peak memory 201620 kb
Host smart-cb829c3f-7487-45af-9ece-c3868cf2e656
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910699465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2910699465
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3734826108
Short name T77
Test name
Test status
Simulation time 349844367 ps
CPU time 1.41 seconds
Started Jun 30 06:19:35 PM PDT 24
Finished Jun 30 06:19:38 PM PDT 24
Peak memory 201752 kb
Host smart-7c98b48c-69fb-4d52-a0cf-652a2e6b1cde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734826108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3734826108
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1607902421
Short name T867
Test name
Test status
Simulation time 8214957453 ps
CPU time 16.82 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201780 kb
Host smart-017a9684-b900-4b17-8c0a-95969ffe2163
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607902421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1607902421
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3655676185
Short name T896
Test name
Test status
Simulation time 564596811 ps
CPU time 1.02 seconds
Started Jun 30 06:19:43 PM PDT 24
Finished Jun 30 06:19:46 PM PDT 24
Peak memory 201564 kb
Host smart-3f683fb2-4222-43df-9774-07527eb358d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655676185 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3655676185
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2495313937
Short name T851
Test name
Test status
Simulation time 376340975 ps
CPU time 1.57 seconds
Started Jun 30 06:19:43 PM PDT 24
Finished Jun 30 06:19:48 PM PDT 24
Peak memory 201484 kb
Host smart-5b6f049b-eacc-41af-9ca9-44b00be0dcca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495313937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2495313937
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.85384776
Short name T911
Test name
Test status
Simulation time 533908566 ps
CPU time 1.21 seconds
Started Jun 30 06:19:46 PM PDT 24
Finished Jun 30 06:19:49 PM PDT 24
Peak memory 201420 kb
Host smart-bc7be2dc-c154-40fd-b0f6-ce677367f327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85384776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.85384776
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.189760019
Short name T907
Test name
Test status
Simulation time 4015367070 ps
CPU time 13.69 seconds
Started Jun 30 06:19:44 PM PDT 24
Finished Jun 30 06:20:00 PM PDT 24
Peak memory 201820 kb
Host smart-b2021526-93fd-4e16-a81e-1b7439d4ca44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189760019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.189760019
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3107255210
Short name T874
Test name
Test status
Simulation time 609193792 ps
CPU time 1.7 seconds
Started Jun 30 06:19:45 PM PDT 24
Finished Jun 30 06:19:49 PM PDT 24
Peak memory 201784 kb
Host smart-f2fbb85c-b512-4ce1-8bee-3debb923bd19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107255210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3107255210
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1062765023
Short name T893
Test name
Test status
Simulation time 4277660886 ps
CPU time 6.98 seconds
Started Jun 30 06:19:43 PM PDT 24
Finished Jun 30 06:19:53 PM PDT 24
Peak memory 201840 kb
Host smart-2a6c9acb-c699-4c3a-8cd5-c649cc4e499a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062765023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1062765023
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.282048310
Short name T823
Test name
Test status
Simulation time 340338579 ps
CPU time 1.59 seconds
Started Jun 30 06:19:45 PM PDT 24
Finished Jun 30 06:19:49 PM PDT 24
Peak memory 201556 kb
Host smart-88adbed6-dfc3-412e-bc6c-aaa993db4388
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282048310 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.282048310
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3414347153
Short name T890
Test name
Test status
Simulation time 508779182 ps
CPU time 1.39 seconds
Started Jun 30 06:19:43 PM PDT 24
Finished Jun 30 06:19:47 PM PDT 24
Peak memory 201488 kb
Host smart-b9b9985d-a104-4ec5-a00a-d70807990f56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414347153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3414347153
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.176126880
Short name T838
Test name
Test status
Simulation time 440390768 ps
CPU time 0.85 seconds
Started Jun 30 06:19:51 PM PDT 24
Finished Jun 30 06:19:53 PM PDT 24
Peak memory 201376 kb
Host smart-78e9b618-3528-4336-8132-d04bc2e1962c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176126880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.176126880
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.140916780
Short name T848
Test name
Test status
Simulation time 4520551968 ps
CPU time 6.15 seconds
Started Jun 30 06:19:48 PM PDT 24
Finished Jun 30 06:19:56 PM PDT 24
Peak memory 201792 kb
Host smart-eb1741ee-626c-4f97-8d0a-90ef1dd1d469
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140916780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.140916780
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.492184529
Short name T869
Test name
Test status
Simulation time 601406205 ps
CPU time 2.26 seconds
Started Jun 30 06:19:43 PM PDT 24
Finished Jun 30 06:19:48 PM PDT 24
Peak memory 201572 kb
Host smart-5423c800-5768-40ea-9780-7ead955243ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492184529 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.492184529
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3837819695
Short name T902
Test name
Test status
Simulation time 478965147 ps
CPU time 0.92 seconds
Started Jun 30 06:19:42 PM PDT 24
Finished Jun 30 06:19:46 PM PDT 24
Peak memory 201528 kb
Host smart-eb49387a-97e3-4352-8663-cb0b3935cc35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837819695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3837819695
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1364147542
Short name T864
Test name
Test status
Simulation time 461846787 ps
CPU time 1.64 seconds
Started Jun 30 06:19:50 PM PDT 24
Finished Jun 30 06:19:54 PM PDT 24
Peak memory 201380 kb
Host smart-af39c66f-6f30-4c7d-a833-10a9f86af98c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364147542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1364147542
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2231935839
Short name T868
Test name
Test status
Simulation time 2662675338 ps
CPU time 1.29 seconds
Started Jun 30 06:19:47 PM PDT 24
Finished Jun 30 06:19:50 PM PDT 24
Peak memory 201640 kb
Host smart-cf6f6175-daf3-4eff-8906-3716489829ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231935839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2231935839
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2431857769
Short name T880
Test name
Test status
Simulation time 708901535 ps
CPU time 1.88 seconds
Started Jun 30 06:19:42 PM PDT 24
Finished Jun 30 06:19:47 PM PDT 24
Peak memory 201824 kb
Host smart-1598a0f7-a8ee-47aa-a08f-aa74e29d0818
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431857769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2431857769
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3390677287
Short name T884
Test name
Test status
Simulation time 545701469 ps
CPU time 1.47 seconds
Started Jun 30 06:19:42 PM PDT 24
Finished Jun 30 06:19:47 PM PDT 24
Peak memory 201568 kb
Host smart-f16214f3-2940-42e2-bcae-424602224c28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390677287 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3390677287
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.467040722
Short name T899
Test name
Test status
Simulation time 349923213 ps
CPU time 1.16 seconds
Started Jun 30 06:19:46 PM PDT 24
Finished Jun 30 06:19:49 PM PDT 24
Peak memory 201516 kb
Host smart-e7991259-2e30-4562-8c31-d799bcf91975
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467040722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.467040722
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3575761652
Short name T905
Test name
Test status
Simulation time 481935201 ps
CPU time 1.14 seconds
Started Jun 30 06:19:42 PM PDT 24
Finished Jun 30 06:19:46 PM PDT 24
Peak memory 201388 kb
Host smart-58c8404e-84fb-4bb0-86b7-549dc7e6ecae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575761652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3575761652
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2911090307
Short name T875
Test name
Test status
Simulation time 3162541426 ps
CPU time 10.1 seconds
Started Jun 30 06:19:50 PM PDT 24
Finished Jun 30 06:20:01 PM PDT 24
Peak memory 201740 kb
Host smart-156f823f-d82f-45c4-8020-d939dd24f428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911090307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2911090307
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.634229086
Short name T76
Test name
Test status
Simulation time 518229574 ps
CPU time 2.55 seconds
Started Jun 30 06:19:45 PM PDT 24
Finished Jun 30 06:19:50 PM PDT 24
Peak memory 201768 kb
Host smart-43cb247b-f08a-4409-8233-6add5df199ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634229086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.634229086
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3385310785
Short name T895
Test name
Test status
Simulation time 4244060388 ps
CPU time 11.56 seconds
Started Jun 30 06:19:44 PM PDT 24
Finished Jun 30 06:19:58 PM PDT 24
Peak memory 201796 kb
Host smart-31b77b67-e2f9-4253-9ee5-84971874c38c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385310785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3385310785
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.126175979
Short name T903
Test name
Test status
Simulation time 569424636 ps
CPU time 1.11 seconds
Started Jun 30 06:19:44 PM PDT 24
Finished Jun 30 06:19:48 PM PDT 24
Peak memory 201572 kb
Host smart-2fb68c02-e8ad-429e-991d-91bf6d4666ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126175979 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.126175979
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.886502597
Short name T140
Test name
Test status
Simulation time 603628392 ps
CPU time 0.98 seconds
Started Jun 30 06:19:45 PM PDT 24
Finished Jun 30 06:19:48 PM PDT 24
Peak memory 201456 kb
Host smart-b91f6cd2-ea50-4c2a-9cc3-2a9f07a13fc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886502597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.886502597
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3912083416
Short name T859
Test name
Test status
Simulation time 374559106 ps
CPU time 1.48 seconds
Started Jun 30 06:19:45 PM PDT 24
Finished Jun 30 06:19:48 PM PDT 24
Peak memory 201428 kb
Host smart-1f4ef3f4-16eb-46fd-a11b-9e8ccd5ec23a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912083416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3912083416
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3430002057
Short name T833
Test name
Test status
Simulation time 2308955521 ps
CPU time 4.23 seconds
Started Jun 30 06:19:47 PM PDT 24
Finished Jun 30 06:19:53 PM PDT 24
Peak memory 201620 kb
Host smart-479bdc64-ccc0-442b-914a-50ef654a4ca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430002057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3430002057
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.254473104
Short name T845
Test name
Test status
Simulation time 595730876 ps
CPU time 3.27 seconds
Started Jun 30 06:19:42 PM PDT 24
Finished Jun 30 06:19:49 PM PDT 24
Peak memory 201768 kb
Host smart-47a1f9d2-87cf-42a3-95f2-2314ae253f09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254473104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.254473104
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3584562180
Short name T74
Test name
Test status
Simulation time 8049478735 ps
CPU time 20.45 seconds
Started Jun 30 06:19:44 PM PDT 24
Finished Jun 30 06:20:07 PM PDT 24
Peak memory 201764 kb
Host smart-d93ebfb4-b0bf-46ae-8247-6a2b11c37cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584562180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3584562180
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1300704085
Short name T870
Test name
Test status
Simulation time 566182472 ps
CPU time 1.25 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:56 PM PDT 24
Peak memory 201528 kb
Host smart-a3f2bcae-3bde-4071-b114-b1bbab7a88da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300704085 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1300704085
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2122952561
Short name T136
Test name
Test status
Simulation time 412340607 ps
CPU time 0.94 seconds
Started Jun 30 06:19:51 PM PDT 24
Finished Jun 30 06:19:54 PM PDT 24
Peak memory 201516 kb
Host smart-476199e3-e18a-46f3-89b8-07e266989d3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122952561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2122952561
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.917794180
Short name T854
Test name
Test status
Simulation time 381192919 ps
CPU time 1.06 seconds
Started Jun 30 06:19:49 PM PDT 24
Finished Jun 30 06:19:51 PM PDT 24
Peak memory 201420 kb
Host smart-d82161b8-99bb-4b5e-8e6a-3492d1eb3096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917794180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.917794180
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2630575330
Short name T143
Test name
Test status
Simulation time 4888831894 ps
CPU time 3.52 seconds
Started Jun 30 06:19:49 PM PDT 24
Finished Jun 30 06:19:54 PM PDT 24
Peak memory 201796 kb
Host smart-989b48e5-bd3a-412d-b9b0-251b4bd327e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630575330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2630575330
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1495624808
Short name T901
Test name
Test status
Simulation time 590894625 ps
CPU time 2.64 seconds
Started Jun 30 06:19:50 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 217588 kb
Host smart-39eb2263-a90f-4aca-b724-f1169f3c4b0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495624808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1495624808
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2627663654
Short name T843
Test name
Test status
Simulation time 4632101673 ps
CPU time 11.45 seconds
Started Jun 30 06:19:50 PM PDT 24
Finished Jun 30 06:20:03 PM PDT 24
Peak memory 201788 kb
Host smart-4ceda29a-e3b9-4289-92ec-51fd87254fca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627663654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2627663654
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1293959282
Short name T917
Test name
Test status
Simulation time 667600811 ps
CPU time 1.84 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:56 PM PDT 24
Peak memory 201596 kb
Host smart-74012bc8-ed93-4b50-9bfb-15ce6d5bf084
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293959282 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1293959282
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4160693976
Short name T138
Test name
Test status
Simulation time 328216669 ps
CPU time 1.08 seconds
Started Jun 30 06:19:51 PM PDT 24
Finished Jun 30 06:19:54 PM PDT 24
Peak memory 201508 kb
Host smart-11ff3da7-1047-4809-8a9c-51b7f37588ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160693976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.4160693976
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3936084207
Short name T806
Test name
Test status
Simulation time 507221933 ps
CPU time 0.76 seconds
Started Jun 30 06:19:50 PM PDT 24
Finished Jun 30 06:19:53 PM PDT 24
Peak memory 201412 kb
Host smart-c6067c4f-cf12-458d-ab46-cefb0c146a6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936084207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3936084207
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4252336928
Short name T70
Test name
Test status
Simulation time 1956783749 ps
CPU time 4.69 seconds
Started Jun 30 06:19:50 PM PDT 24
Finished Jun 30 06:19:56 PM PDT 24
Peak memory 201472 kb
Host smart-97738753-6f99-46cb-a83a-64f3a740ba19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252336928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.4252336928
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3991242182
Short name T913
Test name
Test status
Simulation time 487944706 ps
CPU time 2.07 seconds
Started Jun 30 06:19:49 PM PDT 24
Finished Jun 30 06:19:52 PM PDT 24
Peak memory 218044 kb
Host smart-70c80fa8-fe76-47ab-8a7a-1ea2d8fc58c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991242182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3991242182
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1894647112
Short name T348
Test name
Test status
Simulation time 4152945185 ps
CPU time 9.48 seconds
Started Jun 30 06:19:48 PM PDT 24
Finished Jun 30 06:19:59 PM PDT 24
Peak memory 201912 kb
Host smart-950dcb3f-7736-477d-b397-1bbffdbe9c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894647112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1894647112
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4064754533
Short name T105
Test name
Test status
Simulation time 809893555 ps
CPU time 1.23 seconds
Started Jun 30 06:19:49 PM PDT 24
Finished Jun 30 06:19:52 PM PDT 24
Peak memory 201556 kb
Host smart-165f9bd9-b74b-4fff-9803-4efd13e52024
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064754533 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.4064754533
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4104839630
Short name T133
Test name
Test status
Simulation time 367210498 ps
CPU time 0.91 seconds
Started Jun 30 06:19:50 PM PDT 24
Finished Jun 30 06:19:52 PM PDT 24
Peak memory 201500 kb
Host smart-dc4f3423-0970-49ae-a317-54358069fce3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104839630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.4104839630
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.904492845
Short name T825
Test name
Test status
Simulation time 475254410 ps
CPU time 0.9 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201456 kb
Host smart-d05bc884-b280-4fb2-9d78-ac5620a3951d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904492845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.904492845
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1462655390
Short name T883
Test name
Test status
Simulation time 2373068424 ps
CPU time 1.76 seconds
Started Jun 30 06:19:48 PM PDT 24
Finished Jun 30 06:19:51 PM PDT 24
Peak memory 201828 kb
Host smart-23f21ed9-4827-47e9-ba34-5d70ff8c455d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462655390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1462655390
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1044224689
Short name T83
Test name
Test status
Simulation time 435679819 ps
CPU time 3.44 seconds
Started Jun 30 06:19:50 PM PDT 24
Finished Jun 30 06:19:56 PM PDT 24
Peak memory 209984 kb
Host smart-ea23749c-3e96-4bf8-96c0-be7c2a8a52d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044224689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1044224689
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.744520474
Short name T350
Test name
Test status
Simulation time 4350372666 ps
CPU time 11.5 seconds
Started Jun 30 06:19:54 PM PDT 24
Finished Jun 30 06:20:07 PM PDT 24
Peak memory 201836 kb
Host smart-def13301-efe2-4230-8fdc-efd43300ec28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744520474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.744520474
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3277095474
Short name T885
Test name
Test status
Simulation time 419243889 ps
CPU time 1.28 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:56 PM PDT 24
Peak memory 201544 kb
Host smart-70542052-a16d-44ad-8796-4e18db13fc91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277095474 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3277095474
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.948638387
Short name T836
Test name
Test status
Simulation time 428520195 ps
CPU time 0.97 seconds
Started Jun 30 06:19:48 PM PDT 24
Finished Jun 30 06:19:50 PM PDT 24
Peak memory 201468 kb
Host smart-51aca728-dfc8-48df-996a-56181ecc2efc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948638387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.948638387
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3747514814
Short name T881
Test name
Test status
Simulation time 307980360 ps
CPU time 0.84 seconds
Started Jun 30 06:19:49 PM PDT 24
Finished Jun 30 06:19:51 PM PDT 24
Peak memory 201440 kb
Host smart-c07aa4c8-c28b-42dc-a1cf-5b2b668ac86b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747514814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3747514814
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3345741910
Short name T142
Test name
Test status
Simulation time 4412976272 ps
CPU time 3.5 seconds
Started Jun 30 06:19:51 PM PDT 24
Finished Jun 30 06:19:57 PM PDT 24
Peak memory 201620 kb
Host smart-75400e40-2b02-4f62-9c8c-f65aea03f058
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345741910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3345741910
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3018947347
Short name T873
Test name
Test status
Simulation time 655369825 ps
CPU time 1.52 seconds
Started Jun 30 06:19:49 PM PDT 24
Finished Jun 30 06:19:52 PM PDT 24
Peak memory 201764 kb
Host smart-5b3a1849-b6e7-4430-ae2b-908e5dc474eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018947347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3018947347
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2686667415
Short name T72
Test name
Test status
Simulation time 8823572555 ps
CPU time 21.64 seconds
Started Jun 30 06:19:47 PM PDT 24
Finished Jun 30 06:20:10 PM PDT 24
Peak memory 202080 kb
Host smart-e6b1848d-d3d8-474b-a317-f4430dcd568f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686667415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2686667415
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1470978093
Short name T828
Test name
Test status
Simulation time 605018837 ps
CPU time 1.29 seconds
Started Jun 30 06:19:50 PM PDT 24
Finished Jun 30 06:19:53 PM PDT 24
Peak memory 201500 kb
Host smart-c5763bf2-b4ca-44e3-82ee-5ef1c6876840
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470978093 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1470978093
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4150378092
Short name T137
Test name
Test status
Simulation time 423251713 ps
CPU time 1.01 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201516 kb
Host smart-d6e76606-c5c7-4f9f-9938-878ae81702af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150378092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.4150378092
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1904227572
Short name T813
Test name
Test status
Simulation time 364627373 ps
CPU time 0.88 seconds
Started Jun 30 06:19:50 PM PDT 24
Finished Jun 30 06:19:52 PM PDT 24
Peak memory 201444 kb
Host smart-b091bef7-c30c-43e0-9ad4-51e09aacb5d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904227572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1904227572
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2835357483
Short name T69
Test name
Test status
Simulation time 3180844914 ps
CPU time 2.11 seconds
Started Jun 30 06:19:54 PM PDT 24
Finished Jun 30 06:19:58 PM PDT 24
Peak memory 201848 kb
Host smart-a8c7038d-3af2-49a1-9669-33716db7b470
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835357483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2835357483
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.182845322
Short name T829
Test name
Test status
Simulation time 486157620 ps
CPU time 1.69 seconds
Started Jun 30 06:19:54 PM PDT 24
Finished Jun 30 06:19:58 PM PDT 24
Peak memory 201764 kb
Host smart-0f932b53-016b-4c4b-8980-2e0b52443bf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182845322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.182845322
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3313573263
Short name T82
Test name
Test status
Simulation time 4221626908 ps
CPU time 6.92 seconds
Started Jun 30 06:19:51 PM PDT 24
Finished Jun 30 06:20:00 PM PDT 24
Peak memory 201700 kb
Host smart-2165ada6-c227-4552-9ffd-0c3e00c4127e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313573263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3313573263
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2050623105
Short name T886
Test name
Test status
Simulation time 1393245469 ps
CPU time 5.88 seconds
Started Jun 30 06:19:37 PM PDT 24
Finished Jun 30 06:19:47 PM PDT 24
Peak memory 201700 kb
Host smart-d71a5da3-cabc-4d9d-8819-24ef7dfced6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050623105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2050623105
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2513065918
Short name T912
Test name
Test status
Simulation time 1326211726 ps
CPU time 3.75 seconds
Started Jun 30 06:19:33 PM PDT 24
Finished Jun 30 06:19:38 PM PDT 24
Peak memory 201516 kb
Host smart-9a5a6339-178f-43ed-8cf0-3cc9f0367d61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513065918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2513065918
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2344052360
Short name T852
Test name
Test status
Simulation time 526334400 ps
CPU time 1.27 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:44 PM PDT 24
Peak memory 201560 kb
Host smart-dddde38a-24f4-4f17-a4ec-74f9ba5a3d71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344052360 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2344052360
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2544216542
Short name T132
Test name
Test status
Simulation time 494115066 ps
CPU time 1.64 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:44 PM PDT 24
Peak memory 201476 kb
Host smart-227f226e-2223-4557-be0f-b954967f9aae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544216542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2544216542
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2282076864
Short name T837
Test name
Test status
Simulation time 488364657 ps
CPU time 1.86 seconds
Started Jun 30 06:19:37 PM PDT 24
Finished Jun 30 06:19:43 PM PDT 24
Peak memory 201408 kb
Host smart-67ce37c5-60e7-4e3b-a607-d82b24db50d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282076864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2282076864
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2311001207
Short name T894
Test name
Test status
Simulation time 2556345711 ps
CPU time 2.89 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:42 PM PDT 24
Peak memory 201780 kb
Host smart-9b7a34ef-2d56-461b-b93b-45a5c8c4d29e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311001207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2311001207
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1251818658
Short name T915
Test name
Test status
Simulation time 481713103 ps
CPU time 1.96 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:41 PM PDT 24
Peak memory 201776 kb
Host smart-41940fa8-3101-4af3-a7f1-1ff1e53132ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251818658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1251818658
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1777284956
Short name T349
Test name
Test status
Simulation time 4133026471 ps
CPU time 11.32 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:50 PM PDT 24
Peak memory 201836 kb
Host smart-f6e24b7f-50cd-4270-bb8e-ef40eb5dae5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777284956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1777284956
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2228925802
Short name T826
Test name
Test status
Simulation time 425938329 ps
CPU time 0.92 seconds
Started Jun 30 06:19:53 PM PDT 24
Finished Jun 30 06:19:56 PM PDT 24
Peak memory 201428 kb
Host smart-6441b34d-6e60-4456-9e1d-5fbcc7beccb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228925802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2228925802
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3077613813
Short name T840
Test name
Test status
Simulation time 488440099 ps
CPU time 0.94 seconds
Started Jun 30 06:19:51 PM PDT 24
Finished Jun 30 06:19:54 PM PDT 24
Peak memory 201412 kb
Host smart-6a9c5441-296b-400c-a45d-8ba8981a481d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077613813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3077613813
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2488131259
Short name T889
Test name
Test status
Simulation time 410414898 ps
CPU time 0.92 seconds
Started Jun 30 06:19:50 PM PDT 24
Finished Jun 30 06:19:52 PM PDT 24
Peak memory 201436 kb
Host smart-720717ae-4d0b-4174-a89f-e9441b2cf280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488131259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2488131259
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3757925078
Short name T846
Test name
Test status
Simulation time 461574222 ps
CPU time 0.74 seconds
Started Jun 30 06:19:53 PM PDT 24
Finished Jun 30 06:19:56 PM PDT 24
Peak memory 201428 kb
Host smart-80060b39-4be8-417d-8ac3-d18af7552f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757925078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3757925078
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.998995101
Short name T898
Test name
Test status
Simulation time 531796466 ps
CPU time 1.16 seconds
Started Jun 30 06:19:51 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201440 kb
Host smart-3898c963-cc5b-470a-9ea2-ec26b59c856d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998995101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.998995101
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.259156153
Short name T811
Test name
Test status
Simulation time 404650746 ps
CPU time 0.77 seconds
Started Jun 30 06:19:53 PM PDT 24
Finished Jun 30 06:19:56 PM PDT 24
Peak memory 201432 kb
Host smart-50f3028e-0767-411b-983e-bcd0d07e7cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259156153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.259156153
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.312608466
Short name T914
Test name
Test status
Simulation time 407533517 ps
CPU time 0.86 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201412 kb
Host smart-d5c22583-ec79-4c92-8952-0e8dd4606829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312608466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.312608466
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.519725632
Short name T802
Test name
Test status
Simulation time 391246837 ps
CPU time 0.92 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201436 kb
Host smart-6f0a58d4-c02f-4bc5-bb1b-66e04ef3c964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519725632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.519725632
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2248667122
Short name T866
Test name
Test status
Simulation time 357890536 ps
CPU time 0.81 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201460 kb
Host smart-2ac8d494-6c64-45a9-8365-803499519d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248667122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2248667122
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1162891965
Short name T816
Test name
Test status
Simulation time 308576256 ps
CPU time 0.87 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201436 kb
Host smart-0ff5833d-eba4-4715-9063-f4ac85739c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162891965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1162891965
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3243619020
Short name T824
Test name
Test status
Simulation time 657980784 ps
CPU time 2.83 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:45 PM PDT 24
Peak memory 201672 kb
Host smart-403729cd-bcc6-4b6f-a016-b7da90d6f785
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243619020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3243619020
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.876482144
Short name T817
Test name
Test status
Simulation time 53019981079 ps
CPU time 65.31 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:20:47 PM PDT 24
Peak memory 201772 kb
Host smart-3c2c51e1-331d-45f2-800e-1ac8f28aeb20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876482144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.876482144
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.76025916
Short name T897
Test name
Test status
Simulation time 978753881 ps
CPU time 0.83 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:40 PM PDT 24
Peak memory 201496 kb
Host smart-57dd950b-1089-4185-a822-1d0479e9cb77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76025916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_res
et.76025916
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3393584304
Short name T908
Test name
Test status
Simulation time 428407794 ps
CPU time 1.79 seconds
Started Jun 30 06:19:40 PM PDT 24
Finished Jun 30 06:19:46 PM PDT 24
Peak memory 201556 kb
Host smart-1514afe1-1fd0-48d3-9a11-2ac5f10ccb08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393584304 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3393584304
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.9482267
Short name T135
Test name
Test status
Simulation time 466615905 ps
CPU time 1.37 seconds
Started Jun 30 06:19:32 PM PDT 24
Finished Jun 30 06:19:34 PM PDT 24
Peak memory 201512 kb
Host smart-91ec1323-3764-4b09-aee3-a9c7022d73f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9482267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.9482267
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2439118126
Short name T916
Test name
Test status
Simulation time 404271738 ps
CPU time 0.78 seconds
Started Jun 30 06:19:39 PM PDT 24
Finished Jun 30 06:19:44 PM PDT 24
Peak memory 201420 kb
Host smart-572e9baa-b1d2-4af7-9e81-11b8bcd73e8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439118126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2439118126
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1532177771
Short name T141
Test name
Test status
Simulation time 2459580968 ps
CPU time 6.49 seconds
Started Jun 30 06:19:37 PM PDT 24
Finished Jun 30 06:19:47 PM PDT 24
Peak memory 201676 kb
Host smart-c623b5be-4b0b-4cd1-b912-4eadd77a7508
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532177771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1532177771
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3954689527
Short name T835
Test name
Test status
Simulation time 675809630 ps
CPU time 2.36 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:42 PM PDT 24
Peak memory 201780 kb
Host smart-2f2d3d0c-f562-41b9-84f1-b31221364c3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954689527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3954689527
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1330203683
Short name T841
Test name
Test status
Simulation time 8222204012 ps
CPU time 11 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:51 PM PDT 24
Peak memory 201768 kb
Host smart-2eb885c3-e7b3-46d7-809e-833489bff94d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330203683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1330203683
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.66820584
Short name T882
Test name
Test status
Simulation time 364456097 ps
CPU time 0.98 seconds
Started Jun 30 06:19:51 PM PDT 24
Finished Jun 30 06:19:54 PM PDT 24
Peak memory 201388 kb
Host smart-31e25ef4-2680-490d-9b53-4236bc100cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66820584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.66820584
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2788521269
Short name T814
Test name
Test status
Simulation time 383812772 ps
CPU time 0.92 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201396 kb
Host smart-e3e2320b-7eb1-4a38-9ee3-900a98482954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788521269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2788521269
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.683178478
Short name T799
Test name
Test status
Simulation time 448644795 ps
CPU time 1.66 seconds
Started Jun 30 06:19:51 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201432 kb
Host smart-636b239e-4b1c-4323-9bef-94ace0b09b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683178478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.683178478
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2867061688
Short name T809
Test name
Test status
Simulation time 366632185 ps
CPU time 0.75 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201392 kb
Host smart-c0f56722-e853-44a6-b07d-e7834820dda9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867061688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2867061688
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.4131049019
Short name T888
Test name
Test status
Simulation time 296679592 ps
CPU time 1.43 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201432 kb
Host smart-3981f45e-b267-49fb-9b8d-ecd689164ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131049019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.4131049019
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.789821680
Short name T904
Test name
Test status
Simulation time 434080192 ps
CPU time 1.65 seconds
Started Jun 30 06:19:51 PM PDT 24
Finished Jun 30 06:19:54 PM PDT 24
Peak memory 201416 kb
Host smart-42da1975-60c6-4c01-9405-7aeafabbeb35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789821680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.789821680
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4251036343
Short name T804
Test name
Test status
Simulation time 480658490 ps
CPU time 1 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201428 kb
Host smart-8fcedbf1-89a7-4ecf-addf-ab27eb845c3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251036343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.4251036343
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.871828140
Short name T821
Test name
Test status
Simulation time 517318184 ps
CPU time 0.91 seconds
Started Jun 30 06:19:52 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201396 kb
Host smart-10325753-5558-4bd5-b478-1c74a8155008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871828140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.871828140
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.351242470
Short name T853
Test name
Test status
Simulation time 442925883 ps
CPU time 1.7 seconds
Started Jun 30 06:19:51 PM PDT 24
Finished Jun 30 06:19:54 PM PDT 24
Peak memory 201444 kb
Host smart-32e02259-3580-4755-b33b-f6aff55ce00e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351242470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.351242470
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3549580119
Short name T847
Test name
Test status
Simulation time 402023126 ps
CPU time 0.83 seconds
Started Jun 30 06:19:57 PM PDT 24
Finished Jun 30 06:20:00 PM PDT 24
Peak memory 201432 kb
Host smart-ef109d5e-ea6f-4b8f-8919-9d8e1cac1bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549580119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3549580119
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2926059867
Short name T144
Test name
Test status
Simulation time 1120441463 ps
CPU time 6.01 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:49 PM PDT 24
Peak memory 201712 kb
Host smart-9b178983-b8da-46d0-9275-0e399d8df294
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926059867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2926059867
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3275642520
Short name T871
Test name
Test status
Simulation time 26058322986 ps
CPU time 27.96 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:20:08 PM PDT 24
Peak memory 201860 kb
Host smart-f0b6847b-5140-42a6-ad86-43328e7ab945
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275642520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3275642520
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2987384647
Short name T145
Test name
Test status
Simulation time 1126085034 ps
CPU time 1.39 seconds
Started Jun 30 06:19:37 PM PDT 24
Finished Jun 30 06:19:42 PM PDT 24
Peak memory 201512 kb
Host smart-456a7053-df53-4f59-8646-d4acdb3f91f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987384647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2987384647
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3184411781
Short name T855
Test name
Test status
Simulation time 418585448 ps
CPU time 1.3 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:41 PM PDT 24
Peak memory 201556 kb
Host smart-68c97214-72ca-4179-ab48-3b9a796a4457
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184411781 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3184411781
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1592028589
Short name T822
Test name
Test status
Simulation time 496018558 ps
CPU time 1.84 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:44 PM PDT 24
Peak memory 201508 kb
Host smart-0d3ddc1f-34bb-4c73-b192-45a82b7057d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592028589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1592028589
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.593840354
Short name T819
Test name
Test status
Simulation time 317873146 ps
CPU time 1.01 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:40 PM PDT 24
Peak memory 201392 kb
Host smart-dbbe948a-c9f0-4996-9bac-03d64a583cf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593840354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.593840354
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1198530351
Short name T877
Test name
Test status
Simulation time 3606258428 ps
CPU time 3.98 seconds
Started Jun 30 06:19:35 PM PDT 24
Finished Jun 30 06:19:42 PM PDT 24
Peak memory 201784 kb
Host smart-08176b5f-6e9d-45ae-adfc-00488bba5775
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198530351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1198530351
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.542661003
Short name T84
Test name
Test status
Simulation time 378914743 ps
CPU time 2.56 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:44 PM PDT 24
Peak memory 210992 kb
Host smart-759b305c-eb0b-4c54-8942-8b99a7f75793
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542661003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.542661003
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.613642259
Short name T834
Test name
Test status
Simulation time 9027890145 ps
CPU time 7.62 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:47 PM PDT 24
Peak memory 201812 kb
Host smart-f47931c8-7367-453e-89d3-ecad14d8e2d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613642259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.613642259
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1164722502
Short name T900
Test name
Test status
Simulation time 515118731 ps
CPU time 1.91 seconds
Started Jun 30 06:19:58 PM PDT 24
Finished Jun 30 06:20:01 PM PDT 24
Peak memory 201428 kb
Host smart-b910d603-3a62-4afe-a5a0-d1163d3892b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164722502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1164722502
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3664009515
Short name T891
Test name
Test status
Simulation time 407245243 ps
CPU time 1.45 seconds
Started Jun 30 06:19:56 PM PDT 24
Finished Jun 30 06:19:59 PM PDT 24
Peak memory 201432 kb
Host smart-9d08f9ed-8dbd-4f50-ba28-79e8971e20af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664009515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3664009515
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1734164348
Short name T910
Test name
Test status
Simulation time 410044462 ps
CPU time 0.77 seconds
Started Jun 30 06:19:56 PM PDT 24
Finished Jun 30 06:19:58 PM PDT 24
Peak memory 201420 kb
Host smart-15029a07-4e62-441a-b3a8-169ad2994c66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734164348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1734164348
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1187943768
Short name T801
Test name
Test status
Simulation time 320606221 ps
CPU time 1.38 seconds
Started Jun 30 06:19:53 PM PDT 24
Finished Jun 30 06:19:56 PM PDT 24
Peak memory 201352 kb
Host smart-8d96c507-f602-4965-810b-994b702afa57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187943768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1187943768
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3349707729
Short name T919
Test name
Test status
Simulation time 302235593 ps
CPU time 0.98 seconds
Started Jun 30 06:20:00 PM PDT 24
Finished Jun 30 06:20:01 PM PDT 24
Peak memory 201420 kb
Host smart-f09235bd-60b4-4730-9653-6c67a293d3e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349707729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3349707729
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1691453444
Short name T812
Test name
Test status
Simulation time 399978512 ps
CPU time 1.53 seconds
Started Jun 30 06:19:57 PM PDT 24
Finished Jun 30 06:20:00 PM PDT 24
Peak memory 201436 kb
Host smart-3b510ad8-e9db-461b-9c44-d5f11fd14896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691453444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1691453444
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4147716644
Short name T820
Test name
Test status
Simulation time 370381014 ps
CPU time 1.11 seconds
Started Jun 30 06:19:55 PM PDT 24
Finished Jun 30 06:19:57 PM PDT 24
Peak memory 201392 kb
Host smart-5241c4fb-ecf8-4147-ba88-7bf37a9d6732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147716644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4147716644
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3136580722
Short name T815
Test name
Test status
Simulation time 403399594 ps
CPU time 1.62 seconds
Started Jun 30 06:19:55 PM PDT 24
Finished Jun 30 06:19:58 PM PDT 24
Peak memory 201472 kb
Host smart-6aae0330-0953-47eb-830f-5526974c866f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136580722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3136580722
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3045876305
Short name T860
Test name
Test status
Simulation time 492618477 ps
CPU time 1.69 seconds
Started Jun 30 06:19:57 PM PDT 24
Finished Jun 30 06:20:00 PM PDT 24
Peak memory 201404 kb
Host smart-0c900a50-349d-4142-8544-74f0b3a16685
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045876305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3045876305
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2442756412
Short name T803
Test name
Test status
Simulation time 398991397 ps
CPU time 0.88 seconds
Started Jun 30 06:19:54 PM PDT 24
Finished Jun 30 06:19:57 PM PDT 24
Peak memory 201436 kb
Host smart-f7f833a6-04ae-418a-929a-359388d11825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442756412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2442756412
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1917540463
Short name T831
Test name
Test status
Simulation time 611105018 ps
CPU time 1.36 seconds
Started Jun 30 06:19:35 PM PDT 24
Finished Jun 30 06:19:39 PM PDT 24
Peak memory 201564 kb
Host smart-de031b1a-72f6-4536-be6b-3610cc9d3773
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917540463 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1917540463
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2127176054
Short name T878
Test name
Test status
Simulation time 587162304 ps
CPU time 1.02 seconds
Started Jun 30 06:19:41 PM PDT 24
Finished Jun 30 06:19:45 PM PDT 24
Peak memory 201508 kb
Host smart-fd59139e-a3dc-4e6e-8397-df27943e6bc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127176054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2127176054
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3756602889
Short name T863
Test name
Test status
Simulation time 402813377 ps
CPU time 1.5 seconds
Started Jun 30 06:19:37 PM PDT 24
Finished Jun 30 06:19:43 PM PDT 24
Peak memory 201392 kb
Host smart-546edc3d-3c57-4b42-bfa8-c3182b882ecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756602889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3756602889
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.938255553
Short name T839
Test name
Test status
Simulation time 2751729645 ps
CPU time 1.75 seconds
Started Jun 30 06:19:43 PM PDT 24
Finished Jun 30 06:19:48 PM PDT 24
Peak memory 201452 kb
Host smart-9d9290bc-c152-4479-a97c-7ef1860a35b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938255553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.938255553
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.640780437
Short name T862
Test name
Test status
Simulation time 749921176 ps
CPU time 1.98 seconds
Started Jun 30 06:19:41 PM PDT 24
Finished Jun 30 06:19:47 PM PDT 24
Peak memory 201808 kb
Host smart-4d8cd6b6-c07c-432c-91ff-1c9081d92d62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640780437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.640780437
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3549404598
Short name T876
Test name
Test status
Simulation time 4725352863 ps
CPU time 2.94 seconds
Started Jun 30 06:19:42 PM PDT 24
Finished Jun 30 06:19:48 PM PDT 24
Peak memory 201816 kb
Host smart-ea753e7d-0204-4193-9fd7-7255e5cfe4f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549404598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3549404598
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.436046574
Short name T103
Test name
Test status
Simulation time 669112350 ps
CPU time 1.74 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:44 PM PDT 24
Peak memory 201556 kb
Host smart-5b92242d-88f8-4257-8d7a-873d32396f01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436046574 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.436046574
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1894582604
Short name T918
Test name
Test status
Simulation time 505182151 ps
CPU time 1.38 seconds
Started Jun 30 06:19:39 PM PDT 24
Finished Jun 30 06:19:44 PM PDT 24
Peak memory 201288 kb
Host smart-5839b431-b667-4d76-891b-ea3973904375
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894582604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1894582604
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2061956579
Short name T800
Test name
Test status
Simulation time 286242283 ps
CPU time 1.32 seconds
Started Jun 30 06:19:39 PM PDT 24
Finished Jun 30 06:19:45 PM PDT 24
Peak memory 201420 kb
Host smart-4390e93c-78ad-44b3-a8c9-80c41129015d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061956579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2061956579
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3010940102
Short name T850
Test name
Test status
Simulation time 4943514989 ps
CPU time 4.06 seconds
Started Jun 30 06:19:41 PM PDT 24
Finished Jun 30 06:19:49 PM PDT 24
Peak memory 201816 kb
Host smart-3a49a3c1-4760-42e7-8d15-f89d4e6f7336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010940102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3010940102
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1682036922
Short name T86
Test name
Test status
Simulation time 374638753 ps
CPU time 1.66 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:42 PM PDT 24
Peak memory 201752 kb
Host smart-4989eefa-3ce5-44c5-a0a6-8f0270be83d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682036922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1682036922
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2866119477
Short name T104
Test name
Test status
Simulation time 431487423 ps
CPU time 0.97 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:43 PM PDT 24
Peak memory 201624 kb
Host smart-8c80e257-e440-4991-b32a-e7a4087d8eb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866119477 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2866119477
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.579517239
Short name T139
Test name
Test status
Simulation time 493016151 ps
CPU time 1.72 seconds
Started Jun 30 06:19:35 PM PDT 24
Finished Jun 30 06:19:39 PM PDT 24
Peak memory 201516 kb
Host smart-fae0d6cf-d5c7-4552-9df2-f161af1fba04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579517239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.579517239
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2755088910
Short name T827
Test name
Test status
Simulation time 281298193 ps
CPU time 1.27 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:44 PM PDT 24
Peak memory 201444 kb
Host smart-21c280fe-a0ff-4f3d-8bbe-25688a8e04bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755088910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2755088910
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2764420726
Short name T858
Test name
Test status
Simulation time 4826584585 ps
CPU time 10.33 seconds
Started Jun 30 06:19:41 PM PDT 24
Finished Jun 30 06:19:55 PM PDT 24
Peak memory 201816 kb
Host smart-27baaf16-8013-4ef9-b515-5739636df735
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764420726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2764420726
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4194123578
Short name T909
Test name
Test status
Simulation time 579989450 ps
CPU time 3.28 seconds
Started Jun 30 06:19:43 PM PDT 24
Finished Jun 30 06:19:49 PM PDT 24
Peak memory 209836 kb
Host smart-dad774f9-1e10-49d7-8c62-5c82eaba3b58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194123578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4194123578
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4032706043
Short name T347
Test name
Test status
Simulation time 10039661999 ps
CPU time 7.11 seconds
Started Jun 30 06:19:35 PM PDT 24
Finished Jun 30 06:19:43 PM PDT 24
Peak memory 201776 kb
Host smart-ca236635-64a4-46b9-a03c-dcb5108a01d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032706043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.4032706043
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2056107188
Short name T861
Test name
Test status
Simulation time 554696164 ps
CPU time 1.26 seconds
Started Jun 30 06:19:42 PM PDT 24
Finished Jun 30 06:19:47 PM PDT 24
Peak memory 201536 kb
Host smart-bddda771-7376-4b77-9a0a-a4dfa0d615ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056107188 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2056107188
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3106647272
Short name T832
Test name
Test status
Simulation time 489376624 ps
CPU time 1.97 seconds
Started Jun 30 06:19:43 PM PDT 24
Finished Jun 30 06:19:48 PM PDT 24
Peak memory 201476 kb
Host smart-d8753e39-aa15-47db-bfa9-6c063b9c7f60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106647272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3106647272
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1889537221
Short name T810
Test name
Test status
Simulation time 415845403 ps
CPU time 1.17 seconds
Started Jun 30 06:19:39 PM PDT 24
Finished Jun 30 06:19:44 PM PDT 24
Peak memory 201424 kb
Host smart-f38bc89f-4bbc-40aa-a71c-b8b50ccee9b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889537221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1889537221
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2386653033
Short name T830
Test name
Test status
Simulation time 1859230801 ps
CPU time 5.03 seconds
Started Jun 30 06:19:41 PM PDT 24
Finished Jun 30 06:19:50 PM PDT 24
Peak memory 201508 kb
Host smart-f4ae1703-79e6-46e0-81cb-4f40a9f7ac42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386653033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2386653033
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1466329622
Short name T842
Test name
Test status
Simulation time 435253466 ps
CPU time 3.22 seconds
Started Jun 30 06:19:41 PM PDT 24
Finished Jun 30 06:19:48 PM PDT 24
Peak memory 210008 kb
Host smart-9fb7ac79-c6f3-4dcf-889c-7924487b1176
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466329622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1466329622
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2345674446
Short name T89
Test name
Test status
Simulation time 8417847123 ps
CPU time 6.31 seconds
Started Jun 30 06:19:40 PM PDT 24
Finished Jun 30 06:19:50 PM PDT 24
Peak memory 201836 kb
Host smart-5f08307f-60a1-47fb-acc3-0717f0bd1090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345674446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2345674446
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.970828220
Short name T87
Test name
Test status
Simulation time 569887885 ps
CPU time 2.16 seconds
Started Jun 30 06:19:39 PM PDT 24
Finished Jun 30 06:19:45 PM PDT 24
Peak memory 201404 kb
Host smart-f50b891f-9919-4f0f-94ba-55a8ca248a52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970828220 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.970828220
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1465591826
Short name T130
Test name
Test status
Simulation time 533466689 ps
CPU time 1.5 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:44 PM PDT 24
Peak memory 201496 kb
Host smart-72f9487c-15a8-4b3f-87d2-db3a74a90a65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465591826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1465591826
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2948839529
Short name T805
Test name
Test status
Simulation time 410674874 ps
CPU time 0.85 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:43 PM PDT 24
Peak memory 201488 kb
Host smart-40288552-eb21-44bc-aee8-94bf70cb0351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948839529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2948839529
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2895124740
Short name T849
Test name
Test status
Simulation time 1916098277 ps
CPU time 4.37 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:47 PM PDT 24
Peak memory 201508 kb
Host smart-a6a6bc80-9a0d-451d-8294-22b63e31bf0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895124740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2895124740
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4233998333
Short name T892
Test name
Test status
Simulation time 2087878027 ps
CPU time 2.34 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:42 PM PDT 24
Peak memory 201752 kb
Host smart-e69f49f9-ebde-4af7-b164-071a86158619
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233998333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.4233998333
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2537252037
Short name T88
Test name
Test status
Simulation time 4515568785 ps
CPU time 4.36 seconds
Started Jun 30 06:19:41 PM PDT 24
Finished Jun 30 06:19:49 PM PDT 24
Peak memory 201860 kb
Host smart-f3985a02-3a2f-4802-b46c-a8628fd614cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537252037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2537252037
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3760327520
Short name T342
Test name
Test status
Simulation time 342638442007 ps
CPU time 108.1 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:29:10 PM PDT 24
Peak memory 201860 kb
Host smart-cdcb3ca1-50bc-455d-ad11-2219db1a19e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760327520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3760327520
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1219818140
Short name T214
Test name
Test status
Simulation time 162613388109 ps
CPU time 97.92 seconds
Started Jun 30 06:27:33 PM PDT 24
Finished Jun 30 06:29:11 PM PDT 24
Peak memory 201876 kb
Host smart-ecaa2b06-44a1-40bc-883f-121256d221b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219818140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1219818140
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1271666610
Short name T550
Test name
Test status
Simulation time 496855391930 ps
CPU time 613.04 seconds
Started Jun 30 06:27:17 PM PDT 24
Finished Jun 30 06:37:33 PM PDT 24
Peak memory 201852 kb
Host smart-ecae75e1-2c9f-4133-8ba4-f50cb31df4c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271666610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1271666610
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2443349016
Short name T556
Test name
Test status
Simulation time 324887739265 ps
CPU time 182.04 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:30:20 PM PDT 24
Peak memory 201940 kb
Host smart-72ec5ca8-5ee7-46ca-81d9-a1dcc5fc238b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443349016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2443349016
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3805871111
Short name T594
Test name
Test status
Simulation time 164294710893 ps
CPU time 102.7 seconds
Started Jun 30 06:27:26 PM PDT 24
Finished Jun 30 06:29:10 PM PDT 24
Peak memory 201912 kb
Host smart-a127ba1c-dee9-41ee-9dbb-ae9f5e44e411
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805871111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3805871111
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.992875761
Short name T341
Test name
Test status
Simulation time 184424976160 ps
CPU time 100.48 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:29:01 PM PDT 24
Peak memory 201948 kb
Host smart-7f1d2861-7bf9-49f7-8058-3724a04091e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992875761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.992875761
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.762082241
Short name T446
Test name
Test status
Simulation time 421467928344 ps
CPU time 268.25 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:31:51 PM PDT 24
Peak memory 202052 kb
Host smart-de1caeb7-157d-47c8-914b-2016ec6615b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762082241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.762082241
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3172033570
Short name T24
Test name
Test status
Simulation time 76007582301 ps
CPU time 275.87 seconds
Started Jun 30 06:27:32 PM PDT 24
Finished Jun 30 06:32:08 PM PDT 24
Peak memory 202100 kb
Host smart-2b994df1-c030-4ea7-985b-cbf88f2fab4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172033570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3172033570
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1954272211
Short name T590
Test name
Test status
Simulation time 36332152042 ps
CPU time 9.12 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:27:29 PM PDT 24
Peak memory 201676 kb
Host smart-53f7b0b0-1563-4648-abcd-1d9f432a9d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954272211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1954272211
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3861177568
Short name T440
Test name
Test status
Simulation time 3502081197 ps
CPU time 7.94 seconds
Started Jun 30 06:27:14 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 201624 kb
Host smart-836fbdec-90a1-4c51-88cc-fac3b65934aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861177568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3861177568
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2038975912
Short name T91
Test name
Test status
Simulation time 7795607320 ps
CPU time 15.5 seconds
Started Jun 30 06:27:14 PM PDT 24
Finished Jun 30 06:27:33 PM PDT 24
Peak memory 218196 kb
Host smart-7d20e029-97e5-4cba-a1ef-c062c96bde1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038975912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2038975912
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.994049231
Short name T361
Test name
Test status
Simulation time 5941385534 ps
CPU time 4.42 seconds
Started Jun 30 06:27:23 PM PDT 24
Finished Jun 30 06:27:31 PM PDT 24
Peak memory 201672 kb
Host smart-8bfa41ab-d0b0-46c4-ab04-b4bbf080104d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994049231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.994049231
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3166794140
Short name T301
Test name
Test status
Simulation time 753912393181 ps
CPU time 2432.69 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 07:07:56 PM PDT 24
Peak memory 210392 kb
Host smart-18d39b7c-759a-452e-9fcd-3f5c0c88ee87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166794140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3166794140
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.108170101
Short name T75
Test name
Test status
Simulation time 419090141039 ps
CPU time 150.25 seconds
Started Jun 30 06:27:22 PM PDT 24
Finished Jun 30 06:29:56 PM PDT 24
Peak memory 217760 kb
Host smart-0fc6a5a0-9938-4ae2-aa56-87ba649b9302
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108170101 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.108170101
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2631557333
Short name T613
Test name
Test status
Simulation time 390666199 ps
CPU time 0.83 seconds
Started Jun 30 06:27:26 PM PDT 24
Finished Jun 30 06:27:33 PM PDT 24
Peak memory 201604 kb
Host smart-15f06eec-3dad-4aaa-9066-5b52a8f67527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631557333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2631557333
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1328540951
Short name T560
Test name
Test status
Simulation time 320411206765 ps
CPU time 666.75 seconds
Started Jun 30 06:27:21 PM PDT 24
Finished Jun 30 06:38:32 PM PDT 24
Peak memory 201852 kb
Host smart-02662ae3-8d55-4b9d-81e3-6b6757cb5413
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328540951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1328540951
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3575948181
Short name T57
Test name
Test status
Simulation time 161274335099 ps
CPU time 355.57 seconds
Started Jun 30 06:27:22 PM PDT 24
Finished Jun 30 06:33:21 PM PDT 24
Peak memory 201844 kb
Host smart-7328eb23-a869-4932-b05b-1fd14cf5316a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575948181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3575948181
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.713256172
Short name T710
Test name
Test status
Simulation time 487199656885 ps
CPU time 1082.05 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:45:21 PM PDT 24
Peak memory 201824 kb
Host smart-238954a6-fca2-42b5-b332-e8d8b8d6bb05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=713256172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.713256172
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3362747040
Short name T126
Test name
Test status
Simulation time 485958695026 ps
CPU time 93.08 seconds
Started Jun 30 06:27:22 PM PDT 24
Finished Jun 30 06:28:59 PM PDT 24
Peak memory 201872 kb
Host smart-4a9ebbcf-5445-4216-807b-5798c1220363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362747040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3362747040
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3729104417
Short name T558
Test name
Test status
Simulation time 168868144369 ps
CPU time 106.21 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:29:11 PM PDT 24
Peak memory 201908 kb
Host smart-6457d811-642d-44e9-ad59-f4dddd94a3a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729104417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3729104417
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1356633352
Short name T623
Test name
Test status
Simulation time 198683121799 ps
CPU time 461.91 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:35:04 PM PDT 24
Peak memory 201860 kb
Host smart-e8b57de3-80fe-4ab5-aae6-8d5968760197
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356633352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1356633352
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.4141729113
Short name T697
Test name
Test status
Simulation time 121333635028 ps
CPU time 654.79 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:38:12 PM PDT 24
Peak memory 202196 kb
Host smart-fd8b2bc0-cae0-4ae7-b1ee-9a3fdc7ea1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141729113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.4141729113
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.4083601189
Short name T507
Test name
Test status
Simulation time 38496263592 ps
CPU time 15.62 seconds
Started Jun 30 06:27:17 PM PDT 24
Finished Jun 30 06:27:36 PM PDT 24
Peak memory 201620 kb
Host smart-b60845d2-a0e2-4fba-91b4-2f1841ee6e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083601189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4083601189
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.4161509838
Short name T487
Test name
Test status
Simulation time 4786879246 ps
CPU time 11.74 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:27:36 PM PDT 24
Peak memory 201684 kb
Host smart-16064427-2c42-46ce-9ae6-8c1b63c81888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161509838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.4161509838
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3044446254
Short name T80
Test name
Test status
Simulation time 4323337969 ps
CPU time 10.48 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:25 PM PDT 24
Peak memory 217040 kb
Host smart-fa90486e-13d8-46e2-903b-09fec7f98d9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044446254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3044446254
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.4130796018
Short name T690
Test name
Test status
Simulation time 5561661958 ps
CPU time 4.67 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:27:23 PM PDT 24
Peak memory 201664 kb
Host smart-adfea811-57d3-4377-9eee-3e5e3017544e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130796018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.4130796018
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1190057027
Short name T549
Test name
Test status
Simulation time 526105219 ps
CPU time 1.17 seconds
Started Jun 30 06:27:59 PM PDT 24
Finished Jun 30 06:28:00 PM PDT 24
Peak memory 201604 kb
Host smart-1fd73ee7-1779-4d4b-a2f3-5576b8ab0736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190057027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1190057027
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2170833651
Short name T692
Test name
Test status
Simulation time 584388454573 ps
CPU time 342.12 seconds
Started Jun 30 06:27:58 PM PDT 24
Finished Jun 30 06:33:40 PM PDT 24
Peak memory 201764 kb
Host smart-edcf3fb4-dcee-4de8-937d-89be60d45726
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170833651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2170833651
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.643166670
Short name T36
Test name
Test status
Simulation time 168895404590 ps
CPU time 394.3 seconds
Started Jun 30 06:27:41 PM PDT 24
Finished Jun 30 06:34:15 PM PDT 24
Peak memory 201892 kb
Host smart-d3674a94-5acd-4b58-8cb4-55e7965e1828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643166670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.643166670
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1138245318
Short name T701
Test name
Test status
Simulation time 163802797636 ps
CPU time 75.21 seconds
Started Jun 30 06:27:56 PM PDT 24
Finished Jun 30 06:29:11 PM PDT 24
Peak memory 201916 kb
Host smart-e3fa8f99-08bd-4ac5-b702-2210e35f26be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138245318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1138245318
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2057633273
Short name T528
Test name
Test status
Simulation time 331966635726 ps
CPU time 196.84 seconds
Started Jun 30 06:27:58 PM PDT 24
Finished Jun 30 06:31:15 PM PDT 24
Peak memory 202044 kb
Host smart-a9d20314-f2eb-414b-9150-a6da332e7c14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057633273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2057633273
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2312247388
Short name T228
Test name
Test status
Simulation time 329679603826 ps
CPU time 72.11 seconds
Started Jun 30 06:27:51 PM PDT 24
Finished Jun 30 06:29:04 PM PDT 24
Peak memory 201864 kb
Host smart-97dd4209-8cc1-4b2f-afa5-d81ed8fa06cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312247388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2312247388
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1817539445
Short name T95
Test name
Test status
Simulation time 498927784830 ps
CPU time 262.94 seconds
Started Jun 30 06:27:48 PM PDT 24
Finished Jun 30 06:32:12 PM PDT 24
Peak memory 201772 kb
Host smart-6de74128-4a02-4af9-8747-eac21179b79b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817539445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1817539445
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.4089788227
Short name T412
Test name
Test status
Simulation time 227240703150 ps
CPU time 456.41 seconds
Started Jun 30 06:27:48 PM PDT 24
Finished Jun 30 06:35:25 PM PDT 24
Peak memory 201868 kb
Host smart-68495f52-3e56-4074-9cab-22ebc2c8fb86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089788227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.4089788227
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1959689611
Short name T379
Test name
Test status
Simulation time 201703017239 ps
CPU time 128.96 seconds
Started Jun 30 06:27:56 PM PDT 24
Finished Jun 30 06:30:06 PM PDT 24
Peak memory 201856 kb
Host smart-10264e55-cdcc-44e8-b4ff-951299a4f01d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959689611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1959689611
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.580083786
Short name T65
Test name
Test status
Simulation time 113613779454 ps
CPU time 411.33 seconds
Started Jun 30 06:27:49 PM PDT 24
Finished Jun 30 06:34:41 PM PDT 24
Peak memory 202184 kb
Host smart-c58647c1-84fb-4de9-97df-d43421d19359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580083786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.580083786
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.601759279
Short name T362
Test name
Test status
Simulation time 25880423754 ps
CPU time 64.01 seconds
Started Jun 30 06:28:00 PM PDT 24
Finished Jun 30 06:29:05 PM PDT 24
Peak memory 201688 kb
Host smart-064c3bfc-9fef-4ea8-a7de-2d6b5a082f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601759279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.601759279
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1707980089
Short name T700
Test name
Test status
Simulation time 2916529184 ps
CPU time 6.88 seconds
Started Jun 30 06:27:54 PM PDT 24
Finished Jun 30 06:28:01 PM PDT 24
Peak memory 201684 kb
Host smart-eb293e1f-96bc-4a9f-8459-9051717016d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707980089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1707980089
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2966530091
Short name T777
Test name
Test status
Simulation time 6088493196 ps
CPU time 7.15 seconds
Started Jun 30 06:27:52 PM PDT 24
Finished Jun 30 06:27:59 PM PDT 24
Peak memory 201672 kb
Host smart-2ab27f18-b770-4995-8f58-9dac7509d412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966530091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2966530091
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1450800084
Short name T94
Test name
Test status
Simulation time 289170593 ps
CPU time 1.24 seconds
Started Jun 30 06:27:59 PM PDT 24
Finished Jun 30 06:28:01 PM PDT 24
Peak memory 201632 kb
Host smart-be067e28-2971-4bfb-af05-6c7e89b9c635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450800084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1450800084
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.616615104
Short name T798
Test name
Test status
Simulation time 366027792996 ps
CPU time 430.77 seconds
Started Jun 30 06:28:02 PM PDT 24
Finished Jun 30 06:35:14 PM PDT 24
Peak memory 201940 kb
Host smart-9c8f3889-1a01-47e8-807d-78d68ed8bc6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616615104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.616615104
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3806855330
Short name T603
Test name
Test status
Simulation time 167004543267 ps
CPU time 95.15 seconds
Started Jun 30 06:28:08 PM PDT 24
Finished Jun 30 06:29:46 PM PDT 24
Peak memory 201872 kb
Host smart-4e874208-0ec2-456e-b465-5ef0aa77a329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806855330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3806855330
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2830550989
Short name T277
Test name
Test status
Simulation time 497395164966 ps
CPU time 1189.56 seconds
Started Jun 30 06:27:49 PM PDT 24
Finished Jun 30 06:47:39 PM PDT 24
Peak memory 201836 kb
Host smart-875c2e89-5222-4248-aadd-b22a850231d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830550989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2830550989
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1777866633
Short name T711
Test name
Test status
Simulation time 500018469952 ps
CPU time 1046.42 seconds
Started Jun 30 06:28:03 PM PDT 24
Finished Jun 30 06:45:32 PM PDT 24
Peak memory 201836 kb
Host smart-6e334b41-863c-486e-bfff-291dd8319584
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777866633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1777866633
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1519621633
Short name T56
Test name
Test status
Simulation time 329113728990 ps
CPU time 729.6 seconds
Started Jun 30 06:27:58 PM PDT 24
Finished Jun 30 06:40:09 PM PDT 24
Peak memory 201844 kb
Host smart-0490d9ab-916f-4381-9610-7ccbba93bfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519621633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1519621633
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.444317586
Short name T712
Test name
Test status
Simulation time 485965100470 ps
CPU time 253.76 seconds
Started Jun 30 06:28:02 PM PDT 24
Finished Jun 30 06:32:18 PM PDT 24
Peak memory 201876 kb
Host smart-cade8cf0-521c-4bb7-a0d0-4d5f74c74833
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=444317586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.444317586
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3794839398
Short name T9
Test name
Test status
Simulation time 347547693469 ps
CPU time 416.03 seconds
Started Jun 30 06:28:01 PM PDT 24
Finished Jun 30 06:34:58 PM PDT 24
Peak memory 201888 kb
Host smart-8e57908f-adad-4538-a768-d6cb02015b6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794839398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3794839398
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3747754477
Short name T431
Test name
Test status
Simulation time 595614242522 ps
CPU time 313.43 seconds
Started Jun 30 06:27:52 PM PDT 24
Finished Jun 30 06:33:06 PM PDT 24
Peak memory 201816 kb
Host smart-9930e35f-b11a-491a-93b1-62e4ec20bfd0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747754477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3747754477
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.229862892
Short name T628
Test name
Test status
Simulation time 131652599182 ps
CPU time 586.64 seconds
Started Jun 30 06:28:06 PM PDT 24
Finished Jun 30 06:37:57 PM PDT 24
Peak memory 202104 kb
Host smart-5df6f6a9-c40c-4603-9f32-4b847fa7b73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229862892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.229862892
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3606006370
Short name T676
Test name
Test status
Simulation time 24199362392 ps
CPU time 13.64 seconds
Started Jun 30 06:27:57 PM PDT 24
Finished Jun 30 06:28:12 PM PDT 24
Peak memory 201680 kb
Host smart-eb3f7531-0681-457e-a94c-4cd183c3f7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606006370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3606006370
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.4139017525
Short name T429
Test name
Test status
Simulation time 3972522513 ps
CPU time 3.03 seconds
Started Jun 30 06:28:10 PM PDT 24
Finished Jun 30 06:28:16 PM PDT 24
Peak memory 201632 kb
Host smart-4141e6a9-0d58-4341-a61d-a170cadb42be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139017525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.4139017525
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3609860560
Short name T367
Test name
Test status
Simulation time 5802672199 ps
CPU time 4.05 seconds
Started Jun 30 06:28:03 PM PDT 24
Finished Jun 30 06:28:10 PM PDT 24
Peak memory 201676 kb
Host smart-f54f52f8-5e5f-475e-9a8c-f7d29c34f938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609860560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3609860560
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3401465949
Short name T210
Test name
Test status
Simulation time 605707836077 ps
CPU time 1666.08 seconds
Started Jun 30 06:27:59 PM PDT 24
Finished Jun 30 06:55:46 PM PDT 24
Peak memory 210288 kb
Host smart-c3e8b9c5-16a9-4858-b874-d4eb640cc112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401465949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3401465949
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1181187044
Short name T17
Test name
Test status
Simulation time 505545722739 ps
CPU time 581.43 seconds
Started Jun 30 06:28:01 PM PDT 24
Finished Jun 30 06:37:44 PM PDT 24
Peak memory 202320 kb
Host smart-b4ad8039-7daa-4825-9e16-7d90b4dcaa3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181187044 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1181187044
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.4000911266
Short name T644
Test name
Test status
Simulation time 309241142 ps
CPU time 1.35 seconds
Started Jun 30 06:28:13 PM PDT 24
Finished Jun 30 06:28:18 PM PDT 24
Peak memory 201628 kb
Host smart-9f6385f0-edd1-4f07-bf2c-be01c9f90bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000911266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.4000911266
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3025340765
Short name T504
Test name
Test status
Simulation time 161545581817 ps
CPU time 185.84 seconds
Started Jun 30 06:28:02 PM PDT 24
Finished Jun 30 06:31:09 PM PDT 24
Peak memory 201868 kb
Host smart-d52c7b4c-cb3f-4152-ae02-8c46a123deee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025340765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3025340765
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3747288891
Short name T195
Test name
Test status
Simulation time 329425706179 ps
CPU time 124.17 seconds
Started Jun 30 06:27:58 PM PDT 24
Finished Jun 30 06:30:03 PM PDT 24
Peak memory 201928 kb
Host smart-2d8c3fd2-85d1-4ac7-8c10-53f41eb22163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747288891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3747288891
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.319365485
Short name T741
Test name
Test status
Simulation time 170460400219 ps
CPU time 109.59 seconds
Started Jun 30 06:27:56 PM PDT 24
Finished Jun 30 06:29:46 PM PDT 24
Peak memory 201856 kb
Host smart-fb09c021-fc4b-4ce4-918d-e069c0f64d17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=319365485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.319365485
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2922917263
Short name T278
Test name
Test status
Simulation time 487747205269 ps
CPU time 280.8 seconds
Started Jun 30 06:27:56 PM PDT 24
Finished Jun 30 06:32:37 PM PDT 24
Peak memory 201940 kb
Host smart-b63bb230-a754-423b-85c7-4948aaba4fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922917263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2922917263
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2219365777
Short name T184
Test name
Test status
Simulation time 323257444790 ps
CPU time 44.2 seconds
Started Jun 30 06:27:59 PM PDT 24
Finished Jun 30 06:28:44 PM PDT 24
Peak memory 201840 kb
Host smart-5e0be7f6-2ae4-40d3-9448-b1b6939b4f44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219365777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2219365777
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1780849694
Short name T260
Test name
Test status
Simulation time 407144344581 ps
CPU time 478.27 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:36:05 PM PDT 24
Peak memory 201812 kb
Host smart-9762ad2a-d76d-4c9f-907f-31ea96920c33
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780849694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1780849694
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.605942953
Short name T485
Test name
Test status
Simulation time 396226133869 ps
CPU time 195.27 seconds
Started Jun 30 06:28:03 PM PDT 24
Finished Jun 30 06:31:21 PM PDT 24
Peak memory 201856 kb
Host smart-2998f0de-0bfa-4c3e-b007-590a31fe663f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605942953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.605942953
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2403780385
Short name T197
Test name
Test status
Simulation time 115223935190 ps
CPU time 463.56 seconds
Started Jun 30 06:27:57 PM PDT 24
Finished Jun 30 06:35:41 PM PDT 24
Peak memory 202252 kb
Host smart-b0a56772-8ec7-4fb9-a3dd-99cf933dd59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403780385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2403780385
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3042678905
Short name T665
Test name
Test status
Simulation time 36602334862 ps
CPU time 88.29 seconds
Started Jun 30 06:27:56 PM PDT 24
Finished Jun 30 06:29:24 PM PDT 24
Peak memory 201684 kb
Host smart-a342dbac-b734-4632-9f0c-ff0d5e1b69f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042678905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3042678905
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3100542391
Short name T433
Test name
Test status
Simulation time 5245782525 ps
CPU time 3.99 seconds
Started Jun 30 06:27:58 PM PDT 24
Finished Jun 30 06:28:02 PM PDT 24
Peak memory 201672 kb
Host smart-75585882-8e6a-49af-a1f2-101bf6b0f256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100542391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3100542391
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3312859633
Short name T397
Test name
Test status
Simulation time 5491166740 ps
CPU time 12.68 seconds
Started Jun 30 06:27:58 PM PDT 24
Finished Jun 30 06:28:12 PM PDT 24
Peak memory 201672 kb
Host smart-e27fa209-4d61-4fbf-9530-7bce1493eb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312859633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3312859633
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3488037428
Short name T699
Test name
Test status
Simulation time 287127389103 ps
CPU time 467.13 seconds
Started Jun 30 06:28:01 PM PDT 24
Finished Jun 30 06:35:49 PM PDT 24
Peak memory 202168 kb
Host smart-d4e12857-b514-4f5c-a744-8fae1f3d5055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488037428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3488037428
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3739453933
Short name T336
Test name
Test status
Simulation time 540524659395 ps
CPU time 93.72 seconds
Started Jun 30 06:28:01 PM PDT 24
Finished Jun 30 06:29:36 PM PDT 24
Peak memory 210532 kb
Host smart-7836acff-7008-4e40-8744-d1d490acce78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739453933 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3739453933
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1292217346
Short name T715
Test name
Test status
Simulation time 363577961 ps
CPU time 1.42 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:28:09 PM PDT 24
Peak memory 201632 kb
Host smart-102cbe98-b394-4ed6-81a8-eb2bc9602cff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292217346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1292217346
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3514253268
Short name T237
Test name
Test status
Simulation time 163351763760 ps
CPU time 374.89 seconds
Started Jun 30 06:28:09 PM PDT 24
Finished Jun 30 06:34:28 PM PDT 24
Peak memory 201768 kb
Host smart-e1a94adb-5f40-432d-87fd-a5eaf3c27396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514253268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3514253268
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3256197728
Short name T573
Test name
Test status
Simulation time 168166555008 ps
CPU time 109.52 seconds
Started Jun 30 06:28:03 PM PDT 24
Finished Jun 30 06:29:54 PM PDT 24
Peak memory 201892 kb
Host smart-15e931b5-449f-4643-9951-53691410d2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256197728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3256197728
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2252158687
Short name T738
Test name
Test status
Simulation time 165317142303 ps
CPU time 365.89 seconds
Started Jun 30 06:28:00 PM PDT 24
Finished Jun 30 06:34:06 PM PDT 24
Peak memory 201852 kb
Host smart-0c71b03b-42ec-4a5e-ae87-4c108d7c6f53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252158687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2252158687
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3852217837
Short name T332
Test name
Test status
Simulation time 331891263671 ps
CPU time 218.16 seconds
Started Jun 30 06:28:03 PM PDT 24
Finished Jun 30 06:31:44 PM PDT 24
Peak memory 201860 kb
Host smart-23e33297-f808-4bbc-b4a6-f2c018735536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852217837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3852217837
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.898084905
Short name T373
Test name
Test status
Simulation time 499198886013 ps
CPU time 1032.35 seconds
Started Jun 30 06:28:05 PM PDT 24
Finished Jun 30 06:45:21 PM PDT 24
Peak memory 201860 kb
Host smart-2c3c6c86-c02f-427b-a2f0-62043d78947e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=898084905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.898084905
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.4253593753
Short name T774
Test name
Test status
Simulation time 196757063487 ps
CPU time 131.43 seconds
Started Jun 30 06:27:57 PM PDT 24
Finished Jun 30 06:30:09 PM PDT 24
Peak memory 201856 kb
Host smart-535c7079-3ce6-4fa4-b35c-514d3c5d61eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253593753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.4253593753
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1176086604
Short name T565
Test name
Test status
Simulation time 75676391745 ps
CPU time 261.99 seconds
Started Jun 30 06:27:59 PM PDT 24
Finished Jun 30 06:32:22 PM PDT 24
Peak memory 202192 kb
Host smart-142bd855-6c2e-4599-8247-06d0f849a1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176086604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1176086604
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2639143223
Short name T426
Test name
Test status
Simulation time 37542853118 ps
CPU time 23.58 seconds
Started Jun 30 06:28:02 PM PDT 24
Finished Jun 30 06:28:27 PM PDT 24
Peak memory 201676 kb
Host smart-b5b60941-cd99-41ea-9e5b-e6a72109bfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639143223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2639143223
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.417179952
Short name T129
Test name
Test status
Simulation time 3528237901 ps
CPU time 4.37 seconds
Started Jun 30 06:28:03 PM PDT 24
Finished Jun 30 06:28:10 PM PDT 24
Peak memory 201688 kb
Host smart-d6bd437b-9a49-4d7c-a98e-96292066aa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417179952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.417179952
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2656502106
Short name T537
Test name
Test status
Simulation time 5862468621 ps
CPU time 7.56 seconds
Started Jun 30 06:28:12 PM PDT 24
Finished Jun 30 06:28:23 PM PDT 24
Peak memory 201672 kb
Host smart-ac5b2795-c967-4d36-99dc-f4f80989a175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656502106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2656502106
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1445880941
Short name T661
Test name
Test status
Simulation time 343624317032 ps
CPU time 791.57 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:41:19 PM PDT 24
Peak memory 201844 kb
Host smart-3be9bd0b-5591-427c-9739-c43d2377556d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445880941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1445880941
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1624174471
Short name T396
Test name
Test status
Simulation time 309676641 ps
CPU time 0.93 seconds
Started Jun 30 06:28:05 PM PDT 24
Finished Jun 30 06:28:10 PM PDT 24
Peak memory 201572 kb
Host smart-f2914a62-6afe-4a16-81b5-baf7d298414e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624174471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1624174471
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1262273648
Short name T324
Test name
Test status
Simulation time 173503923940 ps
CPU time 363.3 seconds
Started Jun 30 06:28:05 PM PDT 24
Finished Jun 30 06:34:12 PM PDT 24
Peak memory 201896 kb
Host smart-c303c8e2-768c-496d-91b5-9f6575de1a0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262273648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1262273648
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2138592736
Short name T192
Test name
Test status
Simulation time 491812139397 ps
CPU time 299.5 seconds
Started Jun 30 06:28:01 PM PDT 24
Finished Jun 30 06:33:01 PM PDT 24
Peak memory 201840 kb
Host smart-fc450d57-dd63-463e-b4cf-abb560a866ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138592736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2138592736
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2940672347
Short name T572
Test name
Test status
Simulation time 164123669364 ps
CPU time 354.93 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:34:02 PM PDT 24
Peak memory 201876 kb
Host smart-bd139d78-d892-4739-a328-1a18843470f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940672347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2940672347
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.248638703
Short name T748
Test name
Test status
Simulation time 496061629729 ps
CPU time 255.68 seconds
Started Jun 30 06:27:50 PM PDT 24
Finished Jun 30 06:32:06 PM PDT 24
Peak memory 201876 kb
Host smart-73daa6a1-4dc5-46bd-a8ab-f7d3d311f039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248638703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.248638703
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.4050090212
Short name T434
Test name
Test status
Simulation time 327557008836 ps
CPU time 729.73 seconds
Started Jun 30 06:28:00 PM PDT 24
Finished Jun 30 06:40:10 PM PDT 24
Peak memory 201820 kb
Host smart-8f006e1a-95fb-4aac-99f2-0a47810af1b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050090212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.4050090212
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2364015175
Short name T491
Test name
Test status
Simulation time 170574166950 ps
CPU time 101.21 seconds
Started Jun 30 06:28:06 PM PDT 24
Finished Jun 30 06:29:50 PM PDT 24
Peak memory 201872 kb
Host smart-e4c92ab7-e8e2-4a7d-a6c5-4c802479792d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364015175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2364015175
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3358650160
Short name T744
Test name
Test status
Simulation time 596494634778 ps
CPU time 730.58 seconds
Started Jun 30 06:27:53 PM PDT 24
Finished Jun 30 06:40:04 PM PDT 24
Peak memory 201796 kb
Host smart-6439373f-3588-4241-9fa3-cacfef73b72a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358650160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3358650160
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1200516876
Short name T540
Test name
Test status
Simulation time 44248486457 ps
CPU time 54.99 seconds
Started Jun 30 06:28:02 PM PDT 24
Finished Jun 30 06:28:58 PM PDT 24
Peak memory 201636 kb
Host smart-e10d54c3-821c-49f0-b844-455ad5b7aad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200516876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1200516876
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3941036853
Short name T376
Test name
Test status
Simulation time 4293347075 ps
CPU time 6.4 seconds
Started Jun 30 06:28:09 PM PDT 24
Finished Jun 30 06:28:19 PM PDT 24
Peak memory 201652 kb
Host smart-addb2ab2-e345-4e81-af20-a73dd4e4b549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941036853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3941036853
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2086907983
Short name T570
Test name
Test status
Simulation time 5839442464 ps
CPU time 13.13 seconds
Started Jun 30 06:28:06 PM PDT 24
Finished Jun 30 06:28:23 PM PDT 24
Peak memory 201616 kb
Host smart-8e925f93-7d99-4660-b3f3-3d83bf64e639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086907983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2086907983
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.254265632
Short name T752
Test name
Test status
Simulation time 200707410494 ps
CPU time 76.76 seconds
Started Jun 30 06:28:10 PM PDT 24
Finished Jun 30 06:29:30 PM PDT 24
Peak memory 201868 kb
Host smart-bcffa5f7-bc48-45cc-8451-1b0b512c12c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254265632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
254265632
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1474620021
Short name T482
Test name
Test status
Simulation time 34097009870 ps
CPU time 42.01 seconds
Started Jun 30 06:28:01 PM PDT 24
Finished Jun 30 06:28:44 PM PDT 24
Peak memory 210236 kb
Host smart-c02fe81b-37f5-46df-b8e1-139692f3f421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474620021 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1474620021
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.4194928861
Short name T620
Test name
Test status
Simulation time 321958585 ps
CPU time 1.33 seconds
Started Jun 30 06:28:06 PM PDT 24
Finished Jun 30 06:28:11 PM PDT 24
Peak memory 201488 kb
Host smart-4c48c087-d398-48bd-84af-b11694e08f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194928861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.4194928861
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3614554714
Short name T649
Test name
Test status
Simulation time 356248998775 ps
CPU time 409.11 seconds
Started Jun 30 06:28:03 PM PDT 24
Finished Jun 30 06:34:55 PM PDT 24
Peak memory 201880 kb
Host smart-7e984d8a-0b7b-41a1-8dc2-764571883cde
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614554714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3614554714
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1059879008
Short name T523
Test name
Test status
Simulation time 167676928176 ps
CPU time 54.65 seconds
Started Jun 30 06:28:12 PM PDT 24
Finished Jun 30 06:29:11 PM PDT 24
Peak memory 201904 kb
Host smart-958f91a0-7644-4502-bae7-59a130794c07
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059879008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1059879008
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1864478483
Short name T643
Test name
Test status
Simulation time 163176167021 ps
CPU time 351.74 seconds
Started Jun 30 06:28:07 PM PDT 24
Finished Jun 30 06:34:03 PM PDT 24
Peak memory 201804 kb
Host smart-be0e20d0-43fd-44b4-b050-e8941df31495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864478483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1864478483
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1240550095
Short name T502
Test name
Test status
Simulation time 506271077199 ps
CPU time 256.32 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:32:24 PM PDT 24
Peak memory 201784 kb
Host smart-8370756c-c291-4c41-a793-ed3af4d5b383
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240550095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1240550095
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1146390306
Short name T339
Test name
Test status
Simulation time 170922614138 ps
CPU time 23.57 seconds
Started Jun 30 06:28:08 PM PDT 24
Finished Jun 30 06:28:35 PM PDT 24
Peak memory 201748 kb
Host smart-5befb664-3ff2-4880-8995-294561bf9a5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146390306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1146390306
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2144277102
Short name T772
Test name
Test status
Simulation time 583855205677 ps
CPU time 1399.25 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:51:27 PM PDT 24
Peak memory 201864 kb
Host smart-b9b07d23-c5a7-4c61-805c-1d5e1ce54bb3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144277102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2144277102
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.896941185
Short name T457
Test name
Test status
Simulation time 76813207822 ps
CPU time 388.75 seconds
Started Jun 30 06:28:01 PM PDT 24
Finished Jun 30 06:34:31 PM PDT 24
Peak memory 202200 kb
Host smart-c7eab182-39ff-4826-8d2c-6a81cb042781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896941185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.896941185
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2061730294
Short name T363
Test name
Test status
Simulation time 21590528028 ps
CPU time 47.32 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:29:05 PM PDT 24
Peak memory 201592 kb
Host smart-18889e07-a721-461b-9c48-55a894e4c826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061730294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2061730294
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2221931074
Short name T733
Test name
Test status
Simulation time 3623497658 ps
CPU time 4.88 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:28:12 PM PDT 24
Peak memory 201560 kb
Host smart-34216ba5-5bae-403d-b0e5-271e0b6cd477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221931074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2221931074
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3164858913
Short name T25
Test name
Test status
Simulation time 5921394363 ps
CPU time 13.98 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:28:22 PM PDT 24
Peak memory 201612 kb
Host smart-c6bf6009-9144-473b-9e83-399747eab252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164858913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3164858913
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2854602701
Short name T32
Test name
Test status
Simulation time 172022972399 ps
CPU time 99.59 seconds
Started Jun 30 06:28:08 PM PDT 24
Finished Jun 30 06:29:51 PM PDT 24
Peak memory 201732 kb
Host smart-43578665-3cc6-4b46-a083-c2cb2cf55008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854602701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2854602701
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1240874914
Short name T50
Test name
Test status
Simulation time 34563321016 ps
CPU time 97.16 seconds
Started Jun 30 06:28:09 PM PDT 24
Finished Jun 30 06:29:50 PM PDT 24
Peak memory 218708 kb
Host smart-900da4be-9eb8-4286-b26c-9dbc2d1a6eb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240874914 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1240874914
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.433320558
Short name T450
Test name
Test status
Simulation time 328057668 ps
CPU time 0.76 seconds
Started Jun 30 06:28:12 PM PDT 24
Finished Jun 30 06:28:17 PM PDT 24
Peak memory 201628 kb
Host smart-6447b133-0d5b-4c70-9533-5edf07d95f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433320558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.433320558
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2147380769
Short name T323
Test name
Test status
Simulation time 567648081982 ps
CPU time 610.25 seconds
Started Jun 30 06:28:08 PM PDT 24
Finished Jun 30 06:38:22 PM PDT 24
Peak memory 201808 kb
Host smart-0acc8cef-3c43-4e35-a1d7-b565877a8b51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147380769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2147380769
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1097952515
Short name T736
Test name
Test status
Simulation time 160187184010 ps
CPU time 351.79 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:33:59 PM PDT 24
Peak memory 201864 kb
Host smart-18f84142-ac0d-439b-9a2e-b077e592fba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097952515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1097952515
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1335846159
Short name T442
Test name
Test status
Simulation time 157953202680 ps
CPU time 113.05 seconds
Started Jun 30 06:28:08 PM PDT 24
Finished Jun 30 06:30:05 PM PDT 24
Peak memory 201852 kb
Host smart-76d2ce73-900b-402a-b23f-64c8b406f31b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335846159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1335846159
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3515690033
Short name T241
Test name
Test status
Simulation time 488958366124 ps
CPU time 1087.93 seconds
Started Jun 30 06:28:13 PM PDT 24
Finished Jun 30 06:46:25 PM PDT 24
Peak memory 201936 kb
Host smart-cb331741-9fab-427c-b3bc-f3ff035916a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515690033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3515690033
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1401077915
Short name T680
Test name
Test status
Simulation time 321442752671 ps
CPU time 696.04 seconds
Started Jun 30 06:28:05 PM PDT 24
Finished Jun 30 06:39:45 PM PDT 24
Peak memory 201844 kb
Host smart-d1d1b146-1427-44ce-94d4-ef69b4b050ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401077915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1401077915
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2143040407
Short name T252
Test name
Test status
Simulation time 554551416106 ps
CPU time 306.75 seconds
Started Jun 30 06:28:05 PM PDT 24
Finished Jun 30 06:33:15 PM PDT 24
Peak memory 201912 kb
Host smart-30c0f1db-49f7-4290-a9f8-a55142a5984f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143040407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2143040407
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3023632077
Short name T39
Test name
Test status
Simulation time 618700786270 ps
CPU time 1298.23 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:49:56 PM PDT 24
Peak memory 201856 kb
Host smart-485a05a1-7d8e-4963-b4c2-b66bbb58173c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023632077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3023632077
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1615609103
Short name T717
Test name
Test status
Simulation time 28711725378 ps
CPU time 66.81 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:29:25 PM PDT 24
Peak memory 201624 kb
Host smart-79752bc9-6479-4fd7-9d88-6552a03d2ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615609103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1615609103
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2549869465
Short name T552
Test name
Test status
Simulation time 3250356125 ps
CPU time 7.91 seconds
Started Jun 30 06:28:10 PM PDT 24
Finished Jun 30 06:28:22 PM PDT 24
Peak memory 201672 kb
Host smart-54f03cfd-081d-4e53-a1ba-6baf871d9543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549869465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2549869465
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2300591862
Short name T23
Test name
Test status
Simulation time 5646709733 ps
CPU time 3.72 seconds
Started Jun 30 06:28:02 PM PDT 24
Finished Jun 30 06:28:07 PM PDT 24
Peak memory 201532 kb
Host smart-766c724a-23ca-43f8-a4be-030f2395c933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300591862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2300591862
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1994411970
Short name T262
Test name
Test status
Simulation time 306110498646 ps
CPU time 50.24 seconds
Started Jun 30 06:28:03 PM PDT 24
Finished Jun 30 06:28:56 PM PDT 24
Peak memory 201924 kb
Host smart-3e2539a0-dc2f-4f71-96ea-1d885f67db10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994411970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1994411970
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2769387606
Short name T331
Test name
Test status
Simulation time 707515600684 ps
CPU time 990.06 seconds
Started Jun 30 06:28:11 PM PDT 24
Finished Jun 30 06:44:45 PM PDT 24
Peak memory 210536 kb
Host smart-6b9e5249-9d2f-4960-81f2-ecb46db340b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769387606 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2769387606
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1168844167
Short name T505
Test name
Test status
Simulation time 426510404 ps
CPU time 0.74 seconds
Started Jun 30 06:28:12 PM PDT 24
Finished Jun 30 06:28:17 PM PDT 24
Peak memory 201660 kb
Host smart-53d6495e-f85a-409b-894f-d620f4ef02f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168844167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1168844167
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3753650296
Short name T186
Test name
Test status
Simulation time 602727223668 ps
CPU time 133.22 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:30:31 PM PDT 24
Peak memory 201884 kb
Host smart-e83e6158-a138-4ef3-989e-7ce645e29aa5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753650296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3753650296
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.940598759
Short name T330
Test name
Test status
Simulation time 330786946166 ps
CPU time 116.62 seconds
Started Jun 30 06:28:12 PM PDT 24
Finished Jun 30 06:30:13 PM PDT 24
Peak memory 201876 kb
Host smart-04632c38-c2be-409f-ab60-544f79630d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940598759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.940598759
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.863141799
Short name T685
Test name
Test status
Simulation time 487011895828 ps
CPU time 648.55 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:38:56 PM PDT 24
Peak memory 201844 kb
Host smart-75321f28-3270-44c4-8f5f-5a7e74e429bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863141799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.863141799
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3312485722
Short name T577
Test name
Test status
Simulation time 164022510278 ps
CPU time 200.85 seconds
Started Jun 30 06:28:08 PM PDT 24
Finished Jun 30 06:31:33 PM PDT 24
Peak memory 201780 kb
Host smart-52e9fbc4-ed89-4ba9-9937-eb440a07d3d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312485722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3312485722
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2178956335
Short name T607
Test name
Test status
Simulation time 164609993151 ps
CPU time 247.03 seconds
Started Jun 30 06:28:12 PM PDT 24
Finished Jun 30 06:32:23 PM PDT 24
Peak memory 201944 kb
Host smart-c379670b-d120-4d61-9dee-ee8c02578914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178956335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2178956335
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1762628409
Short name T390
Test name
Test status
Simulation time 329149359803 ps
CPU time 750.04 seconds
Started Jun 30 06:28:02 PM PDT 24
Finished Jun 30 06:40:34 PM PDT 24
Peak memory 201828 kb
Host smart-d62abf07-ec42-4fdc-b058-12c64e0c9997
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762628409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1762628409
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2092512078
Short name T344
Test name
Test status
Simulation time 175830050207 ps
CPU time 169.15 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:31:07 PM PDT 24
Peak memory 201952 kb
Host smart-89d6ea5e-05f0-4ae7-8200-18fc06a53294
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092512078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2092512078
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1331901369
Short name T602
Test name
Test status
Simulation time 388759708483 ps
CPU time 213.25 seconds
Started Jun 30 06:28:09 PM PDT 24
Finished Jun 30 06:31:46 PM PDT 24
Peak memory 201852 kb
Host smart-0c7349fd-4369-4390-83de-1472b8595f72
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331901369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1331901369
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2700049348
Short name T353
Test name
Test status
Simulation time 96951854615 ps
CPU time 321.02 seconds
Started Jun 30 06:28:08 PM PDT 24
Finished Jun 30 06:33:33 PM PDT 24
Peak memory 202208 kb
Host smart-8090f417-671d-4d91-9519-2ea215374791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700049348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2700049348
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3833445675
Short name T729
Test name
Test status
Simulation time 28011638721 ps
CPU time 61.39 seconds
Started Jun 30 06:28:07 PM PDT 24
Finished Jun 30 06:29:12 PM PDT 24
Peak memory 201880 kb
Host smart-c7a4493f-cf7e-4996-94f7-60a84308d377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833445675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3833445675
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1497661919
Short name T401
Test name
Test status
Simulation time 4304375480 ps
CPU time 3.3 seconds
Started Jun 30 06:28:17 PM PDT 24
Finished Jun 30 06:28:23 PM PDT 24
Peak memory 201636 kb
Host smart-06d66645-e025-4b50-a981-fa96868c4a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497661919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1497661919
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.291150272
Short name T728
Test name
Test status
Simulation time 5869107049 ps
CPU time 14.69 seconds
Started Jun 30 06:28:08 PM PDT 24
Finished Jun 30 06:28:26 PM PDT 24
Peak memory 201676 kb
Host smart-e8898036-093f-471a-acbe-219c3de7d7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291150272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.291150272
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3501078396
Short name T428
Test name
Test status
Simulation time 209161658665 ps
CPU time 180.52 seconds
Started Jun 30 06:28:13 PM PDT 24
Finished Jun 30 06:31:17 PM PDT 24
Peak memory 201844 kb
Host smart-152f1487-b385-4880-8162-236b39a9b7f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501078396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3501078396
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2195517563
Short name T42
Test name
Test status
Simulation time 381406181 ps
CPU time 0.72 seconds
Started Jun 30 06:28:09 PM PDT 24
Finished Jun 30 06:28:13 PM PDT 24
Peak memory 201624 kb
Host smart-f50aab2d-ebba-4868-9a52-0ab17b0a3e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195517563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2195517563
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3765420091
Short name T291
Test name
Test status
Simulation time 325981134655 ps
CPU time 298.64 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:33:16 PM PDT 24
Peak memory 201812 kb
Host smart-c066b37d-38a4-497c-8240-57aeadda82ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765420091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3765420091
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.679760019
Short name T315
Test name
Test status
Simulation time 334383970827 ps
CPU time 226.87 seconds
Started Jun 30 06:28:12 PM PDT 24
Finished Jun 30 06:32:03 PM PDT 24
Peak memory 201904 kb
Host smart-fce2a0bf-cf9c-4f49-b606-ec78ad74389b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679760019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.679760019
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2290060195
Short name T219
Test name
Test status
Simulation time 496371352626 ps
CPU time 556.47 seconds
Started Jun 30 06:28:08 PM PDT 24
Finished Jun 30 06:37:28 PM PDT 24
Peak memory 201824 kb
Host smart-d134003e-e7b4-422d-bc5a-e0f628f9b0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290060195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2290060195
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1615739189
Short name T413
Test name
Test status
Simulation time 161677946011 ps
CPU time 93.04 seconds
Started Jun 30 06:28:15 PM PDT 24
Finished Jun 30 06:29:51 PM PDT 24
Peak memory 201812 kb
Host smart-4b79bc10-79e0-4d33-a49d-03bc14a4a1ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615739189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1615739189
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.445697877
Short name T477
Test name
Test status
Simulation time 486357907782 ps
CPU time 330.17 seconds
Started Jun 30 06:28:03 PM PDT 24
Finished Jun 30 06:33:36 PM PDT 24
Peak memory 201844 kb
Host smart-b975751c-8bce-4b6d-9e81-5cc0044fa039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445697877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.445697877
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.322349607
Short name T448
Test name
Test status
Simulation time 161183351765 ps
CPU time 79.48 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:29:27 PM PDT 24
Peak memory 201884 kb
Host smart-57d6d4cd-c0e5-49fe-ae9c-3de27c0d49fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=322349607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.322349607
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3543845156
Short name T392
Test name
Test status
Simulation time 210862197596 ps
CPU time 130.22 seconds
Started Jun 30 06:28:17 PM PDT 24
Finished Jun 30 06:30:30 PM PDT 24
Peak memory 201804 kb
Host smart-6a7c4498-77a6-40e4-817d-aa90048937b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543845156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3543845156
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1561119514
Short name T394
Test name
Test status
Simulation time 25692406466 ps
CPU time 31.12 seconds
Started Jun 30 06:28:12 PM PDT 24
Finished Jun 30 06:28:48 PM PDT 24
Peak memory 201676 kb
Host smart-4dabc140-b055-4db0-b124-248fb60eb01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561119514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1561119514
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.4140256241
Short name T646
Test name
Test status
Simulation time 4407263337 ps
CPU time 5.14 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:28:23 PM PDT 24
Peak memory 201652 kb
Host smart-e5b63eb9-76de-47b5-9a31-1395748a0b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140256241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.4140256241
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.507238691
Short name T422
Test name
Test status
Simulation time 5658737362 ps
CPU time 3.32 seconds
Started Jun 30 06:28:10 PM PDT 24
Finished Jun 30 06:28:17 PM PDT 24
Peak memory 201708 kb
Host smart-9d7c62a3-5848-4905-8f34-3b1d467a3ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507238691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.507238691
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1004690356
Short name T427
Test name
Test status
Simulation time 288265443 ps
CPU time 1.3 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:28:19 PM PDT 24
Peak memory 201628 kb
Host smart-97b4533c-e518-42df-8fd7-3e0f3a80e485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004690356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1004690356
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2613586635
Short name T639
Test name
Test status
Simulation time 180638652433 ps
CPU time 149.56 seconds
Started Jun 30 06:28:12 PM PDT 24
Finished Jun 30 06:30:46 PM PDT 24
Peak memory 201900 kb
Host smart-4aaf2629-c15a-4391-b567-821ba6870aa5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613586635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2613586635
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.203777518
Short name T178
Test name
Test status
Simulation time 330996733701 ps
CPU time 190.6 seconds
Started Jun 30 06:28:21 PM PDT 24
Finished Jun 30 06:31:32 PM PDT 24
Peak memory 201960 kb
Host smart-a8d4b9e3-d526-4fef-ad1b-ff09d851f7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203777518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.203777518
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2892180446
Short name T246
Test name
Test status
Simulation time 484283107048 ps
CPU time 1074.03 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:46:12 PM PDT 24
Peak memory 201952 kb
Host smart-6d89ccf1-4ec5-4421-afcd-1eff7711be45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892180446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2892180446
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.754589709
Short name T791
Test name
Test status
Simulation time 493366107968 ps
CPU time 564.17 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:37:42 PM PDT 24
Peak memory 201852 kb
Host smart-757d5d4e-d005-47d6-803f-05f93164b9f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=754589709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.754589709
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3339593116
Short name T128
Test name
Test status
Simulation time 486425660473 ps
CPU time 1076.31 seconds
Started Jun 30 06:28:03 PM PDT 24
Finished Jun 30 06:46:03 PM PDT 24
Peak memory 201872 kb
Host smart-c393a5bc-4ff7-49f6-808b-24e4a5b4bb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339593116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3339593116
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2857909925
Short name T627
Test name
Test status
Simulation time 492038757167 ps
CPU time 1116.3 seconds
Started Jun 30 06:28:10 PM PDT 24
Finished Jun 30 06:46:50 PM PDT 24
Peak memory 201832 kb
Host smart-c0356f4c-4993-4209-92d7-03d6ca0ae8e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857909925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2857909925
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3329180960
Short name T10
Test name
Test status
Simulation time 560870783988 ps
CPU time 1252.07 seconds
Started Jun 30 06:28:19 PM PDT 24
Finished Jun 30 06:49:13 PM PDT 24
Peak memory 201884 kb
Host smart-c8d63db0-d23f-49aa-9dcf-cc6b7b932a6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329180960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3329180960
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3959548704
Short name T447
Test name
Test status
Simulation time 410063757030 ps
CPU time 958.52 seconds
Started Jun 30 06:28:15 PM PDT 24
Finished Jun 30 06:44:17 PM PDT 24
Peak memory 201852 kb
Host smart-e8cfe3f0-6b70-4b86-a6a4-4035805a3383
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959548704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3959548704
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2116474615
Short name T200
Test name
Test status
Simulation time 87146390294 ps
CPU time 347.88 seconds
Started Jun 30 06:28:11 PM PDT 24
Finished Jun 30 06:34:02 PM PDT 24
Peak memory 202184 kb
Host smart-cafbe941-414c-4138-8138-8f98277e7aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116474615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2116474615
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2249350905
Short name T567
Test name
Test status
Simulation time 44023488805 ps
CPU time 29.54 seconds
Started Jun 30 06:28:11 PM PDT 24
Finished Jun 30 06:28:45 PM PDT 24
Peak memory 201668 kb
Host smart-63c5d246-00df-47db-8c51-8620e9a5dc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249350905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2249350905
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1730525052
Short name T557
Test name
Test status
Simulation time 4952934216 ps
CPU time 10.99 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:28:19 PM PDT 24
Peak memory 201680 kb
Host smart-1e686dd2-6b91-45a7-93b9-c5f4f053cbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730525052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1730525052
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.696734955
Short name T183
Test name
Test status
Simulation time 6049605720 ps
CPU time 2.13 seconds
Started Jun 30 06:28:09 PM PDT 24
Finished Jun 30 06:28:15 PM PDT 24
Peak memory 201680 kb
Host smart-cf7cea09-3e6e-4974-9eda-04a1a0fb51d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696734955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.696734955
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2420100250
Short name T555
Test name
Test status
Simulation time 295239944 ps
CPU time 0.93 seconds
Started Jun 30 06:27:28 PM PDT 24
Finished Jun 30 06:27:30 PM PDT 24
Peak memory 201612 kb
Host smart-33568caf-d2f7-4f32-95f2-4d4f6b8b15dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420100250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2420100250
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2193111924
Short name T645
Test name
Test status
Simulation time 329675570929 ps
CPU time 547.62 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:36:30 PM PDT 24
Peak memory 201880 kb
Host smart-b4dfbdb4-31af-4cde-8485-b7e8cd787469
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193111924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2193111924
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2733159992
Short name T41
Test name
Test status
Simulation time 207732744056 ps
CPU time 118.16 seconds
Started Jun 30 06:27:27 PM PDT 24
Finished Jun 30 06:29:26 PM PDT 24
Peak memory 201876 kb
Host smart-998340b8-5cb1-4cf2-8abc-7b2137885f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733159992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2733159992
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1072944188
Short name T193
Test name
Test status
Simulation time 500955307343 ps
CPU time 1121.77 seconds
Started Jun 30 06:27:27 PM PDT 24
Finished Jun 30 06:46:10 PM PDT 24
Peak memory 201892 kb
Host smart-5232bd84-6cb2-4e21-9cbc-92ceb5d18d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072944188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1072944188
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2305265623
Short name T365
Test name
Test status
Simulation time 328749810917 ps
CPU time 208.55 seconds
Started Jun 30 06:27:20 PM PDT 24
Finished Jun 30 06:30:53 PM PDT 24
Peak memory 201864 kb
Host smart-e2a7f16e-83fd-4bc5-8cc1-fd4c65ce3d4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305265623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2305265623
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.561821286
Short name T754
Test name
Test status
Simulation time 171582347318 ps
CPU time 94.53 seconds
Started Jun 30 06:27:26 PM PDT 24
Finished Jun 30 06:29:02 PM PDT 24
Peak memory 201960 kb
Host smart-e5c35dd6-4eda-4a3e-8dc7-f91ceee35319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561821286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.561821286
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2730102932
Short name T387
Test name
Test status
Simulation time 494018037737 ps
CPU time 194.32 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:30:36 PM PDT 24
Peak memory 201808 kb
Host smart-859ea8e0-800c-4f9b-b002-d3c3a30d0121
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730102932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2730102932
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3080699710
Short name T600
Test name
Test status
Simulation time 575050580513 ps
CPU time 307.75 seconds
Started Jun 30 06:27:33 PM PDT 24
Finished Jun 30 06:32:41 PM PDT 24
Peak memory 201848 kb
Host smart-3a9ce286-7ee8-4993-a83d-9e949e3a8d2f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080699710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3080699710
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1405978500
Short name T731
Test name
Test status
Simulation time 398651866540 ps
CPU time 874.02 seconds
Started Jun 30 06:27:26 PM PDT 24
Finished Jun 30 06:42:01 PM PDT 24
Peak memory 201844 kb
Host smart-43416205-bacd-46ad-8f97-5c5d257a11dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405978500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1405978500
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1798863972
Short name T201
Test name
Test status
Simulation time 131840128581 ps
CPU time 444.19 seconds
Started Jun 30 06:27:35 PM PDT 24
Finished Jun 30 06:35:00 PM PDT 24
Peak memory 202276 kb
Host smart-d996dfc6-78c5-453c-b0ea-bfb64819c46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798863972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1798863972
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3039317695
Short name T127
Test name
Test status
Simulation time 44837720095 ps
CPU time 96.91 seconds
Started Jun 30 06:27:30 PM PDT 24
Finished Jun 30 06:29:07 PM PDT 24
Peak memory 201588 kb
Host smart-997945ba-bf0a-4b76-bebb-1baadc1f8875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039317695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3039317695
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.294876705
Short name T536
Test name
Test status
Simulation time 4746614442 ps
CPU time 3.56 seconds
Started Jun 30 06:27:34 PM PDT 24
Finished Jun 30 06:27:38 PM PDT 24
Peak memory 201600 kb
Host smart-da6d3251-116f-44fb-a5cf-15fb3333099d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294876705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.294876705
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1625298052
Short name T408
Test name
Test status
Simulation time 5930274231 ps
CPU time 7.87 seconds
Started Jun 30 06:27:37 PM PDT 24
Finished Jun 30 06:27:45 PM PDT 24
Peak memory 201580 kb
Host smart-75fdd441-aaff-40bc-805a-754fc370bb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625298052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1625298052
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.479738244
Short name T522
Test name
Test status
Simulation time 31245240529 ps
CPU time 70.91 seconds
Started Jun 30 06:27:36 PM PDT 24
Finished Jun 30 06:28:47 PM PDT 24
Peak memory 201580 kb
Host smart-ce2306ae-327a-497c-a078-5c851cd43cc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479738244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.479738244
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3084473809
Short name T45
Test name
Test status
Simulation time 27665423380 ps
CPU time 15.96 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:27:39 PM PDT 24
Peak memory 210400 kb
Host smart-0dbdb1ce-1221-4a50-9406-dad90d245b54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084473809 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3084473809
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3419969428
Short name T438
Test name
Test status
Simulation time 405598398 ps
CPU time 1.48 seconds
Started Jun 30 06:28:17 PM PDT 24
Finished Jun 30 06:28:21 PM PDT 24
Peak memory 201628 kb
Host smart-e378b68b-da73-4a71-b031-ec00bd25a27b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419969428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3419969428
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3281126581
Short name T175
Test name
Test status
Simulation time 506427904692 ps
CPU time 166.78 seconds
Started Jun 30 06:28:17 PM PDT 24
Finished Jun 30 06:31:06 PM PDT 24
Peak memory 201740 kb
Host smart-894dc4b1-81e0-41d0-8778-3551b76ff227
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281126581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3281126581
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3891772402
Short name T229
Test name
Test status
Simulation time 162519271099 ps
CPU time 96.8 seconds
Started Jun 30 06:28:05 PM PDT 24
Finished Jun 30 06:29:46 PM PDT 24
Peak memory 201924 kb
Host smart-94e8134f-1faf-445d-8009-9e2fed2d4a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891772402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3891772402
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3486481534
Short name T562
Test name
Test status
Simulation time 325363592327 ps
CPU time 174.19 seconds
Started Jun 30 06:28:19 PM PDT 24
Finished Jun 30 06:31:14 PM PDT 24
Peak memory 201836 kb
Host smart-88fdc7cc-07e8-411b-b140-2646ad9640f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486481534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3486481534
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1760815493
Short name T443
Test name
Test status
Simulation time 165576101581 ps
CPU time 99.86 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:29:58 PM PDT 24
Peak memory 201960 kb
Host smart-f075ba5f-6aff-4c0a-8f8c-84f2db43ed5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760815493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1760815493
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3451872563
Short name T471
Test name
Test status
Simulation time 166627595269 ps
CPU time 366.51 seconds
Started Jun 30 06:28:08 PM PDT 24
Finished Jun 30 06:34:19 PM PDT 24
Peak memory 201804 kb
Host smart-00e48c57-0186-433d-b774-165568d5082e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451872563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3451872563
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1664699570
Short name T684
Test name
Test status
Simulation time 611050803327 ps
CPU time 1213.67 seconds
Started Jun 30 06:28:23 PM PDT 24
Finished Jun 30 06:48:38 PM PDT 24
Peak memory 201932 kb
Host smart-16710ef2-ca33-4c41-9af4-9a5e4c5ea4cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664699570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1664699570
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.859230077
Short name T695
Test name
Test status
Simulation time 138534981774 ps
CPU time 470.39 seconds
Started Jun 30 06:28:14 PM PDT 24
Finished Jun 30 06:36:08 PM PDT 24
Peak memory 202188 kb
Host smart-1facb4fb-bf78-4c9f-ace1-4c61762ddcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859230077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.859230077
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1210174179
Short name T584
Test name
Test status
Simulation time 28140112525 ps
CPU time 16.04 seconds
Started Jun 30 06:28:16 PM PDT 24
Finished Jun 30 06:28:35 PM PDT 24
Peak memory 201692 kb
Host smart-26186b5d-4a71-4fb9-b208-7df0acaaec33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210174179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1210174179
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3504970893
Short name T423
Test name
Test status
Simulation time 4731611504 ps
CPU time 12.08 seconds
Started Jun 30 06:28:12 PM PDT 24
Finished Jun 30 06:28:28 PM PDT 24
Peak memory 201664 kb
Host smart-1e3cf467-73f1-4191-b0d9-4f7bd837b83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504970893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3504970893
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3925569493
Short name T106
Test name
Test status
Simulation time 5768382855 ps
CPU time 3.78 seconds
Started Jun 30 06:28:05 PM PDT 24
Finished Jun 30 06:28:12 PM PDT 24
Peak memory 201632 kb
Host smart-779b8362-aa68-469b-ba1b-682e3b246959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925569493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3925569493
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1242649412
Short name T256
Test name
Test status
Simulation time 367664579392 ps
CPU time 837.98 seconds
Started Jun 30 06:28:15 PM PDT 24
Finished Jun 30 06:42:16 PM PDT 24
Peak memory 201928 kb
Host smart-cd278efc-98c2-4fd4-8370-d4e21954427e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242649412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1242649412
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.697267310
Short name T630
Test name
Test status
Simulation time 465520290 ps
CPU time 1.64 seconds
Started Jun 30 06:28:24 PM PDT 24
Finished Jun 30 06:28:26 PM PDT 24
Peak memory 201568 kb
Host smart-b181a49d-8895-44f1-bc4b-1bdfd9ee53fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697267310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.697267310
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2366767048
Short name T490
Test name
Test status
Simulation time 333547311494 ps
CPU time 51.1 seconds
Started Jun 30 06:28:20 PM PDT 24
Finished Jun 30 06:29:12 PM PDT 24
Peak memory 201816 kb
Host smart-b30db22f-1f15-4b82-8bf2-092a34422bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366767048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2366767048
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.136635100
Short name T494
Test name
Test status
Simulation time 324702621836 ps
CPU time 603.47 seconds
Started Jun 30 06:28:16 PM PDT 24
Finished Jun 30 06:38:23 PM PDT 24
Peak memory 201836 kb
Host smart-c57d637f-5bd1-4d4a-b093-5331ac8c8cdd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=136635100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.136635100
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2357993484
Short name T459
Test name
Test status
Simulation time 160828039099 ps
CPU time 93.65 seconds
Started Jun 30 06:28:18 PM PDT 24
Finished Jun 30 06:29:53 PM PDT 24
Peak memory 201980 kb
Host smart-868921c4-ff7c-41f2-b489-1ff0606d2692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357993484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2357993484
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3096312079
Short name T113
Test name
Test status
Simulation time 331877726008 ps
CPU time 777.69 seconds
Started Jun 30 06:28:16 PM PDT 24
Finished Jun 30 06:41:17 PM PDT 24
Peak memory 201844 kb
Host smart-986409d8-b9c3-43b7-aa44-bd431098e16a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096312079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3096312079
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1226856155
Short name T215
Test name
Test status
Simulation time 175699673538 ps
CPU time 288.43 seconds
Started Jun 30 06:28:21 PM PDT 24
Finished Jun 30 06:33:10 PM PDT 24
Peak memory 201916 kb
Host smart-1208feb6-d306-462e-aa4e-17dbc449e428
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226856155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1226856155
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3383885629
Short name T519
Test name
Test status
Simulation time 600249677977 ps
CPU time 313.11 seconds
Started Jun 30 06:28:21 PM PDT 24
Finished Jun 30 06:33:35 PM PDT 24
Peak memory 201788 kb
Host smart-ab29d934-54df-4163-85a6-eee8caab6b6c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383885629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3383885629
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1689670141
Short name T726
Test name
Test status
Simulation time 131537439443 ps
CPU time 449.41 seconds
Started Jun 30 06:28:25 PM PDT 24
Finished Jun 30 06:35:55 PM PDT 24
Peak memory 202192 kb
Host smart-8d8a90cd-8125-42eb-aff0-7db7cbf67233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689670141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1689670141
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1656621113
Short name T386
Test name
Test status
Simulation time 23207834222 ps
CPU time 14.14 seconds
Started Jun 30 06:28:22 PM PDT 24
Finished Jun 30 06:28:36 PM PDT 24
Peak memory 201680 kb
Host smart-5f4b0815-1676-4d42-b1bf-f186c7de0c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656621113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1656621113
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.147092684
Short name T499
Test name
Test status
Simulation time 2869049014 ps
CPU time 7.56 seconds
Started Jun 30 06:28:21 PM PDT 24
Finished Jun 30 06:28:30 PM PDT 24
Peak memory 201668 kb
Host smart-072d4c6e-eca7-4e84-83c8-8e180994b1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147092684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.147092684
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3009626010
Short name T513
Test name
Test status
Simulation time 5646994297 ps
CPU time 2.89 seconds
Started Jun 30 06:28:21 PM PDT 24
Finished Jun 30 06:28:24 PM PDT 24
Peak memory 201644 kb
Host smart-35cf01db-7b4f-40b0-a490-4a272a9aff71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009626010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3009626010
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3083636110
Short name T761
Test name
Test status
Simulation time 211823404652 ps
CPU time 211.01 seconds
Started Jun 30 06:28:27 PM PDT 24
Finished Jun 30 06:31:59 PM PDT 24
Peak memory 201740 kb
Host smart-f4e8137f-eb0d-486c-8d69-5a257a0275c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083636110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3083636110
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.331712653
Short name T16
Test name
Test status
Simulation time 64857379719 ps
CPU time 239.22 seconds
Started Jun 30 06:28:31 PM PDT 24
Finished Jun 30 06:32:31 PM PDT 24
Peak memory 210452 kb
Host smart-4eb292fe-c8d7-456f-a9fe-88701210133e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331712653 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.331712653
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3431876718
Short name T435
Test name
Test status
Simulation time 516911966 ps
CPU time 1.79 seconds
Started Jun 30 06:28:39 PM PDT 24
Finished Jun 30 06:28:41 PM PDT 24
Peak memory 201580 kb
Host smart-c5a76c7e-cbce-4c6d-9520-ab68b383bd54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431876718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3431876718
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.915760569
Short name T764
Test name
Test status
Simulation time 189564024881 ps
CPU time 393.97 seconds
Started Jun 30 06:28:39 PM PDT 24
Finished Jun 30 06:35:13 PM PDT 24
Peak memory 201880 kb
Host smart-a22f86da-5bec-425a-b06a-a9536b597288
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915760569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.915760569
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.225225393
Short name T751
Test name
Test status
Simulation time 163535786763 ps
CPU time 187.55 seconds
Started Jun 30 06:28:38 PM PDT 24
Finished Jun 30 06:31:46 PM PDT 24
Peak memory 201888 kb
Host smart-caea3d80-231c-4fc1-83b6-4800e4bda80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225225393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.225225393
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.600500474
Short name T329
Test name
Test status
Simulation time 324006145753 ps
CPU time 374.06 seconds
Started Jun 30 06:28:37 PM PDT 24
Finished Jun 30 06:34:51 PM PDT 24
Peak memory 201872 kb
Host smart-ecf9554c-043e-4c06-b6f0-52265fecdb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600500474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.600500474
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1424449762
Short name T653
Test name
Test status
Simulation time 492727169233 ps
CPU time 314.19 seconds
Started Jun 30 06:28:31 PM PDT 24
Finished Jun 30 06:33:45 PM PDT 24
Peak memory 201860 kb
Host smart-14810892-d6f0-4777-93c5-49063faaebf9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424449762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1424449762
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1761521906
Short name T170
Test name
Test status
Simulation time 331132699473 ps
CPU time 79.43 seconds
Started Jun 30 06:28:33 PM PDT 24
Finished Jun 30 06:29:52 PM PDT 24
Peak memory 201888 kb
Host smart-0e8e1a0d-12cd-419d-bc6e-b0cd7f98c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761521906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1761521906
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.735273418
Short name T746
Test name
Test status
Simulation time 168353576089 ps
CPU time 198.03 seconds
Started Jun 30 06:28:32 PM PDT 24
Finished Jun 30 06:31:50 PM PDT 24
Peak memory 201868 kb
Host smart-884a4117-576e-4d7a-a8d5-c2fc4e865b3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=735273418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.735273418
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1818561664
Short name T114
Test name
Test status
Simulation time 185676127392 ps
CPU time 98.74 seconds
Started Jun 30 06:28:32 PM PDT 24
Finished Jun 30 06:30:11 PM PDT 24
Peak memory 201888 kb
Host smart-1d0b6e80-5c88-427d-b058-9e2a5f30f9eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818561664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1818561664
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2963674813
Short name T384
Test name
Test status
Simulation time 410456557851 ps
CPU time 250.31 seconds
Started Jun 30 06:28:36 PM PDT 24
Finished Jun 30 06:32:47 PM PDT 24
Peak memory 201860 kb
Host smart-b60b5520-66a1-4d19-91d5-9e2f8ef5bfb8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963674813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2963674813
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2321956940
Short name T198
Test name
Test status
Simulation time 108517333779 ps
CPU time 409.63 seconds
Started Jun 30 06:28:37 PM PDT 24
Finished Jun 30 06:35:27 PM PDT 24
Peak memory 202076 kb
Host smart-3b5264da-a83f-42a7-93c0-8f1309e1f0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321956940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2321956940
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2890131843
Short name T503
Test name
Test status
Simulation time 28201027455 ps
CPU time 65.23 seconds
Started Jun 30 06:28:37 PM PDT 24
Finished Jun 30 06:29:43 PM PDT 24
Peak memory 201692 kb
Host smart-11e87a4b-b91a-4dd5-9659-e1504d0dfa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890131843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2890131843
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3825721310
Short name T617
Test name
Test status
Simulation time 5166552577 ps
CPU time 12.82 seconds
Started Jun 30 06:28:36 PM PDT 24
Finished Jun 30 06:28:49 PM PDT 24
Peak memory 201620 kb
Host smart-d092ef6e-24b9-4f6b-a87b-3a07c7f458e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825721310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3825721310
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.4173319488
Short name T539
Test name
Test status
Simulation time 5866315884 ps
CPU time 2.29 seconds
Started Jun 30 06:28:26 PM PDT 24
Finished Jun 30 06:28:28 PM PDT 24
Peak memory 201676 kb
Host smart-02309961-a6fc-4925-9d08-41a7bde88f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173319488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.4173319488
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3421518786
Short name T299
Test name
Test status
Simulation time 363221601772 ps
CPU time 426.32 seconds
Started Jun 30 06:28:36 PM PDT 24
Finished Jun 30 06:35:43 PM PDT 24
Peak memory 201860 kb
Host smart-3c33bc6e-3777-4305-9800-02d8b9162b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421518786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3421518786
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3952735315
Short name T37
Test name
Test status
Simulation time 343735232 ps
CPU time 0.82 seconds
Started Jun 30 06:28:42 PM PDT 24
Finished Jun 30 06:28:43 PM PDT 24
Peak memory 201632 kb
Host smart-b1353efc-8819-46bb-bcd9-21494bb43c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952735315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3952735315
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3033308441
Short name T343
Test name
Test status
Simulation time 511963594227 ps
CPU time 1116.75 seconds
Started Jun 30 06:28:41 PM PDT 24
Finished Jun 30 06:47:19 PM PDT 24
Peak memory 201760 kb
Host smart-4d436b3d-24b1-4531-b367-5fd5003ea724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033308441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3033308441
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2365608347
Short name T416
Test name
Test status
Simulation time 328594955105 ps
CPU time 646.19 seconds
Started Jun 30 06:28:44 PM PDT 24
Finished Jun 30 06:39:31 PM PDT 24
Peak memory 201844 kb
Host smart-a485aef4-7854-4c0e-a611-9840833e0fd9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365608347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2365608347
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.725899936
Short name T633
Test name
Test status
Simulation time 317977731243 ps
CPU time 692.68 seconds
Started Jun 30 06:28:40 PM PDT 24
Finished Jun 30 06:40:13 PM PDT 24
Peak memory 201948 kb
Host smart-09bd5160-bba8-41ac-9f17-440f566a4998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725899936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.725899936
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1773428374
Short name T678
Test name
Test status
Simulation time 479234984260 ps
CPU time 151.78 seconds
Started Jun 30 06:28:44 PM PDT 24
Finished Jun 30 06:31:17 PM PDT 24
Peak memory 201860 kb
Host smart-dd9e1f23-df17-46a1-bb96-c926b8a2bf9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773428374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1773428374
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.134031610
Short name T248
Test name
Test status
Simulation time 179301864436 ps
CPU time 100.11 seconds
Started Jun 30 06:28:44 PM PDT 24
Finished Jun 30 06:30:25 PM PDT 24
Peak memory 201896 kb
Host smart-339faa57-8f52-439e-bdc7-fd365fa8e3e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134031610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.134031610
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3661910774
Short name T611
Test name
Test status
Simulation time 405467782824 ps
CPU time 871.12 seconds
Started Jun 30 06:28:45 PM PDT 24
Finished Jun 30 06:43:17 PM PDT 24
Peak memory 202164 kb
Host smart-eb875385-5c7f-4822-92fd-cfdb94ec37c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661910774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3661910774
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3258611864
Short name T762
Test name
Test status
Simulation time 105849721237 ps
CPU time 539.5 seconds
Started Jun 30 06:28:46 PM PDT 24
Finished Jun 30 06:37:47 PM PDT 24
Peak memory 202152 kb
Host smart-b4b9505b-6001-4e1d-99f9-6e3cc92e70a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258611864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3258611864
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2799408997
Short name T652
Test name
Test status
Simulation time 35435455293 ps
CPU time 80.57 seconds
Started Jun 30 06:28:44 PM PDT 24
Finished Jun 30 06:30:06 PM PDT 24
Peak memory 201672 kb
Host smart-73b89102-8094-4c94-ac92-2bcb9c34f3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799408997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2799408997
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.193827552
Short name T719
Test name
Test status
Simulation time 4753404763 ps
CPU time 3.77 seconds
Started Jun 30 06:28:46 PM PDT 24
Finished Jun 30 06:28:51 PM PDT 24
Peak memory 201640 kb
Host smart-972e1ede-1a5b-4e68-b9cf-6f51da601666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193827552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.193827552
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2604921473
Short name T637
Test name
Test status
Simulation time 5649842933 ps
CPU time 3.56 seconds
Started Jun 30 06:28:38 PM PDT 24
Finished Jun 30 06:28:42 PM PDT 24
Peak memory 201668 kb
Host smart-e0fd1b4a-afa0-41b0-a0a6-85165e65cd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604921473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2604921473
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3834315456
Short name T571
Test name
Test status
Simulation time 123562788455 ps
CPU time 402.82 seconds
Started Jun 30 06:28:44 PM PDT 24
Finished Jun 30 06:35:28 PM PDT 24
Peak memory 202172 kb
Host smart-27a7b8e7-01c1-45bf-879d-f755c268a9a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834315456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3834315456
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.856045674
Short name T22
Test name
Test status
Simulation time 69171025755 ps
CPU time 133.96 seconds
Started Jun 30 06:28:40 PM PDT 24
Finished Jun 30 06:30:54 PM PDT 24
Peak memory 210564 kb
Host smart-9d1c1f1a-5003-41cc-b323-36b0218b0146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856045674 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.856045674
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3736317995
Short name T797
Test name
Test status
Simulation time 342202429 ps
CPU time 1.37 seconds
Started Jun 30 06:28:57 PM PDT 24
Finished Jun 30 06:29:00 PM PDT 24
Peak memory 201660 kb
Host smart-1ef9a0cd-309c-4295-b4b8-71ba9fdc96b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736317995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3736317995
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.567689211
Short name T156
Test name
Test status
Simulation time 165123652667 ps
CPU time 396.66 seconds
Started Jun 30 06:28:43 PM PDT 24
Finished Jun 30 06:35:21 PM PDT 24
Peak memory 201860 kb
Host smart-bc78a683-82db-426d-90cd-ec619f2a438f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567689211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.567689211
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1414701614
Short name T268
Test name
Test status
Simulation time 323456090973 ps
CPU time 188.18 seconds
Started Jun 30 06:28:50 PM PDT 24
Finished Jun 30 06:31:59 PM PDT 24
Peak memory 201948 kb
Host smart-5377468d-c80a-44a2-b121-f21da55ff0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414701614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1414701614
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2319792915
Short name T789
Test name
Test status
Simulation time 330498355702 ps
CPU time 695.66 seconds
Started Jun 30 06:28:48 PM PDT 24
Finished Jun 30 06:40:24 PM PDT 24
Peak memory 201780 kb
Host smart-1869a21e-480f-4d8d-bcf2-3a5d8ba4dcfa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319792915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2319792915
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3288707972
Short name T165
Test name
Test status
Simulation time 492700328994 ps
CPU time 226.26 seconds
Started Jun 30 06:28:45 PM PDT 24
Finished Jun 30 06:32:32 PM PDT 24
Peak memory 201952 kb
Host smart-f10e6014-83b7-48e2-9fad-359bd0b2f17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288707972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3288707972
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2332577989
Short name T381
Test name
Test status
Simulation time 496187083205 ps
CPU time 547.15 seconds
Started Jun 30 06:28:45 PM PDT 24
Finished Jun 30 06:37:53 PM PDT 24
Peak memory 202104 kb
Host smart-d327c839-0c5f-4226-9a13-1ca6bb09e577
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332577989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2332577989
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3877973580
Short name T294
Test name
Test status
Simulation time 386259379692 ps
CPU time 425.08 seconds
Started Jun 30 06:28:42 PM PDT 24
Finished Jun 30 06:35:48 PM PDT 24
Peak memory 201844 kb
Host smart-58a3806b-8468-44ce-a5dd-694714c297b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877973580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3877973580
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3872300781
Short name T364
Test name
Test status
Simulation time 206828212385 ps
CPU time 453.87 seconds
Started Jun 30 06:28:52 PM PDT 24
Finished Jun 30 06:36:27 PM PDT 24
Peak memory 201848 kb
Host smart-c8fd9ed6-53d8-460a-9f07-5621b38ca25d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872300781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3872300781
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3414648216
Short name T621
Test name
Test status
Simulation time 108038724330 ps
CPU time 314.02 seconds
Started Jun 30 06:28:51 PM PDT 24
Finished Jun 30 06:34:06 PM PDT 24
Peak memory 202200 kb
Host smart-4f1f13ba-cae0-4ffa-b4fd-7fdf35c23e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414648216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3414648216
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2836090341
Short name T634
Test name
Test status
Simulation time 43244764271 ps
CPU time 96.12 seconds
Started Jun 30 06:28:49 PM PDT 24
Finished Jun 30 06:30:26 PM PDT 24
Peak memory 201620 kb
Host smart-af878b50-9079-4327-a707-dac9e0e354c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836090341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2836090341
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.353447122
Short name T755
Test name
Test status
Simulation time 4212732938 ps
CPU time 3.15 seconds
Started Jun 30 06:28:45 PM PDT 24
Finished Jun 30 06:28:50 PM PDT 24
Peak memory 201684 kb
Host smart-f7bf44df-b595-4cc7-9a5b-b0155a695d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353447122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.353447122
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.205494968
Short name T497
Test name
Test status
Simulation time 6011231372 ps
CPU time 13.88 seconds
Started Jun 30 06:28:41 PM PDT 24
Finished Jun 30 06:28:56 PM PDT 24
Peak memory 201664 kb
Host smart-b5d28dd5-b2ee-40d2-be64-caa1d6325e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205494968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.205494968
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1064351380
Short name T120
Test name
Test status
Simulation time 232206539367 ps
CPU time 41.43 seconds
Started Jun 30 06:28:55 PM PDT 24
Finished Jun 30 06:29:38 PM PDT 24
Peak memory 201920 kb
Host smart-b0cb654f-e350-4546-a210-41a3f53b75c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064351380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1064351380
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2148744705
Short name T322
Test name
Test status
Simulation time 265408528787 ps
CPU time 106.21 seconds
Started Jun 30 06:28:50 PM PDT 24
Finished Jun 30 06:30:37 PM PDT 24
Peak memory 210504 kb
Host smart-5e5a838b-6815-4b8e-b195-deeaee6dd28a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148744705 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2148744705
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2454567268
Short name T589
Test name
Test status
Simulation time 389077994 ps
CPU time 0.86 seconds
Started Jun 30 06:28:55 PM PDT 24
Finished Jun 30 06:28:58 PM PDT 24
Peak memory 201632 kb
Host smart-209c6fb5-d113-4e72-b26a-37df72429da2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454567268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2454567268
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.961825401
Short name T282
Test name
Test status
Simulation time 346648556058 ps
CPU time 196.84 seconds
Started Jun 30 06:28:52 PM PDT 24
Finished Jun 30 06:32:10 PM PDT 24
Peak memory 201820 kb
Host smart-b8ed5b09-0f10-4dcb-a3cc-9734c1b09801
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961825401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.961825401
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2254040398
Short name T304
Test name
Test status
Simulation time 169071236330 ps
CPU time 370.35 seconds
Started Jun 30 06:28:49 PM PDT 24
Finished Jun 30 06:35:00 PM PDT 24
Peak memory 201876 kb
Host smart-431ca91c-f3c6-43f5-a187-85986154f1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254040398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2254040398
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3371812632
Short name T116
Test name
Test status
Simulation time 168670325872 ps
CPU time 356.05 seconds
Started Jun 30 06:29:01 PM PDT 24
Finished Jun 30 06:34:58 PM PDT 24
Peak memory 201880 kb
Host smart-0b0b8d4d-63a6-4bab-bb1e-eef5d469177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371812632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3371812632
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.390333248
Short name T101
Test name
Test status
Simulation time 492680298533 ps
CPU time 235.15 seconds
Started Jun 30 06:28:51 PM PDT 24
Finished Jun 30 06:32:47 PM PDT 24
Peak memory 201836 kb
Host smart-d94f6c54-e7a3-4206-9278-9b22b38ca18a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=390333248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.390333248
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1821474150
Short name T783
Test name
Test status
Simulation time 328594638304 ps
CPU time 191.72 seconds
Started Jun 30 06:28:56 PM PDT 24
Finished Jun 30 06:32:09 PM PDT 24
Peak memory 201944 kb
Host smart-422b998b-0814-45eb-8c7e-66a9e28bbd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821474150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1821474150
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2622965935
Short name T391
Test name
Test status
Simulation time 322214295132 ps
CPU time 626 seconds
Started Jun 30 06:28:51 PM PDT 24
Finished Jun 30 06:39:18 PM PDT 24
Peak memory 201824 kb
Host smart-3ec466cc-6817-4f66-bf03-14504e6fba48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622965935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2622965935
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3461543687
Short name T190
Test name
Test status
Simulation time 524565144841 ps
CPU time 1271.75 seconds
Started Jun 30 06:28:52 PM PDT 24
Finished Jun 30 06:50:05 PM PDT 24
Peak memory 201908 kb
Host smart-25234e3f-f311-4f76-b977-b6908956b565
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461543687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3461543687
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3673742266
Short name T682
Test name
Test status
Simulation time 405788432404 ps
CPU time 922.25 seconds
Started Jun 30 06:28:52 PM PDT 24
Finished Jun 30 06:44:16 PM PDT 24
Peak memory 201864 kb
Host smart-cd8755de-5625-4dd3-a515-888b276bd51f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673742266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3673742266
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1494747109
Short name T595
Test name
Test status
Simulation time 105880416586 ps
CPU time 476.76 seconds
Started Jun 30 06:28:52 PM PDT 24
Finished Jun 30 06:36:50 PM PDT 24
Peak memory 202148 kb
Host smart-d4b363d9-8238-4c6c-99d6-0ddbf4b66fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494747109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1494747109
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1331176871
Short name T437
Test name
Test status
Simulation time 36575765187 ps
CPU time 42.61 seconds
Started Jun 30 06:29:06 PM PDT 24
Finished Jun 30 06:29:49 PM PDT 24
Peak memory 201656 kb
Host smart-ae647639-44dd-424f-ab61-7b272b4dac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331176871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1331176871
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1922963026
Short name T463
Test name
Test status
Simulation time 2794075277 ps
CPU time 7 seconds
Started Jun 30 06:28:49 PM PDT 24
Finished Jun 30 06:28:56 PM PDT 24
Peak memory 201696 kb
Host smart-1e0a0651-0ff7-495f-82b1-da3e747ff101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922963026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1922963026
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.801519071
Short name T722
Test name
Test status
Simulation time 5652266259 ps
CPU time 3.54 seconds
Started Jun 30 06:28:51 PM PDT 24
Finished Jun 30 06:28:55 PM PDT 24
Peak memory 201552 kb
Host smart-d1a66e1a-e86a-4660-bc12-4d6f6250b065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801519071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.801519071
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3078335408
Short name T125
Test name
Test status
Simulation time 303756977 ps
CPU time 0.85 seconds
Started Jun 30 06:29:02 PM PDT 24
Finished Jun 30 06:29:04 PM PDT 24
Peak memory 201564 kb
Host smart-bba48f21-982d-4d09-8f33-1b53f64cfec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078335408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3078335408
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1827014262
Short name T696
Test name
Test status
Simulation time 325921355235 ps
CPU time 800.59 seconds
Started Jun 30 06:28:50 PM PDT 24
Finished Jun 30 06:42:12 PM PDT 24
Peak memory 201932 kb
Host smart-2df05e8a-7006-409e-9689-5cbf83cee860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827014262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1827014262
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2425666451
Short name T672
Test name
Test status
Simulation time 160881270525 ps
CPU time 95.76 seconds
Started Jun 30 06:28:52 PM PDT 24
Finished Jun 30 06:30:29 PM PDT 24
Peak memory 201804 kb
Host smart-0f62ab47-1ea9-4c30-8ae5-fab77bb8531a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425666451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2425666451
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.537304621
Short name T760
Test name
Test status
Simulation time 325877162061 ps
CPU time 735.56 seconds
Started Jun 30 06:28:53 PM PDT 24
Finished Jun 30 06:41:10 PM PDT 24
Peak memory 201876 kb
Host smart-f7b29b41-d8e4-4c44-8308-d7c721f50dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537304621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.537304621
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.178334751
Short name T592
Test name
Test status
Simulation time 502795962580 ps
CPU time 201.65 seconds
Started Jun 30 06:28:52 PM PDT 24
Finished Jun 30 06:32:15 PM PDT 24
Peak memory 201868 kb
Host smart-e6b88392-dadd-4b3d-8827-b9cbfbd90a98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=178334751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.178334751
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2475307
Short name T295
Test name
Test status
Simulation time 192498868943 ps
CPU time 219.73 seconds
Started Jun 30 06:28:49 PM PDT 24
Finished Jun 30 06:32:29 PM PDT 24
Peak memory 201864 kb
Host smart-95047ffa-053a-4a16-a4ca-3ad194f83aa4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wa
keup.2475307
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1463301632
Short name T421
Test name
Test status
Simulation time 608224659710 ps
CPU time 680.06 seconds
Started Jun 30 06:28:48 PM PDT 24
Finished Jun 30 06:40:08 PM PDT 24
Peak memory 201844 kb
Host smart-de90ec65-cd46-4cfa-bf9f-fcae8506e0a7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463301632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1463301632
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1806298680
Short name T788
Test name
Test status
Simulation time 28918465377 ps
CPU time 17.31 seconds
Started Jun 30 06:29:02 PM PDT 24
Finished Jun 30 06:29:20 PM PDT 24
Peak memory 201664 kb
Host smart-8ebd7e8a-6d86-4ad5-a5d6-9aa4b1c15a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806298680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1806298680
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.854785737
Short name T601
Test name
Test status
Simulation time 4332692705 ps
CPU time 10.47 seconds
Started Jun 30 06:28:57 PM PDT 24
Finished Jun 30 06:29:09 PM PDT 24
Peak memory 201716 kb
Host smart-3293d46e-0581-4e05-b8e2-4a9480b55bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854785737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.854785737
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2804243839
Short name T716
Test name
Test status
Simulation time 5957395334 ps
CPU time 14.77 seconds
Started Jun 30 06:28:51 PM PDT 24
Finished Jun 30 06:29:06 PM PDT 24
Peak memory 201676 kb
Host smart-fc641390-2b22-41f5-a3ba-475d4cffa59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804243839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2804243839
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1623381582
Short name T212
Test name
Test status
Simulation time 310815177906 ps
CPU time 1006.5 seconds
Started Jun 30 06:28:57 PM PDT 24
Finished Jun 30 06:45:45 PM PDT 24
Peak memory 210416 kb
Host smart-e0b654eb-ef44-42fd-a634-d0932218f16d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623381582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1623381582
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2110322471
Short name T97
Test name
Test status
Simulation time 463588995 ps
CPU time 1.66 seconds
Started Jun 30 06:28:54 PM PDT 24
Finished Jun 30 06:28:57 PM PDT 24
Peak memory 201632 kb
Host smart-12279b5c-5aba-471d-aaca-2506cd998d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110322471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2110322471
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.369754613
Short name T167
Test name
Test status
Simulation time 524735747451 ps
CPU time 325.46 seconds
Started Jun 30 06:29:03 PM PDT 24
Finished Jun 30 06:34:30 PM PDT 24
Peak memory 201832 kb
Host smart-74a12d56-d604-4538-bfa8-423a64d22597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369754613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.369754613
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.759842994
Short name T714
Test name
Test status
Simulation time 486436279977 ps
CPU time 753 seconds
Started Jun 30 06:29:04 PM PDT 24
Finished Jun 30 06:41:38 PM PDT 24
Peak memory 201904 kb
Host smart-90654917-ac40-44be-91ac-948b4c82a882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759842994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.759842994
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2369578271
Short name T734
Test name
Test status
Simulation time 484670118840 ps
CPU time 1154.01 seconds
Started Jun 30 06:29:03 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 201780 kb
Host smart-052b697e-f55d-4374-be22-8536787035dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369578271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2369578271
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3829412012
Short name T40
Test name
Test status
Simulation time 323343490068 ps
CPU time 85.16 seconds
Started Jun 30 06:29:04 PM PDT 24
Finished Jun 30 06:30:30 PM PDT 24
Peak memory 201940 kb
Host smart-e116ecd5-0e16-4447-b723-c904299c2920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829412012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3829412012
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1227153884
Short name T782
Test name
Test status
Simulation time 500088587327 ps
CPU time 461.65 seconds
Started Jun 30 06:28:57 PM PDT 24
Finished Jun 30 06:36:40 PM PDT 24
Peak memory 201804 kb
Host smart-500b50c2-a31b-4226-9c5a-de20b32b4842
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227153884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1227153884
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3358925723
Short name T737
Test name
Test status
Simulation time 538128167025 ps
CPU time 334.02 seconds
Started Jun 30 06:28:59 PM PDT 24
Finished Jun 30 06:34:34 PM PDT 24
Peak memory 201848 kb
Host smart-84495745-2222-4a3d-a446-8a0abc7bdbb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358925723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3358925723
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.277504593
Short name T541
Test name
Test status
Simulation time 386934104900 ps
CPU time 170.49 seconds
Started Jun 30 06:28:55 PM PDT 24
Finished Jun 30 06:31:47 PM PDT 24
Peak memory 201856 kb
Host smart-ef15dc85-d7cf-4dee-910b-c70e832e0e74
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277504593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.277504593
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2925174958
Short name T532
Test name
Test status
Simulation time 33215006810 ps
CPU time 18.25 seconds
Started Jun 30 06:28:57 PM PDT 24
Finished Jun 30 06:29:17 PM PDT 24
Peak memory 201672 kb
Host smart-e963f84e-00f8-491e-a59b-4b8e9d50121b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925174958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2925174958
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3936031604
Short name T574
Test name
Test status
Simulation time 5183290759 ps
CPU time 1.54 seconds
Started Jun 30 06:28:56 PM PDT 24
Finished Jun 30 06:29:00 PM PDT 24
Peak memory 201684 kb
Host smart-7bc9a570-93a6-418a-a14a-8adc549fdd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936031604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3936031604
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3033090147
Short name T771
Test name
Test status
Simulation time 5798599592 ps
CPU time 9.29 seconds
Started Jun 30 06:28:54 PM PDT 24
Finished Jun 30 06:29:05 PM PDT 24
Peak memory 201620 kb
Host smart-d210f645-2340-4264-8f3c-adfc82d5b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033090147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3033090147
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.16202317
Short name T561
Test name
Test status
Simulation time 459301086 ps
CPU time 1.66 seconds
Started Jun 30 06:29:08 PM PDT 24
Finished Jun 30 06:29:10 PM PDT 24
Peak memory 201640 kb
Host smart-0846619c-9757-40a9-9743-ed69a24fc751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16202317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.16202317
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.944615097
Short name T217
Test name
Test status
Simulation time 167276914796 ps
CPU time 92.08 seconds
Started Jun 30 06:29:03 PM PDT 24
Finished Jun 30 06:30:36 PM PDT 24
Peak memory 201876 kb
Host smart-5438d4b4-4632-47ab-95f6-07ab9a86d1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944615097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.944615097
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2012779196
Short name T794
Test name
Test status
Simulation time 331216453442 ps
CPU time 249.73 seconds
Started Jun 30 06:29:10 PM PDT 24
Finished Jun 30 06:33:21 PM PDT 24
Peak memory 201852 kb
Host smart-90c1e743-2d52-48be-9421-e95532a14ece
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012779196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2012779196
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3487333544
Short name T660
Test name
Test status
Simulation time 164389755293 ps
CPU time 366.89 seconds
Started Jun 30 06:29:03 PM PDT 24
Finished Jun 30 06:35:11 PM PDT 24
Peak memory 201844 kb
Host smart-404d6ce3-7a83-45f1-bdc6-8061b4c328d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487333544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3487333544
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2040000721
Short name T500
Test name
Test status
Simulation time 161103595464 ps
CPU time 181.26 seconds
Started Jun 30 06:28:56 PM PDT 24
Finished Jun 30 06:31:59 PM PDT 24
Peak memory 201840 kb
Host smart-5b16b1c1-0068-4e8e-be3e-32146aabadc6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040000721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2040000721
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2781988941
Short name T281
Test name
Test status
Simulation time 357378114306 ps
CPU time 428.32 seconds
Started Jun 30 06:29:04 PM PDT 24
Finished Jun 30 06:36:13 PM PDT 24
Peak memory 201888 kb
Host smart-c12e5187-645c-424e-9ea2-9cb55f0dc4f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781988941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2781988941
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2121038760
Short name T546
Test name
Test status
Simulation time 410916883083 ps
CPU time 898.49 seconds
Started Jun 30 06:29:08 PM PDT 24
Finished Jun 30 06:44:07 PM PDT 24
Peak memory 201928 kb
Host smart-7a1bd716-e633-48b7-a520-c2f2dac46cf7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121038760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2121038760
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1876323257
Short name T3
Test name
Test status
Simulation time 103749167426 ps
CPU time 489.19 seconds
Started Jun 30 06:29:09 PM PDT 24
Finished Jun 30 06:37:19 PM PDT 24
Peak memory 202484 kb
Host smart-85d32aa6-4697-407e-b073-60c4be180a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876323257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1876323257
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1172014344
Short name T702
Test name
Test status
Simulation time 38154323941 ps
CPU time 48.38 seconds
Started Jun 30 06:29:04 PM PDT 24
Finished Jun 30 06:29:53 PM PDT 24
Peak memory 201688 kb
Host smart-75f2e1cb-9444-411f-bdca-37e169fbad2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172014344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1172014344
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2416481026
Short name T544
Test name
Test status
Simulation time 3907593740 ps
CPU time 8.61 seconds
Started Jun 30 06:29:07 PM PDT 24
Finished Jun 30 06:29:16 PM PDT 24
Peak memory 201692 kb
Host smart-8958265e-534a-4869-8f2b-b4e91e84aa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416481026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2416481026
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3565132061
Short name T61
Test name
Test status
Simulation time 5859395473 ps
CPU time 14.33 seconds
Started Jun 30 06:28:56 PM PDT 24
Finished Jun 30 06:29:13 PM PDT 24
Peak memory 201668 kb
Host smart-4abde9a4-e3a0-4a5f-82a2-04faa0620412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565132061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3565132061
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1622334148
Short name T154
Test name
Test status
Simulation time 409416403286 ps
CPU time 864.88 seconds
Started Jun 30 06:29:10 PM PDT 24
Finished Jun 30 06:43:36 PM PDT 24
Peak memory 201804 kb
Host smart-7b1df614-0f4c-4b1d-9ced-d0b8fbeb986f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622334148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1622334148
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2776082894
Short name T102
Test name
Test status
Simulation time 55667567023 ps
CPU time 156.31 seconds
Started Jun 30 06:29:12 PM PDT 24
Finished Jun 30 06:31:49 PM PDT 24
Peak memory 210524 kb
Host smart-c9ae5976-cf69-4c0d-88c7-83338615b316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776082894 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2776082894
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1126074138
Short name T604
Test name
Test status
Simulation time 442235783 ps
CPU time 0.71 seconds
Started Jun 30 06:29:15 PM PDT 24
Finished Jun 30 06:29:16 PM PDT 24
Peak memory 201536 kb
Host smart-64acd337-8da2-44ad-a8ed-0f8e3051b643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126074138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1126074138
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2602907678
Short name T289
Test name
Test status
Simulation time 201287938007 ps
CPU time 468.04 seconds
Started Jun 30 06:29:10 PM PDT 24
Finished Jun 30 06:36:59 PM PDT 24
Peak memory 201860 kb
Host smart-dc0ff108-364f-4e47-8a9c-09a4b411fc4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602907678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2602907678
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.631955422
Short name T586
Test name
Test status
Simulation time 521095758319 ps
CPU time 1158.27 seconds
Started Jun 30 06:29:16 PM PDT 24
Finished Jun 30 06:48:35 PM PDT 24
Peak memory 201860 kb
Host smart-88dfb890-8f6d-471c-9a53-f66a4801b176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631955422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.631955422
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3405127799
Short name T659
Test name
Test status
Simulation time 491023487805 ps
CPU time 1171.88 seconds
Started Jun 30 06:29:12 PM PDT 24
Finished Jun 30 06:48:44 PM PDT 24
Peak memory 201860 kb
Host smart-a7aedbce-7c6f-4064-857a-19fc26522f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405127799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3405127799
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1628619313
Short name T468
Test name
Test status
Simulation time 323911450763 ps
CPU time 770.32 seconds
Started Jun 30 06:29:15 PM PDT 24
Finished Jun 30 06:42:07 PM PDT 24
Peak memory 201816 kb
Host smart-8cfac4c6-b446-40ef-bcf1-0475a17bdcd4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628619313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1628619313
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1570628811
Short name T686
Test name
Test status
Simulation time 327426220940 ps
CPU time 713.6 seconds
Started Jun 30 06:29:06 PM PDT 24
Finished Jun 30 06:41:00 PM PDT 24
Peak memory 201864 kb
Host smart-db61a714-e053-4a7d-82c4-9d10a40908f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570628811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1570628811
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.72553818
Short name T99
Test name
Test status
Simulation time 498288613116 ps
CPU time 176.61 seconds
Started Jun 30 06:29:12 PM PDT 24
Finished Jun 30 06:32:10 PM PDT 24
Peak memory 201832 kb
Host smart-dd7da160-7bc8-473a-9277-a4533183f104
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=72553818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed
.72553818
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.631139832
Short name T181
Test name
Test status
Simulation time 550569895190 ps
CPU time 291.67 seconds
Started Jun 30 06:29:10 PM PDT 24
Finished Jun 30 06:34:03 PM PDT 24
Peak memory 201848 kb
Host smart-e55c937e-bcc5-4b60-a947-e2b927027f84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631139832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.631139832
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3304900466
Short name T388
Test name
Test status
Simulation time 401949525770 ps
CPU time 961.47 seconds
Started Jun 30 06:29:16 PM PDT 24
Finished Jun 30 06:45:18 PM PDT 24
Peak memory 201828 kb
Host smart-3afefa22-48f2-4ed7-b53b-e2a84e7d4d38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304900466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3304900466
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1148645746
Short name T358
Test name
Test status
Simulation time 133121894365 ps
CPU time 673.51 seconds
Started Jun 30 06:29:16 PM PDT 24
Finished Jun 30 06:40:30 PM PDT 24
Peak memory 202200 kb
Host smart-c76c607e-de83-4c38-9901-9fc0a1493eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148645746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1148645746
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3398473476
Short name T750
Test name
Test status
Simulation time 23723037756 ps
CPU time 53.78 seconds
Started Jun 30 06:29:17 PM PDT 24
Finished Jun 30 06:30:11 PM PDT 24
Peak memory 201660 kb
Host smart-8dcc9967-2cac-4d73-882f-45e14f3b785f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398473476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3398473476
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3582426704
Short name T469
Test name
Test status
Simulation time 3604802266 ps
CPU time 8.49 seconds
Started Jun 30 06:29:11 PM PDT 24
Finished Jun 30 06:29:20 PM PDT 24
Peak memory 201644 kb
Host smart-747b584e-e841-4736-bfa7-d8d5f31648fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582426704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3582426704
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.4024131056
Short name T677
Test name
Test status
Simulation time 5893593424 ps
CPU time 14.25 seconds
Started Jun 30 06:29:09 PM PDT 24
Finished Jun 30 06:29:24 PM PDT 24
Peak memory 201672 kb
Host smart-658a0d38-b5cf-43d5-a441-d94eaefdcc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024131056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.4024131056
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3983717486
Short name T382
Test name
Test status
Simulation time 36772399288 ps
CPU time 43.71 seconds
Started Jun 30 06:29:16 PM PDT 24
Finished Jun 30 06:30:00 PM PDT 24
Peak memory 201608 kb
Host smart-de750433-3a84-4eb8-b9a9-38f7712c03cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983717486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3983717486
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1701960053
Short name T20
Test name
Test status
Simulation time 20431981819 ps
CPU time 66.49 seconds
Started Jun 30 06:29:18 PM PDT 24
Finished Jun 30 06:30:25 PM PDT 24
Peak memory 202424 kb
Host smart-0c094a01-725e-4c64-9909-f83af38d9693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701960053 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1701960053
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3947059207
Short name T524
Test name
Test status
Simulation time 443733628 ps
CPU time 1.66 seconds
Started Jun 30 06:27:41 PM PDT 24
Finished Jun 30 06:27:44 PM PDT 24
Peak memory 201488 kb
Host smart-553b2c11-369b-4b59-836e-d5df463707b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947059207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3947059207
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2072835822
Short name T320
Test name
Test status
Simulation time 161671521777 ps
CPU time 97.51 seconds
Started Jun 30 06:27:57 PM PDT 24
Finished Jun 30 06:29:35 PM PDT 24
Peak memory 201856 kb
Host smart-e1a8cd88-1423-4446-8167-53456ade8f1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072835822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2072835822
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3735666657
Short name T582
Test name
Test status
Simulation time 568000772600 ps
CPU time 1308.84 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:49:11 PM PDT 24
Peak memory 201848 kb
Host smart-7470a335-c05c-44f4-9579-7ebebeadadea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735666657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3735666657
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3335046415
Short name T6
Test name
Test status
Simulation time 165731922145 ps
CPU time 404.88 seconds
Started Jun 30 06:27:26 PM PDT 24
Finished Jun 30 06:34:13 PM PDT 24
Peak memory 201884 kb
Host smart-811fbe0d-5fe1-441a-8963-d26dd026af31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335046415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3335046415
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.4254479641
Short name T526
Test name
Test status
Simulation time 167942691762 ps
CPU time 398.94 seconds
Started Jun 30 06:27:24 PM PDT 24
Finished Jun 30 06:34:06 PM PDT 24
Peak memory 201860 kb
Host smart-943dccee-a182-40dd-9dea-86de2bf63cf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254479641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.4254479641
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1340835863
Short name T436
Test name
Test status
Simulation time 161530992448 ps
CPU time 101.31 seconds
Started Jun 30 06:27:23 PM PDT 24
Finished Jun 30 06:29:08 PM PDT 24
Peak memory 201884 kb
Host smart-dd5e8555-c2ce-41eb-ba31-14bdbc327c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340835863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1340835863
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2493267628
Short name T55
Test name
Test status
Simulation time 337025490401 ps
CPU time 319.34 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:32:42 PM PDT 24
Peak memory 201936 kb
Host smart-b17e50e8-d0a0-4f82-80a6-123f0fdc3244
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493267628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2493267628
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2291115937
Short name T370
Test name
Test status
Simulation time 601627628649 ps
CPU time 671.91 seconds
Started Jun 30 06:27:18 PM PDT 24
Finished Jun 30 06:38:34 PM PDT 24
Peak memory 201716 kb
Host smart-933c97b0-2c94-48c3-95e1-709fa2a50202
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291115937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2291115937
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.448917677
Short name T739
Test name
Test status
Simulation time 106223415272 ps
CPU time 571.26 seconds
Started Jun 30 06:27:24 PM PDT 24
Finished Jun 30 06:36:58 PM PDT 24
Peak memory 202220 kb
Host smart-28120a84-2490-4136-86a6-f93ad4e670ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448917677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.448917677
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2427933682
Short name T681
Test name
Test status
Simulation time 30840825859 ps
CPU time 19.12 seconds
Started Jun 30 06:27:19 PM PDT 24
Finished Jun 30 06:27:42 PM PDT 24
Peak memory 201680 kb
Host smart-734f6583-882f-4c2a-b2a2-59f92e9d225c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427933682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2427933682
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3493676488
Short name T456
Test name
Test status
Simulation time 4268004796 ps
CPU time 9.94 seconds
Started Jun 30 06:27:27 PM PDT 24
Finished Jun 30 06:27:38 PM PDT 24
Peak memory 201680 kb
Host smart-34d808f0-7269-45ab-9289-92c2abd74213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493676488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3493676488
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3440313527
Short name T79
Test name
Test status
Simulation time 4350791981 ps
CPU time 4.49 seconds
Started Jun 30 06:27:42 PM PDT 24
Finished Jun 30 06:27:47 PM PDT 24
Peak memory 217220 kb
Host smart-ef7759de-85d2-4202-a470-31a5babd7f5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440313527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3440313527
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.976998174
Short name T790
Test name
Test status
Simulation time 5772616339 ps
CPU time 13.67 seconds
Started Jun 30 06:27:43 PM PDT 24
Finished Jun 30 06:27:58 PM PDT 24
Peak memory 201584 kb
Host smart-78820416-6684-4a8f-949a-c5d063eb7a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976998174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.976998174
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.191748312
Short name T745
Test name
Test status
Simulation time 352083503358 ps
CPU time 52.01 seconds
Started Jun 30 06:27:46 PM PDT 24
Finished Jun 30 06:28:39 PM PDT 24
Peak memory 201772 kb
Host smart-6b7763fd-b2b2-4c68-8ba6-d4925b5e808a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191748312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.191748312
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.4094864745
Short name T721
Test name
Test status
Simulation time 264221236485 ps
CPU time 160.25 seconds
Started Jun 30 06:27:34 PM PDT 24
Finished Jun 30 06:30:14 PM PDT 24
Peak memory 210256 kb
Host smart-68987353-c7d3-4c02-be0b-80fa41c12831
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094864745 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.4094864745
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3865172116
Short name T668
Test name
Test status
Simulation time 401380210 ps
CPU time 1.44 seconds
Started Jun 30 06:29:26 PM PDT 24
Finished Jun 30 06:29:28 PM PDT 24
Peak memory 201588 kb
Host smart-dfc5b424-7ecb-42ad-8ac3-5219a80be340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865172116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3865172116
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2232116442
Short name T224
Test name
Test status
Simulation time 160792162345 ps
CPU time 372.51 seconds
Started Jun 30 06:29:22 PM PDT 24
Finished Jun 30 06:35:36 PM PDT 24
Peak memory 201888 kb
Host smart-ad72e86b-cbcb-481e-af1e-8a48323b65cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232116442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2232116442
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2846464953
Short name T300
Test name
Test status
Simulation time 496020763351 ps
CPU time 304.86 seconds
Started Jun 30 06:29:22 PM PDT 24
Finished Jun 30 06:34:27 PM PDT 24
Peak memory 201832 kb
Host smart-9947d25f-22f3-4e44-a26e-35443fbba10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846464953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2846464953
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2140426828
Short name T374
Test name
Test status
Simulation time 493431302449 ps
CPU time 580.5 seconds
Started Jun 30 06:29:21 PM PDT 24
Finished Jun 30 06:39:02 PM PDT 24
Peak memory 201844 kb
Host smart-b2e5ce9a-a136-4638-b902-7195d49321f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140426828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2140426828
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.262657643
Short name T338
Test name
Test status
Simulation time 162386196545 ps
CPU time 363.07 seconds
Started Jun 30 06:29:21 PM PDT 24
Finished Jun 30 06:35:25 PM PDT 24
Peak memory 201888 kb
Host smart-15c18c9c-14e4-4a5b-b6cc-66395dc1c5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262657643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.262657643
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2434306192
Short name T383
Test name
Test status
Simulation time 325792151778 ps
CPU time 696.94 seconds
Started Jun 30 06:29:21 PM PDT 24
Finished Jun 30 06:40:59 PM PDT 24
Peak memory 201852 kb
Host smart-7adf8f8d-71a4-491e-a5d3-bec6d59f37b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434306192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2434306192
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3528889457
Short name T164
Test name
Test status
Simulation time 404841558531 ps
CPU time 227.06 seconds
Started Jun 30 06:29:21 PM PDT 24
Finished Jun 30 06:33:09 PM PDT 24
Peak memory 201880 kb
Host smart-70495d0a-2eef-4912-bed0-8840723471ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528889457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3528889457
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3005514244
Short name T786
Test name
Test status
Simulation time 194970153823 ps
CPU time 161.86 seconds
Started Jun 30 06:29:21 PM PDT 24
Finished Jun 30 06:32:03 PM PDT 24
Peak memory 201864 kb
Host smart-7fb9e740-e299-4bcd-843f-a55a2531c2ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005514244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3005514244
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3660797004
Short name T204
Test name
Test status
Simulation time 99534343891 ps
CPU time 499.15 seconds
Started Jun 30 06:29:22 PM PDT 24
Finished Jun 30 06:37:42 PM PDT 24
Peak memory 202136 kb
Host smart-aafc2755-7aab-4723-a98b-ea263c023a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660797004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3660797004
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2298447220
Short name T112
Test name
Test status
Simulation time 31049062881 ps
CPU time 12.05 seconds
Started Jun 30 06:29:22 PM PDT 24
Finished Jun 30 06:29:35 PM PDT 24
Peak memory 201680 kb
Host smart-5b553513-e2b1-4c63-bf4e-8bdbc59ee18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298447220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2298447220
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.395406220
Short name T775
Test name
Test status
Simulation time 3994936878 ps
CPU time 10.48 seconds
Started Jun 30 06:29:23 PM PDT 24
Finished Jun 30 06:29:34 PM PDT 24
Peak memory 201072 kb
Host smart-cc50ad0d-50e9-468a-8659-4efa2838eb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395406220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.395406220
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2083490463
Short name T368
Test name
Test status
Simulation time 5778700624 ps
CPU time 3.82 seconds
Started Jun 30 06:29:24 PM PDT 24
Finished Jun 30 06:29:29 PM PDT 24
Peak memory 201672 kb
Host smart-95eec20a-2af7-4140-a095-38a324b80251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083490463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2083490463
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.96559295
Short name T233
Test name
Test status
Simulation time 203092305531 ps
CPU time 81.69 seconds
Started Jun 30 06:29:27 PM PDT 24
Finished Jun 30 06:30:50 PM PDT 24
Peak memory 201924 kb
Host smart-65ee863b-261d-460c-83ab-b0b43215b8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96559295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.96559295
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3936757952
Short name T723
Test name
Test status
Simulation time 497186213 ps
CPU time 1.12 seconds
Started Jun 30 06:29:31 PM PDT 24
Finished Jun 30 06:29:33 PM PDT 24
Peak memory 201564 kb
Host smart-ead164c0-9f05-4cdf-a8c9-b9e737b80f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936757952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3936757952
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3705354177
Short name T232
Test name
Test status
Simulation time 174862331576 ps
CPU time 331.23 seconds
Started Jun 30 06:29:30 PM PDT 24
Finished Jun 30 06:35:02 PM PDT 24
Peak memory 201908 kb
Host smart-85cc4f71-e163-435c-b1f1-2c714c688415
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705354177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3705354177
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2162819585
Short name T31
Test name
Test status
Simulation time 414396236926 ps
CPU time 245.06 seconds
Started Jun 30 06:29:33 PM PDT 24
Finished Jun 30 06:33:39 PM PDT 24
Peak memory 201908 kb
Host smart-4d03b2c2-1b13-4b21-8fab-68ccde6700d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162819585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2162819585
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.740081837
Short name T531
Test name
Test status
Simulation time 331122340660 ps
CPU time 383.29 seconds
Started Jun 30 06:29:27 PM PDT 24
Finished Jun 30 06:35:51 PM PDT 24
Peak memory 201828 kb
Host smart-546f85d8-e62c-4d77-abc8-d09379636f51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=740081837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.740081837
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2821017872
Short name T161
Test name
Test status
Simulation time 324461967517 ps
CPU time 768.86 seconds
Started Jun 30 06:29:26 PM PDT 24
Finished Jun 30 06:42:15 PM PDT 24
Peak memory 201832 kb
Host smart-d8661b42-bd04-4a0e-9416-0939c357200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821017872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2821017872
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3384279838
Short name T398
Test name
Test status
Simulation time 163016755683 ps
CPU time 40.79 seconds
Started Jun 30 06:29:26 PM PDT 24
Finished Jun 30 06:30:07 PM PDT 24
Peak memory 201792 kb
Host smart-94963256-1e02-4195-b437-7b99e5482caa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384279838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3384279838
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1213221557
Short name T258
Test name
Test status
Simulation time 535697521192 ps
CPU time 1146.78 seconds
Started Jun 30 06:29:29 PM PDT 24
Finished Jun 30 06:48:36 PM PDT 24
Peak memory 201884 kb
Host smart-40eccb77-b93d-403b-ba2b-9e497e9b5377
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213221557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1213221557
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.249898050
Short name T462
Test name
Test status
Simulation time 201161516129 ps
CPU time 241.93 seconds
Started Jun 30 06:29:26 PM PDT 24
Finished Jun 30 06:33:29 PM PDT 24
Peak memory 201844 kb
Host smart-4301a865-7357-4587-a479-d9c23fbb8bb1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249898050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.249898050
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1770760161
Short name T208
Test name
Test status
Simulation time 98166653716 ps
CPU time 292.4 seconds
Started Jun 30 06:29:33 PM PDT 24
Finished Jun 30 06:34:27 PM PDT 24
Peak memory 202260 kb
Host smart-687a0434-ccdb-446a-8dba-b04ed1b3421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770760161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1770760161
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2211922918
Short name T511
Test name
Test status
Simulation time 29813302355 ps
CPU time 17.09 seconds
Started Jun 30 06:29:26 PM PDT 24
Finished Jun 30 06:29:44 PM PDT 24
Peak memory 201688 kb
Host smart-72b787f9-caa5-4163-8d5f-30c8f12010ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211922918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2211922918
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.594555523
Short name T576
Test name
Test status
Simulation time 3476321210 ps
CPU time 4.69 seconds
Started Jun 30 06:29:34 PM PDT 24
Finished Jun 30 06:29:39 PM PDT 24
Peak memory 201704 kb
Host smart-234b6602-99ed-4285-869d-7947b3799da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594555523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.594555523
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2719086978
Short name T439
Test name
Test status
Simulation time 6136944213 ps
CPU time 8.9 seconds
Started Jun 30 06:29:29 PM PDT 24
Finished Jun 30 06:29:39 PM PDT 24
Peak memory 201656 kb
Host smart-eedb428f-b693-45c2-9817-71bf5875d979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719086978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2719086978
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.587253140
Short name T624
Test name
Test status
Simulation time 1164764366 ps
CPU time 3.4 seconds
Started Jun 30 06:29:32 PM PDT 24
Finished Jun 30 06:29:36 PM PDT 24
Peak memory 201572 kb
Host smart-89a8b643-3142-4aa6-a19c-a3506a940504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587253140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
587253140
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1209412599
Short name T776
Test name
Test status
Simulation time 129217202485 ps
CPU time 206.74 seconds
Started Jun 30 06:29:32 PM PDT 24
Finished Jun 30 06:32:59 PM PDT 24
Peak memory 210564 kb
Host smart-05bec695-4ff8-434b-bee7-3e3a5f5cd19e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209412599 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1209412599
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1576415059
Short name T474
Test name
Test status
Simulation time 298139040 ps
CPU time 1.27 seconds
Started Jun 30 06:29:37 PM PDT 24
Finished Jun 30 06:29:39 PM PDT 24
Peak memory 201660 kb
Host smart-50bb29e9-b9d3-45e9-87e4-2c66737b1513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576415059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1576415059
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.4170222447
Short name T123
Test name
Test status
Simulation time 493494738331 ps
CPU time 1098.94 seconds
Started Jun 30 06:29:40 PM PDT 24
Finished Jun 30 06:47:59 PM PDT 24
Peak memory 201880 kb
Host smart-8c89ce42-2e23-4c11-ad6a-36db14aef0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170222447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.4170222447
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2870343844
Short name T763
Test name
Test status
Simulation time 329716000357 ps
CPU time 358.36 seconds
Started Jun 30 06:29:34 PM PDT 24
Finished Jun 30 06:35:33 PM PDT 24
Peak memory 201864 kb
Host smart-0bc988aa-919f-4a3e-b803-2114ab283663
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870343844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2870343844
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1394461438
Short name T404
Test name
Test status
Simulation time 162574364511 ps
CPU time 83.59 seconds
Started Jun 30 06:29:30 PM PDT 24
Finished Jun 30 06:30:55 PM PDT 24
Peak memory 201868 kb
Host smart-d93acc0b-9541-4da3-ba3a-d5cd2ce2475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394461438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1394461438
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1846354712
Short name T11
Test name
Test status
Simulation time 329709293876 ps
CPU time 217.79 seconds
Started Jun 30 06:29:32 PM PDT 24
Finished Jun 30 06:33:10 PM PDT 24
Peak memory 201868 kb
Host smart-1d1d81c3-73f9-4a62-a274-1705472ec572
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846354712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1846354712
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3581166625
Short name T306
Test name
Test status
Simulation time 536144182250 ps
CPU time 1195.41 seconds
Started Jun 30 06:29:33 PM PDT 24
Finished Jun 30 06:49:29 PM PDT 24
Peak memory 201868 kb
Host smart-c20f74c4-0eeb-4023-9d98-4a67d04f7261
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581166625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3581166625
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1645887312
Short name T385
Test name
Test status
Simulation time 608125542791 ps
CPU time 1423.06 seconds
Started Jun 30 06:29:37 PM PDT 24
Finished Jun 30 06:53:21 PM PDT 24
Peak memory 201864 kb
Host smart-fbb26277-3413-4fbd-a151-509408a07c26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645887312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1645887312
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2775668999
Short name T199
Test name
Test status
Simulation time 143654282682 ps
CPU time 508.92 seconds
Started Jun 30 06:29:37 PM PDT 24
Finished Jun 30 06:38:07 PM PDT 24
Peak memory 202176 kb
Host smart-dfddb2a1-f120-4c68-b0ab-30bd0be87d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775668999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2775668999
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3978544490
Short name T445
Test name
Test status
Simulation time 30805180299 ps
CPU time 17.71 seconds
Started Jun 30 06:29:36 PM PDT 24
Finished Jun 30 06:29:55 PM PDT 24
Peak memory 201668 kb
Host smart-8e3931be-fb3a-407c-be27-e3711df0400f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978544490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3978544490
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.4135350104
Short name T612
Test name
Test status
Simulation time 4566759826 ps
CPU time 11.25 seconds
Started Jun 30 06:29:32 PM PDT 24
Finished Jun 30 06:29:44 PM PDT 24
Peak memory 201636 kb
Host smart-9ad91797-f4c8-4b87-b790-dc801a1f30fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135350104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4135350104
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2882435985
Short name T606
Test name
Test status
Simulation time 5801799122 ps
CPU time 7.45 seconds
Started Jun 30 06:29:30 PM PDT 24
Finished Jun 30 06:29:38 PM PDT 24
Peak memory 201688 kb
Host smart-c3f4d68b-3a85-4f29-baf4-a1c2e9006bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882435985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2882435985
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2058837151
Short name T675
Test name
Test status
Simulation time 341218743569 ps
CPU time 204.08 seconds
Started Jun 30 06:29:38 PM PDT 24
Finished Jun 30 06:33:02 PM PDT 24
Peak memory 201860 kb
Host smart-d83e1d1f-5f01-4d5d-b9a0-09f83b3d089b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058837151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2058837151
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2946664055
Short name T784
Test name
Test status
Simulation time 154245563882 ps
CPU time 327.41 seconds
Started Jun 30 06:29:37 PM PDT 24
Finished Jun 30 06:35:05 PM PDT 24
Peak memory 210584 kb
Host smart-c4743986-5a20-4e1d-8756-bd2ebe58d8a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946664055 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2946664055
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2149578780
Short name T640
Test name
Test status
Simulation time 523824788 ps
CPU time 0.92 seconds
Started Jun 30 06:29:44 PM PDT 24
Finished Jun 30 06:29:46 PM PDT 24
Peak memory 201628 kb
Host smart-20e1dbc7-04c6-46d7-b320-2c816b9a7b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149578780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2149578780
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.4258253852
Short name T166
Test name
Test status
Simulation time 162620509244 ps
CPU time 51.27 seconds
Started Jun 30 06:29:43 PM PDT 24
Finished Jun 30 06:30:35 PM PDT 24
Peak memory 201852 kb
Host smart-e5545252-549d-4c32-8a13-d88027d014e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258253852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.4258253852
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3566793926
Short name T225
Test name
Test status
Simulation time 178173507312 ps
CPU time 431.32 seconds
Started Jun 30 06:29:43 PM PDT 24
Finished Jun 30 06:36:55 PM PDT 24
Peak memory 201956 kb
Host smart-c500842d-17c1-4027-8749-37d78070d99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566793926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3566793926
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1760546936
Short name T498
Test name
Test status
Simulation time 167580262636 ps
CPU time 371.96 seconds
Started Jun 30 06:29:38 PM PDT 24
Finished Jun 30 06:35:50 PM PDT 24
Peak memory 201848 kb
Host smart-0d4cea48-9842-47dc-89f2-0c8f55299b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760546936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1760546936
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2589759478
Short name T535
Test name
Test status
Simulation time 165626518909 ps
CPU time 389.27 seconds
Started Jun 30 06:29:40 PM PDT 24
Finished Jun 30 06:36:10 PM PDT 24
Peak memory 201840 kb
Host smart-cce70423-0423-4529-8b45-30e674a6d88d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589759478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2589759478
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2114244965
Short name T688
Test name
Test status
Simulation time 327599459331 ps
CPU time 97.28 seconds
Started Jun 30 06:29:36 PM PDT 24
Finished Jun 30 06:31:14 PM PDT 24
Peak memory 201952 kb
Host smart-00e0cb86-8f95-438c-bf33-4b3e995695b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114244965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2114244965
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3794448452
Short name T493
Test name
Test status
Simulation time 495833698075 ps
CPU time 611.79 seconds
Started Jun 30 06:29:42 PM PDT 24
Finished Jun 30 06:39:54 PM PDT 24
Peak memory 201856 kb
Host smart-7dabceb7-6f90-4fd7-a51a-3562bd08b977
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794448452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3794448452
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3057742407
Short name T516
Test name
Test status
Simulation time 401810320433 ps
CPU time 851.16 seconds
Started Jun 30 06:29:39 PM PDT 24
Finished Jun 30 06:43:51 PM PDT 24
Peak memory 201940 kb
Host smart-f73ebd23-1146-471a-8725-acd0a1b05007
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057742407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3057742407
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.968849821
Short name T111
Test name
Test status
Simulation time 206924152117 ps
CPU time 498.72 seconds
Started Jun 30 06:29:45 PM PDT 24
Finished Jun 30 06:38:04 PM PDT 24
Peak memory 201856 kb
Host smart-59296a92-cde1-4a22-bb85-6dd3e12e2d8a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968849821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.968849821
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3690326802
Short name T424
Test name
Test status
Simulation time 22907381057 ps
CPU time 13.48 seconds
Started Jun 30 06:29:42 PM PDT 24
Finished Jun 30 06:29:56 PM PDT 24
Peak memory 201680 kb
Host smart-4f2fe2e3-5c74-4d0e-a846-04adefcb8d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690326802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3690326802
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3734244772
Short name T100
Test name
Test status
Simulation time 5374835472 ps
CPU time 11.61 seconds
Started Jun 30 06:29:43 PM PDT 24
Finished Jun 30 06:29:55 PM PDT 24
Peak memory 201628 kb
Host smart-c733e5e0-e201-4559-a206-91b50bc66dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734244772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3734244772
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.256181770
Short name T454
Test name
Test status
Simulation time 6054860846 ps
CPU time 1.79 seconds
Started Jun 30 06:29:42 PM PDT 24
Finished Jun 30 06:29:44 PM PDT 24
Peak memory 201680 kb
Host smart-f089d3ac-5668-439c-8cda-135a84efcb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256181770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.256181770
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1631608764
Short name T239
Test name
Test status
Simulation time 399179204970 ps
CPU time 448.94 seconds
Started Jun 30 06:29:42 PM PDT 24
Finished Jun 30 06:37:11 PM PDT 24
Peak memory 201928 kb
Host smart-ed4cea74-10b1-49fd-a431-3627ddb70d66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631608764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1631608764
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3482093746
Short name T669
Test name
Test status
Simulation time 101895736043 ps
CPU time 130.91 seconds
Started Jun 30 06:29:44 PM PDT 24
Finished Jun 30 06:31:55 PM PDT 24
Peak memory 210504 kb
Host smart-ad5acab9-a5fc-48b3-8b0c-8f543b82b7fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482093746 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3482093746
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.235368509
Short name T787
Test name
Test status
Simulation time 325170994 ps
CPU time 0.82 seconds
Started Jun 30 06:29:53 PM PDT 24
Finished Jun 30 06:29:54 PM PDT 24
Peak memory 201640 kb
Host smart-fda85002-f423-4183-b3ae-d47edaebb04c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235368509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.235368509
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3170232638
Short name T158
Test name
Test status
Simulation time 330262911796 ps
CPU time 161.76 seconds
Started Jun 30 06:29:47 PM PDT 24
Finished Jun 30 06:32:29 PM PDT 24
Peak memory 201868 kb
Host smart-ca9b2c4f-ef7f-4fc9-bc4d-11bb1efd611e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170232638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3170232638
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3274032780
Short name T663
Test name
Test status
Simulation time 490369715898 ps
CPU time 189.37 seconds
Started Jun 30 06:29:47 PM PDT 24
Finished Jun 30 06:32:57 PM PDT 24
Peak memory 201796 kb
Host smart-9d647818-76d7-4324-b692-38149b4e735e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274032780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3274032780
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.400952179
Short name T460
Test name
Test status
Simulation time 174308021174 ps
CPU time 81.19 seconds
Started Jun 30 06:29:44 PM PDT 24
Finished Jun 30 06:31:05 PM PDT 24
Peak memory 201856 kb
Host smart-10bfc380-47fe-4f1b-bcd2-062a0c85c08b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=400952179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.400952179
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3754356046
Short name T543
Test name
Test status
Simulation time 162325542869 ps
CPU time 350.64 seconds
Started Jun 30 06:29:44 PM PDT 24
Finished Jun 30 06:35:36 PM PDT 24
Peak memory 201832 kb
Host smart-a56f6951-b5d9-4e19-a60d-4bb3cb6dbd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754356046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3754356046
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1927664423
Short name T662
Test name
Test status
Simulation time 160271588673 ps
CPU time 51.17 seconds
Started Jun 30 06:29:45 PM PDT 24
Finished Jun 30 06:30:36 PM PDT 24
Peak memory 201816 kb
Host smart-75550927-9cce-404e-865f-d250a0d087ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927664423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1927664423
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.998802401
Short name T679
Test name
Test status
Simulation time 597757172791 ps
CPU time 115 seconds
Started Jun 30 06:29:48 PM PDT 24
Finished Jun 30 06:31:44 PM PDT 24
Peak memory 201832 kb
Host smart-8cec323e-dc07-47a2-9043-bb7b4f2fae22
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998802401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.998802401
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.4010986483
Short name T357
Test name
Test status
Simulation time 84263184270 ps
CPU time 264.67 seconds
Started Jun 30 06:29:49 PM PDT 24
Finished Jun 30 06:34:15 PM PDT 24
Peak memory 202192 kb
Host smart-e381f8f9-7ec0-467f-85b1-9a851bac14bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010986483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.4010986483
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1388842668
Short name T667
Test name
Test status
Simulation time 39563501687 ps
CPU time 90.33 seconds
Started Jun 30 06:29:51 PM PDT 24
Finished Jun 30 06:31:21 PM PDT 24
Peak memory 201696 kb
Host smart-242c2224-e478-4fc9-a658-f9d5f297fb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388842668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1388842668
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.734789186
Short name T585
Test name
Test status
Simulation time 3146394262 ps
CPU time 1.3 seconds
Started Jun 30 06:29:49 PM PDT 24
Finished Jun 30 06:29:51 PM PDT 24
Peak memory 201680 kb
Host smart-689afbb1-17ed-4237-ba4a-f6143e3f2f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734789186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.734789186
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1885660790
Short name T375
Test name
Test status
Simulation time 6142078434 ps
CPU time 4.34 seconds
Started Jun 30 06:29:45 PM PDT 24
Finished Jun 30 06:29:50 PM PDT 24
Peak memory 201584 kb
Host smart-937085fd-f91d-4c50-84a1-b2088484a593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885660790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1885660790
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.925024099
Short name T273
Test name
Test status
Simulation time 513041083177 ps
CPU time 111.64 seconds
Started Jun 30 06:29:49 PM PDT 24
Finished Jun 30 06:31:41 PM PDT 24
Peak memory 201808 kb
Host smart-06744740-2c7a-436c-8a73-e6c2f3dacde6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925024099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
925024099
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1073291524
Short name T46
Test name
Test status
Simulation time 23634143955 ps
CPU time 44.12 seconds
Started Jun 30 06:29:51 PM PDT 24
Finished Jun 30 06:30:36 PM PDT 24
Peak memory 202052 kb
Host smart-68525918-032a-4212-a493-2198423a881e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073291524 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1073291524
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1748754373
Short name T506
Test name
Test status
Simulation time 435818076 ps
CPU time 1.12 seconds
Started Jun 30 06:30:02 PM PDT 24
Finished Jun 30 06:30:03 PM PDT 24
Peak memory 201608 kb
Host smart-03c877e0-0e3e-4eb4-b39f-7c5f85c4dca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748754373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1748754373
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3789232956
Short name T38
Test name
Test status
Simulation time 328510461776 ps
CPU time 196.76 seconds
Started Jun 30 06:29:57 PM PDT 24
Finished Jun 30 06:33:14 PM PDT 24
Peak memory 201880 kb
Host smart-5af66844-23da-46c2-95f6-a22e7712bf91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789232956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3789232956
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3732756338
Short name T740
Test name
Test status
Simulation time 165051155032 ps
CPU time 93.77 seconds
Started Jun 30 06:30:06 PM PDT 24
Finished Jun 30 06:31:40 PM PDT 24
Peak memory 201868 kb
Host smart-8518ca48-8a90-4f80-99ec-6d57441b8ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732756338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3732756338
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1867300839
Short name T43
Test name
Test status
Simulation time 166362135887 ps
CPU time 362.02 seconds
Started Jun 30 06:29:54 PM PDT 24
Finished Jun 30 06:35:57 PM PDT 24
Peak memory 201856 kb
Host smart-5a631e0a-411c-4944-8120-131a942b4b56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867300839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1867300839
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.488111008
Short name T718
Test name
Test status
Simulation time 327679295490 ps
CPU time 112.34 seconds
Started Jun 30 06:29:49 PM PDT 24
Finished Jun 30 06:31:42 PM PDT 24
Peak memory 201984 kb
Host smart-520a381a-d484-4a97-be8d-b7be3ca32e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488111008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.488111008
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.239176594
Short name T420
Test name
Test status
Simulation time 167319577852 ps
CPU time 315.74 seconds
Started Jun 30 06:29:51 PM PDT 24
Finished Jun 30 06:35:07 PM PDT 24
Peak memory 202004 kb
Host smart-8247fc9b-c441-47fd-b43c-5ff13f7e8623
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=239176594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.239176594
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.572801077
Short name T96
Test name
Test status
Simulation time 165962167257 ps
CPU time 354.59 seconds
Started Jun 30 06:29:55 PM PDT 24
Finished Jun 30 06:35:50 PM PDT 24
Peak memory 201912 kb
Host smart-68511957-0ef6-4f2f-a388-cb6cc207c633
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572801077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.572801077
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2558735422
Short name T778
Test name
Test status
Simulation time 396281828921 ps
CPU time 467.78 seconds
Started Jun 30 06:29:54 PM PDT 24
Finished Jun 30 06:37:42 PM PDT 24
Peak memory 201840 kb
Host smart-2388a74c-7e16-4b33-a6ac-6afddab8f3b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558735422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2558735422
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.499154585
Short name T356
Test name
Test status
Simulation time 121032018349 ps
CPU time 456.49 seconds
Started Jun 30 06:29:59 PM PDT 24
Finished Jun 30 06:37:36 PM PDT 24
Peak memory 202156 kb
Host smart-3e1617bb-d5ff-4d0f-84ed-ddf95e9f9c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499154585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.499154585
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1445710049
Short name T642
Test name
Test status
Simulation time 33784757365 ps
CPU time 74.21 seconds
Started Jun 30 06:30:02 PM PDT 24
Finished Jun 30 06:31:16 PM PDT 24
Peak memory 201676 kb
Host smart-abb152b9-6926-4cf7-a0a2-98ba962a26cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445710049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1445710049
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1617235822
Short name T411
Test name
Test status
Simulation time 5223621291 ps
CPU time 12.07 seconds
Started Jun 30 06:29:59 PM PDT 24
Finished Jun 30 06:30:12 PM PDT 24
Peak memory 201676 kb
Host smart-a2ae9e8a-2147-4878-a356-514f4be35590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617235822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1617235822
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.420673119
Short name T626
Test name
Test status
Simulation time 5849706818 ps
CPU time 4.16 seconds
Started Jun 30 06:29:47 PM PDT 24
Finished Jun 30 06:29:52 PM PDT 24
Peak memory 201668 kb
Host smart-63f943dc-efdc-45fd-bfb3-5b996cd69290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420673119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.420673119
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.135061937
Short name T575
Test name
Test status
Simulation time 102305056280 ps
CPU time 525.78 seconds
Started Jun 30 06:30:00 PM PDT 24
Finished Jun 30 06:38:46 PM PDT 24
Peak memory 218132 kb
Host smart-98e57aab-d8da-41ee-a55c-bd7d2f620dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135061937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
135061937
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.367829926
Short name T757
Test name
Test status
Simulation time 802490807461 ps
CPU time 114.01 seconds
Started Jun 30 06:30:00 PM PDT 24
Finished Jun 30 06:31:54 PM PDT 24
Peak memory 210144 kb
Host smart-2bc4d27d-59a6-4b7b-91f0-ae737aa53a42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367829926 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.367829926
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2424678871
Short name T29
Test name
Test status
Simulation time 407647309 ps
CPU time 0.75 seconds
Started Jun 30 06:30:11 PM PDT 24
Finished Jun 30 06:30:12 PM PDT 24
Peak memory 201624 kb
Host smart-e774ab3d-65fd-4712-b482-b45bd91863c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424678871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2424678871
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3487737531
Short name T231
Test name
Test status
Simulation time 571838730300 ps
CPU time 277.44 seconds
Started Jun 30 06:30:03 PM PDT 24
Finished Jun 30 06:34:41 PM PDT 24
Peak memory 201932 kb
Host smart-444f73c5-0bdc-4aef-bcbe-1ed86eb3dc93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487737531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3487737531
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2836325781
Short name T618
Test name
Test status
Simulation time 340225964417 ps
CPU time 186.91 seconds
Started Jun 30 06:30:04 PM PDT 24
Finished Jun 30 06:33:12 PM PDT 24
Peak memory 201892 kb
Host smart-e5889e2a-f5bc-4f70-b1fa-8aa3f6cf7257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836325781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2836325781
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2850246659
Short name T302
Test name
Test status
Simulation time 166627590607 ps
CPU time 370.85 seconds
Started Jun 30 06:30:00 PM PDT 24
Finished Jun 30 06:36:11 PM PDT 24
Peak memory 201864 kb
Host smart-5e7bba26-5fca-4a73-9158-876d2c3f6f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850246659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2850246659
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3953154987
Short name T481
Test name
Test status
Simulation time 162842517572 ps
CPU time 74.13 seconds
Started Jun 30 06:30:01 PM PDT 24
Finished Jun 30 06:31:15 PM PDT 24
Peak memory 201852 kb
Host smart-565d8951-0f1d-4b80-8b6e-c0fcd2f39310
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953154987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3953154987
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3338414255
Short name T191
Test name
Test status
Simulation time 498385134819 ps
CPU time 270.61 seconds
Started Jun 30 06:30:02 PM PDT 24
Finished Jun 30 06:34:33 PM PDT 24
Peak memory 201864 kb
Host smart-5c4aea56-e1e1-4fae-a003-1704f4a92a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338414255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3338414255
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.109197092
Short name T671
Test name
Test status
Simulation time 327329242862 ps
CPU time 736.88 seconds
Started Jun 30 06:29:59 PM PDT 24
Finished Jun 30 06:42:16 PM PDT 24
Peak memory 201848 kb
Host smart-4c973556-6cb1-4bd5-b493-7ecac710c166
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=109197092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.109197092
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.642519022
Short name T177
Test name
Test status
Simulation time 370448121714 ps
CPU time 47.01 seconds
Started Jun 30 06:30:03 PM PDT 24
Finished Jun 30 06:30:50 PM PDT 24
Peak memory 201940 kb
Host smart-68d12fa0-2f50-40a9-9121-1923b1bd2e51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642519022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.642519022
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2445740623
Short name T418
Test name
Test status
Simulation time 617623569250 ps
CPU time 136.89 seconds
Started Jun 30 06:30:04 PM PDT 24
Finished Jun 30 06:32:22 PM PDT 24
Peak memory 202052 kb
Host smart-e6a849fa-7817-488e-91e2-b421fb17e42f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445740623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2445740623
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.489431565
Short name T631
Test name
Test status
Simulation time 111117533447 ps
CPU time 554.35 seconds
Started Jun 30 06:30:04 PM PDT 24
Finished Jun 30 06:39:18 PM PDT 24
Peak memory 202164 kb
Host smart-4f53af53-37da-440b-bc80-a321a4350fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489431565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.489431565
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1619293107
Short name T115
Test name
Test status
Simulation time 25883234249 ps
CPU time 7.45 seconds
Started Jun 30 06:30:04 PM PDT 24
Finished Jun 30 06:30:12 PM PDT 24
Peak memory 201680 kb
Host smart-e359091a-0bff-47d5-90d0-c8dd98d5aaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619293107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1619293107
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1678165464
Short name T380
Test name
Test status
Simulation time 3850742192 ps
CPU time 5.04 seconds
Started Jun 30 06:30:06 PM PDT 24
Finished Jun 30 06:30:12 PM PDT 24
Peak memory 201672 kb
Host smart-cc4eafb8-4839-4dcb-99ec-f6d07350079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678165464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1678165464
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.850913395
Short name T596
Test name
Test status
Simulation time 6039270691 ps
CPU time 5.63 seconds
Started Jun 30 06:30:00 PM PDT 24
Finished Jun 30 06:30:06 PM PDT 24
Peak memory 201680 kb
Host smart-71e16e0c-bdf4-4f9c-a353-1e1e5ded8c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850913395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.850913395
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2719304017
Short name T520
Test name
Test status
Simulation time 338727197032 ps
CPU time 712.6 seconds
Started Jun 30 06:30:12 PM PDT 24
Finished Jun 30 06:42:05 PM PDT 24
Peak memory 201888 kb
Host smart-c3fb1c89-2f71-45d9-a3f9-c6e31995b570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719304017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2719304017
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2908113983
Short name T44
Test name
Test status
Simulation time 33820270859 ps
CPU time 75.82 seconds
Started Jun 30 06:30:10 PM PDT 24
Finished Jun 30 06:31:26 PM PDT 24
Peak memory 210160 kb
Host smart-51536824-039f-4ec5-a769-a1beacbea31f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908113983 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2908113983
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.4040928052
Short name T488
Test name
Test status
Simulation time 523599003 ps
CPU time 1.86 seconds
Started Jun 30 06:30:18 PM PDT 24
Finished Jun 30 06:30:21 PM PDT 24
Peak memory 201632 kb
Host smart-98b3bdf2-b0e4-41fe-8ef8-219a3abe3e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040928052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.4040928052
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3697103233
Short name T179
Test name
Test status
Simulation time 479912539527 ps
CPU time 184.08 seconds
Started Jun 30 06:30:17 PM PDT 24
Finished Jun 30 06:33:22 PM PDT 24
Peak memory 201628 kb
Host smart-395b8d17-2a0a-4023-9f17-e50f9f45997e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697103233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3697103233
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1501088731
Short name T310
Test name
Test status
Simulation time 165428477841 ps
CPU time 406.97 seconds
Started Jun 30 06:30:14 PM PDT 24
Finished Jun 30 06:37:01 PM PDT 24
Peak memory 201936 kb
Host smart-02e7d429-83d5-4afe-9c60-9938dd0940c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501088731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1501088731
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1905168552
Short name T465
Test name
Test status
Simulation time 162202616509 ps
CPU time 381.08 seconds
Started Jun 30 06:30:17 PM PDT 24
Finished Jun 30 06:36:39 PM PDT 24
Peak memory 201688 kb
Host smart-47d150f5-4831-4419-8797-156cf9d027ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905168552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1905168552
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.630433556
Short name T518
Test name
Test status
Simulation time 328588129145 ps
CPU time 717.26 seconds
Started Jun 30 06:30:11 PM PDT 24
Finished Jun 30 06:42:09 PM PDT 24
Peak memory 201912 kb
Host smart-ac9253e1-8674-4a40-a9e7-de19ae9c2076
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=630433556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.630433556
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1647604465
Short name T599
Test name
Test status
Simulation time 205649490402 ps
CPU time 368.14 seconds
Started Jun 30 06:30:12 PM PDT 24
Finished Jun 30 06:36:20 PM PDT 24
Peak memory 201816 kb
Host smart-1cd5dc0b-0ca2-475b-9494-f7477371b62d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647604465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1647604465
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1145493543
Short name T609
Test name
Test status
Simulation time 100319158952 ps
CPU time 310.59 seconds
Started Jun 30 06:30:11 PM PDT 24
Finished Jun 30 06:35:22 PM PDT 24
Peak memory 202172 kb
Host smart-6dc2c7f5-0771-4fd3-b733-4748c18eabd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145493543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1145493543
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.291095997
Short name T706
Test name
Test status
Simulation time 37981660146 ps
CPU time 43.76 seconds
Started Jun 30 06:30:11 PM PDT 24
Finished Jun 30 06:30:55 PM PDT 24
Peak memory 201668 kb
Host smart-d39aa634-439e-49e6-a802-d7ecef2d9c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291095997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.291095997
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.756891505
Short name T533
Test name
Test status
Simulation time 2857284399 ps
CPU time 7.11 seconds
Started Jun 30 06:30:15 PM PDT 24
Finished Jun 30 06:30:22 PM PDT 24
Peak memory 201664 kb
Host smart-548aea1b-3bfe-431e-a990-3397a4dcea90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756891505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.756891505
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.691389116
Short name T566
Test name
Test status
Simulation time 5907082034 ps
CPU time 4.08 seconds
Started Jun 30 06:30:09 PM PDT 24
Finished Jun 30 06:30:14 PM PDT 24
Peak memory 201624 kb
Host smart-9bd664d9-6bf6-4012-81d0-06e156eeb6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691389116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.691389116
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3394570488
Short name T49
Test name
Test status
Simulation time 57314626871 ps
CPU time 160.01 seconds
Started Jun 30 06:30:15 PM PDT 24
Finished Jun 30 06:32:56 PM PDT 24
Peak memory 210500 kb
Host smart-3add42fd-fdb4-4899-baaf-72e40bf9c93d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394570488 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3394570488
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2706843455
Short name T664
Test name
Test status
Simulation time 507517691 ps
CPU time 0.89 seconds
Started Jun 30 06:30:20 PM PDT 24
Finished Jun 30 06:30:22 PM PDT 24
Peak memory 201628 kb
Host smart-68d5ad71-230b-490e-b0b8-58afc6a96aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706843455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2706843455
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.729599897
Short name T629
Test name
Test status
Simulation time 164215155644 ps
CPU time 338.14 seconds
Started Jun 30 06:30:21 PM PDT 24
Finished Jun 30 06:35:59 PM PDT 24
Peak memory 201872 kb
Host smart-a3040767-c87c-4ac7-8b17-76e9176126b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729599897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.729599897
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3655507278
Short name T346
Test name
Test status
Simulation time 339651863574 ps
CPU time 69.29 seconds
Started Jun 30 06:30:21 PM PDT 24
Finished Jun 30 06:31:31 PM PDT 24
Peak memory 201880 kb
Host smart-a477dcb8-974a-4d65-8d5a-d7142fb1c9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655507278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3655507278
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2239927812
Short name T318
Test name
Test status
Simulation time 331536824760 ps
CPU time 199.11 seconds
Started Jun 30 06:30:16 PM PDT 24
Finished Jun 30 06:33:36 PM PDT 24
Peak memory 201892 kb
Host smart-eafd8c88-82df-444b-b21c-f5e535f8310e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239927812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2239927812
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1308259479
Short name T243
Test name
Test status
Simulation time 159622722699 ps
CPU time 357.23 seconds
Started Jun 30 06:30:17 PM PDT 24
Finished Jun 30 06:36:15 PM PDT 24
Peak memory 201896 kb
Host smart-899569fe-1e85-4b46-be35-380b9856f671
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308259479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1308259479
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2055313790
Short name T5
Test name
Test status
Simulation time 159392678589 ps
CPU time 25.02 seconds
Started Jun 30 06:30:15 PM PDT 24
Finished Jun 30 06:30:40 PM PDT 24
Peak memory 201760 kb
Host smart-29523bf6-30c5-419b-aa6b-52d19aebd8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055313790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2055313790
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.344161759
Short name T484
Test name
Test status
Simulation time 163703499781 ps
CPU time 212 seconds
Started Jun 30 06:30:18 PM PDT 24
Finished Jun 30 06:33:51 PM PDT 24
Peak memory 201888 kb
Host smart-0537ba6e-2abd-4327-bf8e-a3faf43d3139
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=344161759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.344161759
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.726560602
Short name T253
Test name
Test status
Simulation time 180223227317 ps
CPU time 204.4 seconds
Started Jun 30 06:30:16 PM PDT 24
Finished Jun 30 06:33:41 PM PDT 24
Peak memory 201936 kb
Host smart-7e94a8f2-2089-4c5d-831f-8741cd5577db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726560602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.726560602
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3592725423
Short name T478
Test name
Test status
Simulation time 202132040623 ps
CPU time 434.28 seconds
Started Jun 30 06:30:15 PM PDT 24
Finished Jun 30 06:37:30 PM PDT 24
Peak memory 201888 kb
Host smart-55cdeec9-cabf-4195-bd80-0394cae358e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592725423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3592725423
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3291587512
Short name T559
Test name
Test status
Simulation time 134008371232 ps
CPU time 664.02 seconds
Started Jun 30 06:30:20 PM PDT 24
Finished Jun 30 06:41:25 PM PDT 24
Peak memory 202204 kb
Host smart-da9654d1-79b6-49de-9c5e-5d96b20026b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291587512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3291587512
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.4086705162
Short name T713
Test name
Test status
Simulation time 35258575511 ps
CPU time 21.58 seconds
Started Jun 30 06:30:21 PM PDT 24
Finished Jun 30 06:30:44 PM PDT 24
Peak memory 201680 kb
Host smart-de6eab2b-d38f-4d82-9adb-a119e1375189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086705162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.4086705162
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1750101033
Short name T122
Test name
Test status
Simulation time 5049994272 ps
CPU time 6.41 seconds
Started Jun 30 06:30:21 PM PDT 24
Finished Jun 30 06:30:28 PM PDT 24
Peak memory 201676 kb
Host smart-cd9da721-a819-42ec-b274-b3542dfa5a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750101033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1750101033
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1760195409
Short name T486
Test name
Test status
Simulation time 6197214009 ps
CPU time 12.24 seconds
Started Jun 30 06:30:17 PM PDT 24
Finished Jun 30 06:30:30 PM PDT 24
Peak memory 201676 kb
Host smart-4417e971-9fec-40f7-bebc-563e9ebcddbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760195409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1760195409
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1696144221
Short name T33
Test name
Test status
Simulation time 437468546415 ps
CPU time 555.72 seconds
Started Jun 30 06:30:23 PM PDT 24
Finished Jun 30 06:39:39 PM PDT 24
Peak memory 202176 kb
Host smart-c1eb2f99-0c0f-4166-81a7-112d89c7325d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696144221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1696144221
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.90121713
Short name T691
Test name
Test status
Simulation time 347721813258 ps
CPU time 234.28 seconds
Started Jun 30 06:30:21 PM PDT 24
Finished Jun 30 06:34:16 PM PDT 24
Peak memory 211584 kb
Host smart-8e78ea87-248e-48cf-b394-bd4350261ca2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90121713 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.90121713
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.967903884
Short name T515
Test name
Test status
Simulation time 302207701 ps
CPU time 0.81 seconds
Started Jun 30 06:30:27 PM PDT 24
Finished Jun 30 06:30:29 PM PDT 24
Peak memory 201836 kb
Host smart-d46fc589-4930-4027-b475-32c8033bea06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967903884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.967903884
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.4194061561
Short name T238
Test name
Test status
Simulation time 170049787247 ps
CPU time 202.58 seconds
Started Jun 30 06:30:29 PM PDT 24
Finished Jun 30 06:33:52 PM PDT 24
Peak memory 201928 kb
Host smart-83943d52-6162-468a-9f69-7313a5e1fd82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194061561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.4194061561
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1569340378
Short name T259
Test name
Test status
Simulation time 369059401822 ps
CPU time 827.53 seconds
Started Jun 30 06:30:31 PM PDT 24
Finished Jun 30 06:44:19 PM PDT 24
Peak memory 201884 kb
Host smart-1898b7f2-4d96-4358-a948-64a52afea4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569340378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1569340378
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2142345150
Short name T317
Test name
Test status
Simulation time 322701244333 ps
CPU time 412.8 seconds
Started Jun 30 06:30:20 PM PDT 24
Finished Jun 30 06:37:13 PM PDT 24
Peak memory 201868 kb
Host smart-89196ef7-3392-4146-8f19-23dd162c6c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142345150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2142345150
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3777984354
Short name T689
Test name
Test status
Simulation time 334388061292 ps
CPU time 754.35 seconds
Started Jun 30 06:30:26 PM PDT 24
Finished Jun 30 06:43:01 PM PDT 24
Peak memory 201836 kb
Host smart-dd42e19d-f064-4a63-83a9-5b79d3e7a16b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777984354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3777984354
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2146494650
Short name T187
Test name
Test status
Simulation time 325817831052 ps
CPU time 187.1 seconds
Started Jun 30 06:30:23 PM PDT 24
Finished Jun 30 06:33:30 PM PDT 24
Peak memory 201880 kb
Host smart-5599d92f-8e9e-42a4-9101-19f7f43a485e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146494650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2146494650
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.414981156
Short name T509
Test name
Test status
Simulation time 166590630983 ps
CPU time 175.39 seconds
Started Jun 30 06:30:24 PM PDT 24
Finished Jun 30 06:33:20 PM PDT 24
Peak memory 201852 kb
Host smart-e75fe965-a75b-4b64-a0c8-9a83e2453e46
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=414981156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.414981156
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2499812909
Short name T587
Test name
Test status
Simulation time 350402816756 ps
CPU time 82.16 seconds
Started Jun 30 06:30:30 PM PDT 24
Finished Jun 30 06:31:53 PM PDT 24
Peak memory 201936 kb
Host smart-1bb9deca-ae94-4445-a644-7dbfd82bc1b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499812909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2499812909
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.530775593
Short name T547
Test name
Test status
Simulation time 212243978122 ps
CPU time 318.54 seconds
Started Jun 30 06:30:27 PM PDT 24
Finished Jun 30 06:35:46 PM PDT 24
Peak memory 201884 kb
Host smart-f24d0c74-f152-42bb-bc54-c1a55272a6ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530775593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.530775593
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2520342052
Short name T432
Test name
Test status
Simulation time 104112457747 ps
CPU time 438.23 seconds
Started Jun 30 06:30:26 PM PDT 24
Finished Jun 30 06:37:45 PM PDT 24
Peak memory 202216 kb
Host smart-48b7efb3-ddd3-4e0d-b4cc-31c0722dc94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520342052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2520342052
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.374369140
Short name T792
Test name
Test status
Simulation time 33348855919 ps
CPU time 40.6 seconds
Started Jun 30 06:30:28 PM PDT 24
Finished Jun 30 06:31:09 PM PDT 24
Peak memory 201692 kb
Host smart-290e6bf3-a324-46a6-ade4-8ff7c83171c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374369140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.374369140
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2670958453
Short name T369
Test name
Test status
Simulation time 3986493858 ps
CPU time 6.73 seconds
Started Jun 30 06:30:29 PM PDT 24
Finished Jun 30 06:30:36 PM PDT 24
Peak memory 201664 kb
Host smart-d0bf4571-81a6-48b5-b9a6-bcff9d1e1b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670958453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2670958453
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3041336599
Short name T118
Test name
Test status
Simulation time 5781034734 ps
CPU time 4.05 seconds
Started Jun 30 06:30:21 PM PDT 24
Finished Jun 30 06:30:26 PM PDT 24
Peak memory 201688 kb
Host smart-42bbfbf5-879e-4103-9ccd-6cd01a688501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041336599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3041336599
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3364453292
Short name T245
Test name
Test status
Simulation time 257506863271 ps
CPU time 562.32 seconds
Started Jun 30 06:30:28 PM PDT 24
Finished Jun 30 06:39:51 PM PDT 24
Peak memory 210420 kb
Host smart-81e453de-bebb-4ae1-ab28-c3bed9ed44cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364453292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3364453292
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1999822570
Short name T705
Test name
Test status
Simulation time 47042218315 ps
CPU time 132.69 seconds
Started Jun 30 06:30:29 PM PDT 24
Finished Jun 30 06:32:42 PM PDT 24
Peak memory 217616 kb
Host smart-44d94997-560e-4cfd-a0f0-73ee208d1d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999822570 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1999822570
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.165584353
Short name T759
Test name
Test status
Simulation time 442560034 ps
CPU time 0.79 seconds
Started Jun 30 06:27:25 PM PDT 24
Finished Jun 30 06:27:28 PM PDT 24
Peak memory 201616 kb
Host smart-efc86cfe-7ca6-4561-a965-8d36a6864da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165584353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.165584353
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1007307885
Short name T781
Test name
Test status
Simulation time 340936649891 ps
CPU time 384.55 seconds
Started Jun 30 06:27:48 PM PDT 24
Finished Jun 30 06:34:14 PM PDT 24
Peak memory 201880 kb
Host smart-c4be3b99-357b-4287-9148-4a759bd0d0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007307885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1007307885
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1885078443
Short name T121
Test name
Test status
Simulation time 162040667913 ps
CPU time 44.48 seconds
Started Jun 30 06:27:46 PM PDT 24
Finished Jun 30 06:28:32 PM PDT 24
Peak memory 201856 kb
Host smart-6f3c4ff0-0bbf-4d9d-8a6a-531d0fc669de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885078443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1885078443
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1726993069
Short name T162
Test name
Test status
Simulation time 166195806477 ps
CPU time 61.98 seconds
Started Jun 30 06:27:31 PM PDT 24
Finished Jun 30 06:28:33 PM PDT 24
Peak memory 201904 kb
Host smart-4c407517-c613-4b0f-876d-26a38cf354ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726993069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1726993069
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2236189644
Short name T27
Test name
Test status
Simulation time 324951419228 ps
CPU time 736.53 seconds
Started Jun 30 06:27:48 PM PDT 24
Finished Jun 30 06:40:05 PM PDT 24
Peak memory 201792 kb
Host smart-619d4821-4a18-4fb7-bdaf-41204b478343
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236189644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2236189644
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3065103009
Short name T793
Test name
Test status
Simulation time 346498470000 ps
CPU time 414.09 seconds
Started Jun 30 06:27:39 PM PDT 24
Finished Jun 30 06:34:34 PM PDT 24
Peak memory 201936 kb
Host smart-fbf464e6-dde0-496a-b3ee-9a8498383f09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065103009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3065103009
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4287831748
Short name T683
Test name
Test status
Simulation time 405669645687 ps
CPU time 169.04 seconds
Started Jun 30 06:27:40 PM PDT 24
Finished Jun 30 06:30:29 PM PDT 24
Peak memory 201868 kb
Host smart-a72e0bfb-3d56-45f0-81fa-df0832045597
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287831748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4287831748
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.900407636
Short name T638
Test name
Test status
Simulation time 86499856956 ps
CPU time 368.27 seconds
Started Jun 30 06:27:27 PM PDT 24
Finished Jun 30 06:33:41 PM PDT 24
Peak memory 202164 kb
Host smart-32b62500-167b-4529-bfe1-d09687270532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900407636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.900407636
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.47901023
Short name T583
Test name
Test status
Simulation time 41874000950 ps
CPU time 93.98 seconds
Started Jun 30 06:27:34 PM PDT 24
Finished Jun 30 06:29:08 PM PDT 24
Peak memory 201640 kb
Host smart-a0bbe18e-ce09-419f-9b55-a88ffa25fd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47901023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.47901023
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1547018255
Short name T641
Test name
Test status
Simulation time 4707991266 ps
CPU time 3.29 seconds
Started Jun 30 06:27:26 PM PDT 24
Finished Jun 30 06:27:31 PM PDT 24
Peak memory 201688 kb
Host smart-f8a0c3df-2dda-4b84-a063-f3eee7a56e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547018255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1547018255
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3521649730
Short name T92
Test name
Test status
Simulation time 8304550709 ps
CPU time 20.12 seconds
Started Jun 30 06:27:28 PM PDT 24
Finished Jun 30 06:27:49 PM PDT 24
Peak memory 218176 kb
Host smart-32cf03b0-d560-4f42-b82a-b21444a307b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521649730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3521649730
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2656066961
Short name T591
Test name
Test status
Simulation time 5880897056 ps
CPU time 4.75 seconds
Started Jun 30 06:27:46 PM PDT 24
Finished Jun 30 06:27:52 PM PDT 24
Peak memory 201676 kb
Host smart-6e42025f-d961-444b-a456-e57e051e646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656066961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2656066961
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3662345248
Short name T554
Test name
Test status
Simulation time 173767489187 ps
CPU time 70.98 seconds
Started Jun 30 06:27:22 PM PDT 24
Finished Jun 30 06:28:36 PM PDT 24
Peak memory 201876 kb
Host smart-c5559819-d50d-4647-b44a-1f015ebed1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662345248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3662345248
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3717384790
Short name T271
Test name
Test status
Simulation time 94606887619 ps
CPU time 31.15 seconds
Started Jun 30 06:27:48 PM PDT 24
Finished Jun 30 06:28:20 PM PDT 24
Peak memory 218652 kb
Host smart-5b29a0e7-7bd1-4c5a-b06e-3a708642d445
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717384790 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3717384790
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2651204105
Short name T452
Test name
Test status
Simulation time 431040034 ps
CPU time 1.1 seconds
Started Jun 30 06:30:48 PM PDT 24
Finished Jun 30 06:30:49 PM PDT 24
Peak memory 201624 kb
Host smart-3f11f46a-d68f-4497-99a1-54b8c3577929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651204105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2651204105
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1108511158
Short name T581
Test name
Test status
Simulation time 164041189067 ps
CPU time 385.72 seconds
Started Jun 30 06:30:34 PM PDT 24
Finished Jun 30 06:37:01 PM PDT 24
Peak memory 201884 kb
Host smart-cddb22df-2171-4800-b7ed-070a9b0e9582
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108511158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1108511158
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3060020265
Short name T312
Test name
Test status
Simulation time 351270456377 ps
CPU time 763.19 seconds
Started Jun 30 06:30:31 PM PDT 24
Finished Jun 30 06:43:15 PM PDT 24
Peak memory 201872 kb
Host smart-49b5adbe-128f-4a25-a93b-fee7c3ec9d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060020265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3060020265
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2161360860
Short name T185
Test name
Test status
Simulation time 334292190937 ps
CPU time 212.33 seconds
Started Jun 30 06:30:31 PM PDT 24
Finished Jun 30 06:34:04 PM PDT 24
Peak memory 201880 kb
Host smart-48df1980-aa98-4517-a34e-09b89a2cbe1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161360860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2161360860
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2236655071
Short name T400
Test name
Test status
Simulation time 327204138408 ps
CPU time 195.55 seconds
Started Jun 30 06:30:31 PM PDT 24
Finished Jun 30 06:33:47 PM PDT 24
Peak memory 201844 kb
Host smart-c8943d72-2c10-410f-acb0-40c8fd9cf17e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236655071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2236655071
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3276003309
Short name T530
Test name
Test status
Simulation time 159178083487 ps
CPU time 186.88 seconds
Started Jun 30 06:30:28 PM PDT 24
Finished Jun 30 06:33:36 PM PDT 24
Peak memory 201972 kb
Host smart-dc28b8ef-2f79-460b-8942-d6ddbb8cdbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276003309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3276003309
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3432436131
Short name T545
Test name
Test status
Simulation time 158782108649 ps
CPU time 89.91 seconds
Started Jun 30 06:30:32 PM PDT 24
Finished Jun 30 06:32:02 PM PDT 24
Peak memory 201820 kb
Host smart-dd4518f8-d449-4223-8502-57706a40b2f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432436131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3432436131
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1389417579
Short name T153
Test name
Test status
Simulation time 177714107905 ps
CPU time 426.4 seconds
Started Jun 30 06:30:34 PM PDT 24
Finished Jun 30 06:37:41 PM PDT 24
Peak memory 201880 kb
Host smart-9a07b645-34dc-41df-850f-d9d6ff582889
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389417579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1389417579
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3000734708
Short name T124
Test name
Test status
Simulation time 614812861348 ps
CPU time 734.87 seconds
Started Jun 30 06:30:34 PM PDT 24
Finished Jun 30 06:42:49 PM PDT 24
Peak memory 201880 kb
Host smart-807d5fe9-bab4-4a10-b267-113210547366
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000734708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3000734708
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.46430029
Short name T534
Test name
Test status
Simulation time 73851071972 ps
CPU time 319.57 seconds
Started Jun 30 06:30:45 PM PDT 24
Finished Jun 30 06:36:05 PM PDT 24
Peak memory 202176 kb
Host smart-348fdd12-4941-4827-9ce8-be3a88464a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46430029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.46430029
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3549788722
Short name T538
Test name
Test status
Simulation time 35356215473 ps
CPU time 35.31 seconds
Started Jun 30 06:30:35 PM PDT 24
Finished Jun 30 06:31:11 PM PDT 24
Peak memory 201624 kb
Host smart-df6907a1-62b0-4765-bd98-0a6093337d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549788722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3549788722
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1784627792
Short name T622
Test name
Test status
Simulation time 3379382897 ps
CPU time 1.73 seconds
Started Jun 30 06:30:35 PM PDT 24
Finished Jun 30 06:30:37 PM PDT 24
Peak memory 201668 kb
Host smart-4f50a5d9-a90e-4ff5-84a5-54691e9b28b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784627792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1784627792
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1923457974
Short name T635
Test name
Test status
Simulation time 6007231495 ps
CPU time 1.86 seconds
Started Jun 30 06:30:27 PM PDT 24
Finished Jun 30 06:30:29 PM PDT 24
Peak memory 201660 kb
Host smart-c7a3cc56-2b15-4675-8157-a3a71099b0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923457974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1923457974
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2226395312
Short name T14
Test name
Test status
Simulation time 51521366229 ps
CPU time 104.02 seconds
Started Jun 30 06:30:48 PM PDT 24
Finished Jun 30 06:32:33 PM PDT 24
Peak memory 210260 kb
Host smart-c71a8fbd-b2b5-4c81-ae19-e1fb18c1d8d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226395312 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2226395312
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3111401844
Short name T85
Test name
Test status
Simulation time 445326625 ps
CPU time 0.87 seconds
Started Jun 30 06:30:49 PM PDT 24
Finished Jun 30 06:30:51 PM PDT 24
Peak memory 201632 kb
Host smart-7c521284-1506-4ba7-b96f-2aee98d20ae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111401844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3111401844
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2179282806
Short name T257
Test name
Test status
Simulation time 560292957040 ps
CPU time 1324.73 seconds
Started Jun 30 06:30:43 PM PDT 24
Finished Jun 30 06:52:49 PM PDT 24
Peak memory 201860 kb
Host smart-098e7bda-18ab-48c0-a509-244f288fcbc0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179282806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2179282806
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.880517256
Short name T274
Test name
Test status
Simulation time 160504433590 ps
CPU time 28.17 seconds
Started Jun 30 06:30:45 PM PDT 24
Finished Jun 30 06:31:13 PM PDT 24
Peak memory 201884 kb
Host smart-a5723130-ffc1-4eac-abbe-ef3b9c5366e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880517256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.880517256
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2853001804
Short name T548
Test name
Test status
Simulation time 160168246064 ps
CPU time 183 seconds
Started Jun 30 06:30:48 PM PDT 24
Finished Jun 30 06:33:51 PM PDT 24
Peak memory 201884 kb
Host smart-81f340df-b792-4636-8e38-c7b4089796cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853001804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2853001804
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1079735897
Short name T389
Test name
Test status
Simulation time 327093689436 ps
CPU time 773.61 seconds
Started Jun 30 06:30:47 PM PDT 24
Finished Jun 30 06:43:41 PM PDT 24
Peak memory 201844 kb
Host smart-25db837d-97e6-4dcd-9fa3-e39a0dfeea24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079735897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1079735897
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1681408262
Short name T464
Test name
Test status
Simulation time 329223782929 ps
CPU time 201.25 seconds
Started Jun 30 06:30:46 PM PDT 24
Finished Jun 30 06:34:08 PM PDT 24
Peak memory 201940 kb
Host smart-2602b080-4789-48bd-98ab-9f576514d341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681408262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1681408262
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1618301770
Short name T743
Test name
Test status
Simulation time 165064458414 ps
CPU time 25.06 seconds
Started Jun 30 06:30:37 PM PDT 24
Finished Jun 30 06:31:02 PM PDT 24
Peak memory 201860 kb
Host smart-e465d3db-f88b-4429-9587-a9b2358d9611
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618301770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1618301770
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3389290130
Short name T479
Test name
Test status
Simulation time 590445571832 ps
CPU time 328.86 seconds
Started Jun 30 06:30:42 PM PDT 24
Finished Jun 30 06:36:12 PM PDT 24
Peak memory 201828 kb
Host smart-aadd5648-efda-4b93-82c4-1b28fb3f92f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389290130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3389290130
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3702390103
Short name T766
Test name
Test status
Simulation time 76211015838 ps
CPU time 269.93 seconds
Started Jun 30 06:30:44 PM PDT 24
Finished Jun 30 06:35:14 PM PDT 24
Peak memory 202228 kb
Host smart-8c130d0f-dffa-4443-b307-3be4856ad7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702390103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3702390103
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.742964006
Short name T372
Test name
Test status
Simulation time 32309240993 ps
CPU time 17.85 seconds
Started Jun 30 06:30:45 PM PDT 24
Finished Jun 30 06:31:04 PM PDT 24
Peak memory 201668 kb
Host smart-7004c4d9-5741-4f28-b388-b0ac8142b2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742964006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.742964006
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3669294738
Short name T475
Test name
Test status
Simulation time 4155857674 ps
CPU time 4.83 seconds
Started Jun 30 06:30:41 PM PDT 24
Finished Jun 30 06:30:46 PM PDT 24
Peak memory 201680 kb
Host smart-13dd37bc-8c8f-45da-a3f9-950f73d1eb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669294738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3669294738
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2097862707
Short name T473
Test name
Test status
Simulation time 5905900714 ps
CPU time 1.46 seconds
Started Jun 30 06:30:48 PM PDT 24
Finished Jun 30 06:30:50 PM PDT 24
Peak memory 201672 kb
Host smart-3862a698-2c1c-45f1-8ab8-3669038aea1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097862707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2097862707
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2467448512
Short name T51
Test name
Test status
Simulation time 307497393672 ps
CPU time 205.48 seconds
Started Jun 30 06:30:43 PM PDT 24
Finished Jun 30 06:34:09 PM PDT 24
Peak memory 210508 kb
Host smart-0d11d549-e7d2-4cbf-ab50-76861d156671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467448512 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2467448512
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3572281404
Short name T467
Test name
Test status
Simulation time 437552357 ps
CPU time 1.62 seconds
Started Jun 30 06:30:56 PM PDT 24
Finished Jun 30 06:30:58 PM PDT 24
Peak memory 201608 kb
Host smart-fdf38e0d-f489-4d24-bbe4-4a518949f1ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572281404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3572281404
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3238523745
Short name T255
Test name
Test status
Simulation time 164048434020 ps
CPU time 175.45 seconds
Started Jun 30 06:30:48 PM PDT 24
Finished Jun 30 06:33:44 PM PDT 24
Peak memory 201872 kb
Host smart-9d9de06f-b18d-4f06-9568-c7c76bc8321a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238523745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3238523745
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.56985224
Short name T747
Test name
Test status
Simulation time 169698478890 ps
CPU time 376.03 seconds
Started Jun 30 06:30:49 PM PDT 24
Finished Jun 30 06:37:07 PM PDT 24
Peak memory 201896 kb
Host smart-e3ef008b-2e30-4293-ad22-f2274bcef856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56985224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.56985224
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.918418703
Short name T657
Test name
Test status
Simulation time 488756053218 ps
CPU time 586.93 seconds
Started Jun 30 06:30:53 PM PDT 24
Finished Jun 30 06:40:41 PM PDT 24
Peak memory 201904 kb
Host smart-3a8a9185-6640-43cf-ab58-01b5067d5624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918418703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.918418703
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.653779570
Short name T458
Test name
Test status
Simulation time 160619833434 ps
CPU time 367.32 seconds
Started Jun 30 06:30:49 PM PDT 24
Finished Jun 30 06:36:57 PM PDT 24
Peak memory 201812 kb
Host smart-2c727453-0f02-4548-925c-abfd90ac37bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=653779570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.653779570
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3642296266
Short name T724
Test name
Test status
Simulation time 483074354847 ps
CPU time 1082.4 seconds
Started Jun 30 06:30:48 PM PDT 24
Finished Jun 30 06:48:51 PM PDT 24
Peak memory 201832 kb
Host smart-9877acfc-106d-49a8-addf-d35d14201f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642296266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3642296266
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.676212587
Short name T703
Test name
Test status
Simulation time 165023811117 ps
CPU time 79.48 seconds
Started Jun 30 06:30:48 PM PDT 24
Finished Jun 30 06:32:09 PM PDT 24
Peak memory 201852 kb
Host smart-4bea5271-e747-474b-a1cb-43d45178aa49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=676212587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.676212587
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3305758977
Short name T270
Test name
Test status
Simulation time 542042713979 ps
CPU time 1186.09 seconds
Started Jun 30 06:30:48 PM PDT 24
Finished Jun 30 06:50:35 PM PDT 24
Peak memory 201900 kb
Host smart-3cabd702-2a66-4b5f-ad18-f504fc86773d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305758977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3305758977
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1345415244
Short name T366
Test name
Test status
Simulation time 400970855804 ps
CPU time 216.75 seconds
Started Jun 30 06:30:53 PM PDT 24
Finished Jun 30 06:34:31 PM PDT 24
Peak memory 201836 kb
Host smart-2b99b930-a0ff-4cbb-9432-38243de2c8d7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345415244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1345415244
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3729013776
Short name T666
Test name
Test status
Simulation time 120094736238 ps
CPU time 630.93 seconds
Started Jun 30 06:30:56 PM PDT 24
Finished Jun 30 06:41:27 PM PDT 24
Peak memory 202280 kb
Host smart-d04da6fc-64c6-4bed-a534-b5802d70de10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729013776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3729013776
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3207919761
Short name T779
Test name
Test status
Simulation time 22961196061 ps
CPU time 56.64 seconds
Started Jun 30 06:30:54 PM PDT 24
Finished Jun 30 06:31:51 PM PDT 24
Peak memory 201676 kb
Host smart-f21b8ad3-6475-453b-b579-d1b732bb744b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207919761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3207919761
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.473342359
Short name T110
Test name
Test status
Simulation time 3042704302 ps
CPU time 3.39 seconds
Started Jun 30 06:30:52 PM PDT 24
Finished Jun 30 06:30:56 PM PDT 24
Peak memory 201656 kb
Host smart-462ba12c-f4f6-4345-b638-f863dc9147b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473342359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.473342359
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3750642994
Short name T510
Test name
Test status
Simulation time 5982807422 ps
CPU time 15.13 seconds
Started Jun 30 06:30:52 PM PDT 24
Finished Jun 30 06:31:08 PM PDT 24
Peak memory 201656 kb
Host smart-2627b9b2-feed-42cc-b383-f31970a8d15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750642994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3750642994
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.26792404
Short name T15
Test name
Test status
Simulation time 220140482207 ps
CPU time 124.71 seconds
Started Jun 30 06:30:56 PM PDT 24
Finished Jun 30 06:33:01 PM PDT 24
Peak memory 210508 kb
Host smart-effd4292-1a1e-488c-9747-ae3daced59ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26792404 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.26792404
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.695237739
Short name T647
Test name
Test status
Simulation time 424486963 ps
CPU time 1.63 seconds
Started Jun 30 06:31:01 PM PDT 24
Finished Jun 30 06:31:03 PM PDT 24
Peak memory 201640 kb
Host smart-ca3e7279-d274-4a75-9a01-b6597090afe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695237739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.695237739
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1227046162
Short name T168
Test name
Test status
Simulation time 351514000062 ps
CPU time 205.78 seconds
Started Jun 30 06:31:03 PM PDT 24
Finished Jun 30 06:34:29 PM PDT 24
Peak memory 201888 kb
Host smart-af05cdb0-ab95-41ad-863e-97b2551a2d21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227046162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1227046162
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.229760088
Short name T632
Test name
Test status
Simulation time 189614478174 ps
CPU time 109.09 seconds
Started Jun 30 06:31:00 PM PDT 24
Finished Jun 30 06:32:50 PM PDT 24
Peak memory 201864 kb
Host smart-7531d258-fa28-4171-bf12-13d00f09dfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229760088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.229760088
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.4181319030
Short name T403
Test name
Test status
Simulation time 493572003740 ps
CPU time 1224.35 seconds
Started Jun 30 06:30:54 PM PDT 24
Finished Jun 30 06:51:20 PM PDT 24
Peak memory 201820 kb
Host smart-313cb306-2b58-4a72-8195-6b07a4219b10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181319030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.4181319030
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3857644513
Short name T288
Test name
Test status
Simulation time 167043115333 ps
CPU time 180.91 seconds
Started Jun 30 06:30:56 PM PDT 24
Finished Jun 30 06:33:58 PM PDT 24
Peak memory 201952 kb
Host smart-dca5508a-b92b-4279-8956-ee131c0799e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857644513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3857644513
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1994201175
Short name T580
Test name
Test status
Simulation time 326016745619 ps
CPU time 732.97 seconds
Started Jun 30 06:30:54 PM PDT 24
Finished Jun 30 06:43:08 PM PDT 24
Peak memory 201792 kb
Host smart-918afb7f-f01d-4643-8b25-f92aedb2195a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994201175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1994201175
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1166357003
Short name T796
Test name
Test status
Simulation time 596782844476 ps
CPU time 1343.98 seconds
Started Jun 30 06:31:03 PM PDT 24
Finished Jun 30 06:53:28 PM PDT 24
Peak memory 201916 kb
Host smart-74b05b74-c50b-4012-9af3-440cafd0cd76
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166357003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1166357003
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.11246686
Short name T354
Test name
Test status
Simulation time 111010578292 ps
CPU time 609.77 seconds
Started Jun 30 06:31:05 PM PDT 24
Finished Jun 30 06:41:16 PM PDT 24
Peak memory 202184 kb
Host smart-dcd8069d-55ef-4a0e-8e65-c3351a49318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11246686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.11246686
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1257568160
Short name T496
Test name
Test status
Simulation time 38997950431 ps
CPU time 49.68 seconds
Started Jun 30 06:31:00 PM PDT 24
Finished Jun 30 06:31:50 PM PDT 24
Peak memory 201640 kb
Host smart-da8ee94f-6995-4756-a03c-25effd565568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257568160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1257568160
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2126527610
Short name T444
Test name
Test status
Simulation time 4347737287 ps
CPU time 3.11 seconds
Started Jun 30 06:30:59 PM PDT 24
Finished Jun 30 06:31:03 PM PDT 24
Peak memory 201632 kb
Host smart-9b9dcfb8-db8d-4a28-9a97-f17244c1aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126527610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2126527610
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1598201247
Short name T654
Test name
Test status
Simulation time 5961189042 ps
CPU time 4.29 seconds
Started Jun 30 06:30:54 PM PDT 24
Finished Jun 30 06:30:59 PM PDT 24
Peak memory 201668 kb
Host smart-985b02dc-164d-4817-b158-7306ca6d2b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598201247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1598201247
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.328753030
Short name T673
Test name
Test status
Simulation time 378531292236 ps
CPU time 297.51 seconds
Started Jun 30 06:31:01 PM PDT 24
Finished Jun 30 06:35:59 PM PDT 24
Peak memory 201932 kb
Host smart-1cd68876-3830-4986-a70d-22a55d55a078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328753030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
328753030
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1893313778
Short name T625
Test name
Test status
Simulation time 411603437 ps
CPU time 0.86 seconds
Started Jun 30 06:31:15 PM PDT 24
Finished Jun 30 06:31:17 PM PDT 24
Peak memory 201552 kb
Host smart-320a314f-9c36-424d-be11-7688049a642e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893313778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1893313778
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2621307781
Short name T579
Test name
Test status
Simulation time 184606932520 ps
CPU time 9.57 seconds
Started Jun 30 06:31:06 PM PDT 24
Finished Jun 30 06:31:16 PM PDT 24
Peak memory 201880 kb
Host smart-aeef319d-4e05-4a23-8378-6449154396ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621307781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2621307781
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.179026191
Short name T333
Test name
Test status
Simulation time 160656144297 ps
CPU time 34.41 seconds
Started Jun 30 06:31:05 PM PDT 24
Finished Jun 30 06:31:41 PM PDT 24
Peak memory 201876 kb
Host smart-94710fd3-8b30-4ae7-8fb8-0677f48a8418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179026191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.179026191
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1305187830
Short name T720
Test name
Test status
Simulation time 162980290360 ps
CPU time 195.01 seconds
Started Jun 30 06:31:05 PM PDT 24
Finished Jun 30 06:34:22 PM PDT 24
Peak memory 201784 kb
Host smart-8fbdf3c7-673d-4800-97cc-461a72e7ab24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305187830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1305187830
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.255813745
Short name T327
Test name
Test status
Simulation time 324472246501 ps
CPU time 190.62 seconds
Started Jun 30 06:31:07 PM PDT 24
Finished Jun 30 06:34:18 PM PDT 24
Peak memory 201836 kb
Host smart-197cc1f0-6d7c-4a2f-8987-a96cf8b4d7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255813745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.255813745
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.919784408
Short name T470
Test name
Test status
Simulation time 499778384587 ps
CPU time 299.76 seconds
Started Jun 30 06:31:04 PM PDT 24
Finished Jun 30 06:36:04 PM PDT 24
Peak memory 201868 kb
Host smart-316418fc-8a1b-484b-87b2-b72aca743f45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=919784408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.919784408
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3057443410
Short name T708
Test name
Test status
Simulation time 180447302531 ps
CPU time 76.99 seconds
Started Jun 30 06:31:05 PM PDT 24
Finished Jun 30 06:32:23 PM PDT 24
Peak memory 201856 kb
Host smart-a29c04e0-840c-4eb5-af19-d7af500887d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057443410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3057443410
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2092713715
Short name T593
Test name
Test status
Simulation time 195047768774 ps
CPU time 136 seconds
Started Jun 30 06:31:04 PM PDT 24
Finished Jun 30 06:33:21 PM PDT 24
Peak memory 201856 kb
Host smart-669fe6ea-b3a2-4122-bdfd-0d9c11162d17
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092713715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2092713715
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2334866022
Short name T402
Test name
Test status
Simulation time 123438207970 ps
CPU time 636.83 seconds
Started Jun 30 06:31:15 PM PDT 24
Finished Jun 30 06:41:54 PM PDT 24
Peak memory 202216 kb
Host smart-f5b91a79-b45f-41a7-aa9d-62fb4cac5d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334866022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2334866022
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.4220402969
Short name T117
Test name
Test status
Simulation time 25527511013 ps
CPU time 21.42 seconds
Started Jun 30 06:31:14 PM PDT 24
Finished Jun 30 06:31:37 PM PDT 24
Peak memory 201676 kb
Host smart-43ee45cd-cd6e-4f23-a566-89c0d00ea66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220402969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.4220402969
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2790623055
Short name T495
Test name
Test status
Simulation time 5705035773 ps
CPU time 3.09 seconds
Started Jun 30 06:31:05 PM PDT 24
Finished Jun 30 06:31:09 PM PDT 24
Peak memory 201684 kb
Host smart-10e1230a-22bc-4c37-8421-c8cd9b0e7d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790623055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2790623055
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1141521726
Short name T656
Test name
Test status
Simulation time 5689679767 ps
CPU time 4.49 seconds
Started Jun 30 06:31:04 PM PDT 24
Finished Jun 30 06:31:09 PM PDT 24
Peak memory 201672 kb
Host smart-72c2eedb-d941-4b1d-867b-cb8ab4beb803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141521726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1141521726
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1974032801
Short name T34
Test name
Test status
Simulation time 308125214544 ps
CPU time 592.83 seconds
Started Jun 30 06:31:15 PM PDT 24
Finished Jun 30 06:41:10 PM PDT 24
Peak memory 218588 kb
Host smart-06ad5fc3-b204-49c5-99c0-1a0ff18aa444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974032801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1974032801
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2702147846
Short name T221
Test name
Test status
Simulation time 398267146758 ps
CPU time 548.85 seconds
Started Jun 30 06:31:14 PM PDT 24
Finished Jun 30 06:40:25 PM PDT 24
Peak memory 210508 kb
Host smart-3095f8b9-574c-41cd-9943-c74a67171d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702147846 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2702147846
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1078129913
Short name T453
Test name
Test status
Simulation time 327105154 ps
CPU time 0.83 seconds
Started Jun 30 06:31:24 PM PDT 24
Finished Jun 30 06:31:25 PM PDT 24
Peak memory 201596 kb
Host smart-c19886b8-ba5f-4d83-a389-1913753c3d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078129913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1078129913
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2617725024
Short name T180
Test name
Test status
Simulation time 513246072704 ps
CPU time 97.46 seconds
Started Jun 30 06:31:15 PM PDT 24
Finished Jun 30 06:32:54 PM PDT 24
Peak memory 201740 kb
Host smart-f89e1933-c472-4f76-845b-c3dcaea34c9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617725024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2617725024
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2341502542
Short name T709
Test name
Test status
Simulation time 374161726735 ps
CPU time 885.74 seconds
Started Jun 30 06:31:23 PM PDT 24
Finished Jun 30 06:46:10 PM PDT 24
Peak memory 201872 kb
Host smart-a029e0dd-f3c8-4894-8660-e644acbef35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341502542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2341502542
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1830334327
Short name T52
Test name
Test status
Simulation time 164171673425 ps
CPU time 369.53 seconds
Started Jun 30 06:31:16 PM PDT 24
Finished Jun 30 06:37:27 PM PDT 24
Peak memory 201888 kb
Host smart-b9d1d0c2-22ef-4365-8c74-fa3f745c0cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830334327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1830334327
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1418497756
Short name T569
Test name
Test status
Simulation time 325644456895 ps
CPU time 69.08 seconds
Started Jun 30 06:31:18 PM PDT 24
Finished Jun 30 06:32:28 PM PDT 24
Peak memory 201844 kb
Host smart-474cc9b1-7211-4741-bcae-2eaeaefe1d47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418497756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1418497756
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4176464285
Short name T614
Test name
Test status
Simulation time 162452025090 ps
CPU time 93.63 seconds
Started Jun 30 06:31:15 PM PDT 24
Finished Jun 30 06:32:51 PM PDT 24
Peak memory 201900 kb
Host smart-ffb7a6e3-6f39-46bb-9aed-3268301c2e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176464285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4176464285
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.4072159537
Short name T451
Test name
Test status
Simulation time 330226597342 ps
CPU time 241.94 seconds
Started Jun 30 06:31:16 PM PDT 24
Finished Jun 30 06:35:19 PM PDT 24
Peak memory 201828 kb
Host smart-25183f82-619f-458f-92ad-656e3d1b79af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072159537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.4072159537
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.140315770
Short name T194
Test name
Test status
Simulation time 373810573512 ps
CPU time 206.61 seconds
Started Jun 30 06:31:18 PM PDT 24
Finished Jun 30 06:34:45 PM PDT 24
Peak memory 201948 kb
Host smart-2e768aa7-0b9d-46a9-a3f3-cf99299d66c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140315770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.140315770
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.692819032
Short name T405
Test name
Test status
Simulation time 604907940865 ps
CPU time 98.95 seconds
Started Jun 30 06:31:17 PM PDT 24
Finished Jun 30 06:32:57 PM PDT 24
Peak memory 201844 kb
Host smart-fd3a864d-f85d-43a8-82dc-1d4980df9d5f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692819032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.692819032
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1671925458
Short name T203
Test name
Test status
Simulation time 79878256637 ps
CPU time 330.45 seconds
Started Jun 30 06:31:24 PM PDT 24
Finished Jun 30 06:36:55 PM PDT 24
Peak memory 202188 kb
Host smart-5c6f5f5f-c672-49e5-8d56-a45739f43749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671925458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1671925458
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.216567434
Short name T610
Test name
Test status
Simulation time 46190210642 ps
CPU time 100.72 seconds
Started Jun 30 06:31:26 PM PDT 24
Finished Jun 30 06:33:07 PM PDT 24
Peak memory 201688 kb
Host smart-691e42c1-28f1-4596-a935-509ba8b4bef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216567434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.216567434
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.901550103
Short name T107
Test name
Test status
Simulation time 4371678532 ps
CPU time 9.67 seconds
Started Jun 30 06:31:25 PM PDT 24
Finished Jun 30 06:31:35 PM PDT 24
Peak memory 201684 kb
Host smart-5118f3e8-1e43-48e2-8491-f609185f7dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901550103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.901550103
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2784016375
Short name T785
Test name
Test status
Simulation time 5921396954 ps
CPU time 13.83 seconds
Started Jun 30 06:31:14 PM PDT 24
Finished Jun 30 06:31:30 PM PDT 24
Peak memory 201672 kb
Host smart-eaa516e8-38de-49da-8c48-19befed5cabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784016375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2784016375
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2248411859
Short name T48
Test name
Test status
Simulation time 104087185689 ps
CPU time 215.19 seconds
Started Jun 30 06:31:25 PM PDT 24
Finished Jun 30 06:35:01 PM PDT 24
Peak memory 210516 kb
Host smart-8572a9b4-a4a1-4fed-908b-6680ede3dc6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248411859 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2248411859
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.4201638322
Short name T542
Test name
Test status
Simulation time 370911393 ps
CPU time 1.42 seconds
Started Jun 30 06:31:30 PM PDT 24
Finished Jun 30 06:31:32 PM PDT 24
Peak memory 201560 kb
Host smart-6f4d2aae-589a-4748-a114-a28a42074baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201638322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.4201638322
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.27043772
Short name T284
Test name
Test status
Simulation time 525910386426 ps
CPU time 291.74 seconds
Started Jun 30 06:31:37 PM PDT 24
Finished Jun 30 06:36:29 PM PDT 24
Peak memory 201936 kb
Host smart-1bdf397f-d7ed-4781-87ca-cf1ac010e090
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27043772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gatin
g.27043772
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1113619316
Short name T279
Test name
Test status
Simulation time 501649005245 ps
CPU time 1120.02 seconds
Started Jun 30 06:31:28 PM PDT 24
Finished Jun 30 06:50:09 PM PDT 24
Peak memory 201948 kb
Host smart-e2bed72e-04d7-44e2-a7c6-ad5b4ee270fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113619316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1113619316
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.4147745891
Short name T568
Test name
Test status
Simulation time 326545415786 ps
CPU time 776.65 seconds
Started Jun 30 06:31:31 PM PDT 24
Finished Jun 30 06:44:28 PM PDT 24
Peak memory 201776 kb
Host smart-ede52afc-ec34-4348-a4bc-2553a86719a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147745891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.4147745891
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2312822209
Short name T12
Test name
Test status
Simulation time 164293954261 ps
CPU time 259.94 seconds
Started Jun 30 06:31:29 PM PDT 24
Finished Jun 30 06:35:49 PM PDT 24
Peak memory 201944 kb
Host smart-d4b280a1-868a-4f1d-9031-9f04c150ef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312822209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2312822209
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2416115651
Short name T54
Test name
Test status
Simulation time 489510351904 ps
CPU time 1075.66 seconds
Started Jun 30 06:31:31 PM PDT 24
Finished Jun 30 06:49:27 PM PDT 24
Peak memory 201848 kb
Host smart-faee5e7d-ded6-471c-a773-ec3ce8cbcc05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416115651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2416115651
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.4019976462
Short name T636
Test name
Test status
Simulation time 195474267996 ps
CPU time 208.1 seconds
Started Jun 30 06:31:29 PM PDT 24
Finished Jun 30 06:34:59 PM PDT 24
Peak memory 201860 kb
Host smart-50062d37-a9fd-4814-8302-867ac0f8205b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019976462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.4019976462
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1746939607
Short name T352
Test name
Test status
Simulation time 109871155611 ps
CPU time 442.11 seconds
Started Jun 30 06:31:37 PM PDT 24
Finished Jun 30 06:39:00 PM PDT 24
Peak memory 202260 kb
Host smart-8c54a9ae-bde8-4d2e-9fa9-188e0b8cf0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746939607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1746939607
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4130291554
Short name T514
Test name
Test status
Simulation time 39991000222 ps
CPU time 7.93 seconds
Started Jun 30 06:31:34 PM PDT 24
Finished Jun 30 06:31:42 PM PDT 24
Peak memory 201692 kb
Host smart-7531f38f-5a64-4028-8dfa-7c1bcd860e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130291554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4130291554
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.4179287285
Short name T619
Test name
Test status
Simulation time 5064619265 ps
CPU time 3.21 seconds
Started Jun 30 06:31:33 PM PDT 24
Finished Jun 30 06:31:37 PM PDT 24
Peak memory 201680 kb
Host smart-73a50d0d-91b9-4027-84e4-926c738bef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179287285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.4179287285
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3984322958
Short name T687
Test name
Test status
Simulation time 6178513177 ps
CPU time 8.15 seconds
Started Jun 30 06:31:24 PM PDT 24
Finished Jun 30 06:31:33 PM PDT 24
Peak memory 201680 kb
Host smart-a599cb47-716d-43be-b0fa-02f4f479229d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984322958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3984322958
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1696386101
Short name T597
Test name
Test status
Simulation time 209867869741 ps
CPU time 220.13 seconds
Started Jun 30 06:31:30 PM PDT 24
Finished Jun 30 06:35:11 PM PDT 24
Peak memory 201844 kb
Host smart-c8686d3e-9a12-4b23-b67f-b194a72f0466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696386101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1696386101
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.768951542
Short name T334
Test name
Test status
Simulation time 197105861412 ps
CPU time 614.23 seconds
Started Jun 30 06:31:30 PM PDT 24
Finished Jun 30 06:41:45 PM PDT 24
Peak memory 217656 kb
Host smart-5ea12626-137a-4c69-a2c3-53328e0921c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768951542 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.768951542
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2936877033
Short name T425
Test name
Test status
Simulation time 485702231 ps
CPU time 1.1 seconds
Started Jun 30 06:31:40 PM PDT 24
Finished Jun 30 06:31:41 PM PDT 24
Peak memory 201624 kb
Host smart-48468d28-eb07-4180-bf37-7371457f744c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936877033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2936877033
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3319159746
Short name T598
Test name
Test status
Simulation time 498768947235 ps
CPU time 110.61 seconds
Started Jun 30 06:31:38 PM PDT 24
Finished Jun 30 06:33:29 PM PDT 24
Peak memory 201892 kb
Host smart-e578d16e-36e4-4aa6-a9d6-b8175eac5b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319159746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3319159746
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3364503216
Short name T749
Test name
Test status
Simulation time 167016746265 ps
CPU time 197.7 seconds
Started Jun 30 06:31:32 PM PDT 24
Finished Jun 30 06:34:50 PM PDT 24
Peak memory 201824 kb
Host smart-784fd9ee-bf95-4e76-9670-efdbe3e9b750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364503216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3364503216
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3663759783
Short name T359
Test name
Test status
Simulation time 490651128175 ps
CPU time 1039.88 seconds
Started Jun 30 06:31:38 PM PDT 24
Finished Jun 30 06:48:59 PM PDT 24
Peak memory 201832 kb
Host smart-6cedd5a7-e298-4bde-8b4c-6a4d2b0e0cdd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663759783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3663759783
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1019707722
Short name T378
Test name
Test status
Simulation time 494624530242 ps
CPU time 448.54 seconds
Started Jun 30 06:31:33 PM PDT 24
Finished Jun 30 06:39:01 PM PDT 24
Peak memory 201932 kb
Host smart-22fcdffa-4094-47d9-8b8e-debbc5314c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019707722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1019707722
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3104864016
Short name T655
Test name
Test status
Simulation time 160817801912 ps
CPU time 20.03 seconds
Started Jun 30 06:31:37 PM PDT 24
Finished Jun 30 06:31:57 PM PDT 24
Peak memory 201900 kb
Host smart-b85150c0-8e32-4e63-90cd-3afe36b6959c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104864016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3104864016
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3791325578
Short name T234
Test name
Test status
Simulation time 360818845691 ps
CPU time 821.83 seconds
Started Jun 30 06:31:34 PM PDT 24
Finished Jun 30 06:45:16 PM PDT 24
Peak memory 201948 kb
Host smart-93f6e549-a44d-4e37-aa3b-9de0cd153005
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791325578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3791325578
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.390988104
Short name T693
Test name
Test status
Simulation time 193060533996 ps
CPU time 401.02 seconds
Started Jun 30 06:31:39 PM PDT 24
Finished Jun 30 06:38:20 PM PDT 24
Peak memory 201848 kb
Host smart-6b67bf15-b367-4ec6-b654-b736d737dd5a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390988104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.390988104
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2467448226
Short name T355
Test name
Test status
Simulation time 110055963144 ps
CPU time 433.72 seconds
Started Jun 30 06:31:39 PM PDT 24
Finished Jun 30 06:38:53 PM PDT 24
Peak memory 202132 kb
Host smart-159398e9-1270-4b77-9fae-43f669caeb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467448226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2467448226
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2485080937
Short name T461
Test name
Test status
Simulation time 45763127478 ps
CPU time 28.81 seconds
Started Jun 30 06:31:47 PM PDT 24
Finished Jun 30 06:32:16 PM PDT 24
Peak memory 201680 kb
Host smart-a4b44641-7828-4f3b-88c0-deef3de87890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485080937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2485080937
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2348384178
Short name T698
Test name
Test status
Simulation time 4877924693 ps
CPU time 8.23 seconds
Started Jun 30 06:31:41 PM PDT 24
Finished Jun 30 06:31:50 PM PDT 24
Peak memory 201676 kb
Host smart-7aa8606b-14e1-4556-bd1d-e2a3213fffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348384178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2348384178
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2699229583
Short name T455
Test name
Test status
Simulation time 5983511193 ps
CPU time 7.68 seconds
Started Jun 30 06:31:36 PM PDT 24
Finished Jun 30 06:31:45 PM PDT 24
Peak memory 201676 kb
Host smart-f52f381d-36c7-4053-b62f-d8585c97842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699229583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2699229583
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3788891810
Short name T307
Test name
Test status
Simulation time 370814691963 ps
CPU time 74.76 seconds
Started Jun 30 06:31:45 PM PDT 24
Finished Jun 30 06:33:01 PM PDT 24
Peak memory 201852 kb
Host smart-d14fce3e-edf4-4ecd-8351-b5de0896b5d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788891810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3788891810
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1101369779
Short name T735
Test name
Test status
Simulation time 29621208097 ps
CPU time 62.14 seconds
Started Jun 30 06:31:40 PM PDT 24
Finished Jun 30 06:32:43 PM PDT 24
Peak memory 210256 kb
Host smart-c5aff402-e918-4bcc-a51a-6f3568baad1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101369779 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1101369779
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1414425916
Short name T756
Test name
Test status
Simulation time 456754195 ps
CPU time 1.54 seconds
Started Jun 30 06:31:51 PM PDT 24
Finished Jun 30 06:31:53 PM PDT 24
Peak memory 201624 kb
Host smart-baa23d78-f962-4f6e-a87a-43d9a6831732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414425916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1414425916
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1945355182
Short name T173
Test name
Test status
Simulation time 358271945890 ps
CPU time 851.63 seconds
Started Jun 30 06:31:48 PM PDT 24
Finished Jun 30 06:46:00 PM PDT 24
Peak memory 201912 kb
Host smart-33e837b0-1328-4aad-b3ba-a47f76cecb74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945355182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1945355182
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3294515862
Short name T651
Test name
Test status
Simulation time 159052444022 ps
CPU time 344.79 seconds
Started Jun 30 06:31:41 PM PDT 24
Finished Jun 30 06:37:26 PM PDT 24
Peak memory 201892 kb
Host smart-845d8f6c-f892-47ab-9238-547c68d83cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294515862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3294515862
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2473871253
Short name T93
Test name
Test status
Simulation time 491776124074 ps
CPU time 1180.68 seconds
Started Jun 30 06:31:46 PM PDT 24
Finished Jun 30 06:51:27 PM PDT 24
Peak memory 201796 kb
Host smart-41e309d4-fb1a-40bd-9baa-e8f88413edeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473871253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2473871253
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1217447883
Short name T414
Test name
Test status
Simulation time 482446603612 ps
CPU time 536.37 seconds
Started Jun 30 06:31:37 PM PDT 24
Finished Jun 30 06:40:34 PM PDT 24
Peak memory 201848 kb
Host smart-febb6dd9-cd44-41df-acb2-4e04f361c5d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217447883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1217447883
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2233196962
Short name T188
Test name
Test status
Simulation time 366544457044 ps
CPU time 66.14 seconds
Started Jun 30 06:31:45 PM PDT 24
Finished Jun 30 06:32:51 PM PDT 24
Peak memory 201824 kb
Host smart-a76e090b-57d7-40ae-accf-7aecca3cff13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233196962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2233196962
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2344119181
Short name T472
Test name
Test status
Simulation time 219876379035 ps
CPU time 228.26 seconds
Started Jun 30 06:31:46 PM PDT 24
Finished Jun 30 06:35:35 PM PDT 24
Peak memory 202096 kb
Host smart-8da8f991-95be-4248-a9fe-a2def7c7e1d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344119181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2344119181
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3570870501
Short name T430
Test name
Test status
Simulation time 114946899026 ps
CPU time 623.85 seconds
Started Jun 30 06:31:52 PM PDT 24
Finished Jun 30 06:42:17 PM PDT 24
Peak memory 202212 kb
Host smart-b821c686-ac1d-4680-89d2-b57ee9524382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570870501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3570870501
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3495930029
Short name T521
Test name
Test status
Simulation time 27125575005 ps
CPU time 59.2 seconds
Started Jun 30 06:31:55 PM PDT 24
Finished Jun 30 06:32:54 PM PDT 24
Peak memory 201688 kb
Host smart-8b47b725-7f98-4b14-b45d-53b9365c9a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495930029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3495930029
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.788744112
Short name T98
Test name
Test status
Simulation time 3259967017 ps
CPU time 2.68 seconds
Started Jun 30 06:31:52 PM PDT 24
Finished Jun 30 06:31:55 PM PDT 24
Peak memory 201628 kb
Host smart-08789d07-91f0-46df-9199-7d28e078e3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788744112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.788744112
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3591908467
Short name T395
Test name
Test status
Simulation time 6036054670 ps
CPU time 8.22 seconds
Started Jun 30 06:31:39 PM PDT 24
Finished Jun 30 06:31:48 PM PDT 24
Peak memory 201644 kb
Host smart-116aff58-fffe-4326-85a0-4188d0de985e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591908467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3591908467
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.4145169410
Short name T26
Test name
Test status
Simulation time 178135934785 ps
CPU time 439.96 seconds
Started Jun 30 06:31:51 PM PDT 24
Finished Jun 30 06:39:12 PM PDT 24
Peak memory 201864 kb
Host smart-d3015653-073a-419d-9517-0ffb20fd0f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145169410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.4145169410
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2753914282
Short name T340
Test name
Test status
Simulation time 83040824096 ps
CPU time 103.07 seconds
Started Jun 30 06:31:51 PM PDT 24
Finished Jun 30 06:33:35 PM PDT 24
Peak memory 210496 kb
Host smart-49b7a4af-336e-4a38-9db0-0beb259722fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753914282 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2753914282
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2152052316
Short name T658
Test name
Test status
Simulation time 436430739 ps
CPU time 1.53 seconds
Started Jun 30 06:32:02 PM PDT 24
Finished Jun 30 06:32:04 PM PDT 24
Peak memory 201632 kb
Host smart-a460409e-cd87-4671-8ec5-63dffe3dd762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152052316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2152052316
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2596303441
Short name T616
Test name
Test status
Simulation time 353054091572 ps
CPU time 391.01 seconds
Started Jun 30 06:31:58 PM PDT 24
Finished Jun 30 06:38:29 PM PDT 24
Peak memory 201884 kb
Host smart-69e88141-bd9f-4fd7-b037-ba0d15a39046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596303441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2596303441
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.706140320
Short name T308
Test name
Test status
Simulation time 487269262382 ps
CPU time 93.63 seconds
Started Jun 30 06:31:57 PM PDT 24
Finished Jun 30 06:33:31 PM PDT 24
Peak memory 201800 kb
Host smart-00cc14dd-3741-4d4e-a5a4-753b6c41c019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706140320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.706140320
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2211837894
Short name T182
Test name
Test status
Simulation time 161100197860 ps
CPU time 109.11 seconds
Started Jun 30 06:31:56 PM PDT 24
Finished Jun 30 06:33:46 PM PDT 24
Peak memory 201860 kb
Host smart-4c606a7e-0ec9-44ae-99af-79220ec58e1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211837894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2211837894
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2493420285
Short name T551
Test name
Test status
Simulation time 163909580655 ps
CPU time 337.5 seconds
Started Jun 30 06:31:50 PM PDT 24
Finished Jun 30 06:37:28 PM PDT 24
Peak memory 201824 kb
Host smart-2693249d-edd1-42ff-8782-d1e914783f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493420285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2493420285
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4036630084
Short name T501
Test name
Test status
Simulation time 330981695211 ps
CPU time 210.17 seconds
Started Jun 30 06:31:57 PM PDT 24
Finished Jun 30 06:35:28 PM PDT 24
Peak memory 201868 kb
Host smart-feaa48cc-ef1c-46ad-97b1-884f7ecf58b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036630084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4036630084
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.423720586
Short name T399
Test name
Test status
Simulation time 419799966479 ps
CPU time 935.44 seconds
Started Jun 30 06:31:56 PM PDT 24
Finished Jun 30 06:47:32 PM PDT 24
Peak memory 201920 kb
Host smart-959069ec-8173-4ae5-95cf-336175a52e80
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423720586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.423720586
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1571245117
Short name T406
Test name
Test status
Simulation time 110797621374 ps
CPU time 538.18 seconds
Started Jun 30 06:32:04 PM PDT 24
Finished Jun 30 06:41:02 PM PDT 24
Peak memory 202200 kb
Host smart-d96760ca-3d5c-48ff-94c8-0796d9daeb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571245117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1571245117
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1090430327
Short name T578
Test name
Test status
Simulation time 46825601607 ps
CPU time 104.75 seconds
Started Jun 30 06:32:01 PM PDT 24
Finished Jun 30 06:33:46 PM PDT 24
Peak memory 201676 kb
Host smart-a2dff802-945e-404e-8eac-5333739ba068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090430327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1090430327
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1922116168
Short name T393
Test name
Test status
Simulation time 5488524935 ps
CPU time 7.5 seconds
Started Jun 30 06:32:04 PM PDT 24
Finished Jun 30 06:32:12 PM PDT 24
Peak memory 201660 kb
Host smart-c6a7625c-1667-4c78-8af4-a3cbf14e356d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922116168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1922116168
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2615451137
Short name T773
Test name
Test status
Simulation time 5887562783 ps
CPU time 4.36 seconds
Started Jun 30 06:31:53 PM PDT 24
Finished Jun 30 06:31:57 PM PDT 24
Peak memory 201844 kb
Host smart-41cd6a93-eb4c-42d8-ade9-0a6a33855fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615451137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2615451137
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2013121829
Short name T58
Test name
Test status
Simulation time 43391137595 ps
CPU time 84.01 seconds
Started Jun 30 06:32:01 PM PDT 24
Finished Jun 30 06:33:26 PM PDT 24
Peak memory 210072 kb
Host smart-b4c2b020-1590-4a23-881f-c0a59357f899
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013121829 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2013121829
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1945932906
Short name T517
Test name
Test status
Simulation time 451314245 ps
CPU time 0.8 seconds
Started Jun 30 06:27:43 PM PDT 24
Finished Jun 30 06:27:45 PM PDT 24
Peak memory 201528 kb
Host smart-bc94b4bc-b2bc-44f7-b91d-37c406ab7f13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945932906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1945932906
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1182276003
Short name T770
Test name
Test status
Simulation time 176937364489 ps
CPU time 378.43 seconds
Started Jun 30 06:27:52 PM PDT 24
Finished Jun 30 06:34:11 PM PDT 24
Peak memory 201876 kb
Host smart-d7fa5912-e3f7-4ea4-94fa-174fae04526d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182276003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1182276003
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1564104191
Short name T492
Test name
Test status
Simulation time 486393892606 ps
CPU time 1125.12 seconds
Started Jun 30 06:27:44 PM PDT 24
Finished Jun 30 06:46:30 PM PDT 24
Peak memory 201752 kb
Host smart-595509e9-d8c2-4467-8c50-73915b20a2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564104191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1564104191
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.4148390730
Short name T267
Test name
Test status
Simulation time 327864655139 ps
CPU time 702.48 seconds
Started Jun 30 06:27:24 PM PDT 24
Finished Jun 30 06:39:09 PM PDT 24
Peak memory 201872 kb
Host smart-2b62ba13-c0e9-4f98-b700-14d193935df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148390730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.4148390730
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2110839032
Short name T670
Test name
Test status
Simulation time 162255186574 ps
CPU time 99.1 seconds
Started Jun 30 06:27:58 PM PDT 24
Finished Jun 30 06:29:38 PM PDT 24
Peak memory 201848 kb
Host smart-3f79c8ce-00ed-4127-a451-df8f14b30f10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110839032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2110839032
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.497614131
Short name T466
Test name
Test status
Simulation time 330094663948 ps
CPU time 704.59 seconds
Started Jun 30 06:27:27 PM PDT 24
Finished Jun 30 06:39:13 PM PDT 24
Peak memory 201876 kb
Host smart-4a30a5c3-bfea-41b9-b2a7-78922c5773ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497614131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.497614131
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3046156613
Short name T795
Test name
Test status
Simulation time 161744105894 ps
CPU time 379.59 seconds
Started Jun 30 06:27:47 PM PDT 24
Finished Jun 30 06:34:07 PM PDT 24
Peak memory 201928 kb
Host smart-081c281d-2df3-429e-a9d7-b17808dc852c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046156613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3046156613
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2930656154
Short name T415
Test name
Test status
Simulation time 206858413839 ps
CPU time 99.15 seconds
Started Jun 30 06:27:44 PM PDT 24
Finished Jun 30 06:29:24 PM PDT 24
Peak memory 201860 kb
Host smart-576196ba-d53a-441f-8c2b-73d49d2d5885
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930656154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2930656154
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.4061087917
Short name T732
Test name
Test status
Simulation time 100437273313 ps
CPU time 454.33 seconds
Started Jun 30 06:27:35 PM PDT 24
Finished Jun 30 06:35:09 PM PDT 24
Peak memory 202064 kb
Host smart-7885b80e-6056-434a-906e-d8d8a147222b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061087917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4061087917
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2574667179
Short name T371
Test name
Test status
Simulation time 40510142168 ps
CPU time 22.91 seconds
Started Jun 30 06:27:26 PM PDT 24
Finished Jun 30 06:27:50 PM PDT 24
Peak memory 201680 kb
Host smart-a93c6b0c-30dc-4978-8da0-d60ab092569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574667179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2574667179
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2742174893
Short name T476
Test name
Test status
Simulation time 2874843117 ps
CPU time 7.49 seconds
Started Jun 30 06:27:49 PM PDT 24
Finished Jun 30 06:27:57 PM PDT 24
Peak memory 201688 kb
Host smart-1b387361-68ce-4f6b-8101-9c1137f67eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742174893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2742174893
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.639506627
Short name T35
Test name
Test status
Simulation time 5960328887 ps
CPU time 13.31 seconds
Started Jun 30 06:27:46 PM PDT 24
Finished Jun 30 06:28:00 PM PDT 24
Peak memory 201580 kb
Host smart-31419682-5bed-43fd-8bc3-3eca20fac786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639506627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.639506627
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.4002292341
Short name T742
Test name
Test status
Simulation time 504251518667 ps
CPU time 75.9 seconds
Started Jun 30 06:27:49 PM PDT 24
Finished Jun 30 06:29:06 PM PDT 24
Peak memory 201924 kb
Host smart-11cc4c77-679c-414b-9b46-e873f2694f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002292341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
4002292341
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3088481362
Short name T21
Test name
Test status
Simulation time 120247149060 ps
CPU time 115.27 seconds
Started Jun 30 06:27:47 PM PDT 24
Finished Jun 30 06:29:43 PM PDT 24
Peak memory 210464 kb
Host smart-ac79fb46-c80e-4054-a0a0-80bf2434d377
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088481362 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3088481362
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2898253421
Short name T441
Test name
Test status
Simulation time 325567535 ps
CPU time 0.96 seconds
Started Jun 30 06:27:57 PM PDT 24
Finished Jun 30 06:27:59 PM PDT 24
Peak memory 201564 kb
Host smart-cddb4bab-aebe-4263-bda4-b6fc5f687dac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898253421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2898253421
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2568606557
Short name T285
Test name
Test status
Simulation time 510402649736 ps
CPU time 460.62 seconds
Started Jun 30 06:27:41 PM PDT 24
Finished Jun 30 06:35:23 PM PDT 24
Peak memory 201860 kb
Host smart-7b4c047f-617c-44d0-affb-cf142635d251
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568606557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2568606557
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.4028470229
Short name T768
Test name
Test status
Simulation time 170269714336 ps
CPU time 100.05 seconds
Started Jun 30 06:27:42 PM PDT 24
Finished Jun 30 06:29:23 PM PDT 24
Peak memory 201960 kb
Host smart-6fb7c5b2-0ee3-45d2-858a-1a26e4802168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028470229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.4028470229
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.957993004
Short name T109
Test name
Test status
Simulation time 325772481072 ps
CPU time 189.76 seconds
Started Jun 30 06:27:43 PM PDT 24
Finished Jun 30 06:30:54 PM PDT 24
Peak memory 201880 kb
Host smart-9687015e-b196-4a1b-b7f6-f4ce0394584e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957993004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.957993004
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.4040075300
Short name T377
Test name
Test status
Simulation time 160807389784 ps
CPU time 340.29 seconds
Started Jun 30 06:27:48 PM PDT 24
Finished Jun 30 06:33:30 PM PDT 24
Peak memory 201860 kb
Host smart-76cab9fa-2b0a-4f13-8167-1d6c4c751728
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040075300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.4040075300
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.4231201765
Short name T527
Test name
Test status
Simulation time 161352385560 ps
CPU time 173.13 seconds
Started Jun 30 06:28:04 PM PDT 24
Finished Jun 30 06:31:00 PM PDT 24
Peak memory 201952 kb
Host smart-8eaf3da9-3a95-4f58-8033-692ddcc8edef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231201765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.4231201765
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1160016361
Short name T410
Test name
Test status
Simulation time 324007889769 ps
CPU time 709.11 seconds
Started Jun 30 06:27:44 PM PDT 24
Finished Jun 30 06:39:33 PM PDT 24
Peak memory 201864 kb
Host smart-475c658e-4f85-4239-8f28-42b05c3a8ac5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160016361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1160016361
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2425477914
Short name T261
Test name
Test status
Simulation time 350683080061 ps
CPU time 400.8 seconds
Started Jun 30 06:27:47 PM PDT 24
Finished Jun 30 06:34:28 PM PDT 24
Peak memory 201932 kb
Host smart-aff798c5-c816-4181-be03-c1681e23e10e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425477914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2425477914
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3658781775
Short name T419
Test name
Test status
Simulation time 406399864854 ps
CPU time 271.27 seconds
Started Jun 30 06:27:47 PM PDT 24
Finished Jun 30 06:32:19 PM PDT 24
Peak memory 201836 kb
Host smart-1a53ebb5-a858-46f6-9a39-ff24593887c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658781775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3658781775
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.118476539
Short name T694
Test name
Test status
Simulation time 78935342026 ps
CPU time 314.09 seconds
Started Jun 30 06:27:36 PM PDT 24
Finished Jun 30 06:32:50 PM PDT 24
Peak memory 202144 kb
Host smart-560523f9-91d0-45b1-a3d1-81d743c54d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118476539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.118476539
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.410796705
Short name T409
Test name
Test status
Simulation time 35943286937 ps
CPU time 29.1 seconds
Started Jun 30 06:27:38 PM PDT 24
Finished Jun 30 06:28:08 PM PDT 24
Peak memory 201688 kb
Host smart-b273e2aa-6ed1-49d9-abd3-c1c23351fd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410796705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.410796705
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.349778231
Short name T8
Test name
Test status
Simulation time 3882958621 ps
CPU time 4.86 seconds
Started Jun 30 06:27:45 PM PDT 24
Finished Jun 30 06:27:50 PM PDT 24
Peak memory 201896 kb
Host smart-f3db9571-b37e-4f4b-a83a-c3c2864ce632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349778231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.349778231
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1143083007
Short name T608
Test name
Test status
Simulation time 5811946876 ps
CPU time 3.29 seconds
Started Jun 30 06:27:48 PM PDT 24
Finished Jun 30 06:27:53 PM PDT 24
Peak memory 201672 kb
Host smart-7d178612-47fa-4fa0-8dd5-8958e0b90e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143083007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1143083007
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.149395222
Short name T704
Test name
Test status
Simulation time 244134662642 ps
CPU time 366.16 seconds
Started Jun 30 06:27:47 PM PDT 24
Finished Jun 30 06:33:54 PM PDT 24
Peak memory 202184 kb
Host smart-b39dac49-4c1a-4c7d-ac08-25301fa99ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149395222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.149395222
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2348614185
Short name T196
Test name
Test status
Simulation time 33290236021 ps
CPU time 69.8 seconds
Started Jun 30 06:28:05 PM PDT 24
Finished Jun 30 06:29:18 PM PDT 24
Peak memory 210168 kb
Host smart-784219ad-24ba-4417-88db-6724e2159725
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348614185 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2348614185
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1577516485
Short name T780
Test name
Test status
Simulation time 500872374 ps
CPU time 0.74 seconds
Started Jun 30 06:27:46 PM PDT 24
Finished Jun 30 06:27:47 PM PDT 24
Peak memory 201648 kb
Host smart-f5d9f0ed-e4a4-4373-a58a-d8259f5983b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577516485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1577516485
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1556564388
Short name T588
Test name
Test status
Simulation time 366954482940 ps
CPU time 847.53 seconds
Started Jun 30 06:27:48 PM PDT 24
Finished Jun 30 06:41:57 PM PDT 24
Peak memory 201780 kb
Host smart-6caa9b0c-93de-4b58-bc81-e9653be8abff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556564388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1556564388
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.588048651
Short name T176
Test name
Test status
Simulation time 337382835005 ps
CPU time 836.08 seconds
Started Jun 30 06:27:46 PM PDT 24
Finished Jun 30 06:41:42 PM PDT 24
Peak memory 201924 kb
Host smart-befd9403-6cac-42e3-a31a-79a15908859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588048651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.588048651
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.236901671
Short name T321
Test name
Test status
Simulation time 170597227686 ps
CPU time 421.48 seconds
Started Jun 30 06:27:47 PM PDT 24
Finished Jun 30 06:34:49 PM PDT 24
Peak memory 201872 kb
Host smart-104fae60-cd8d-42b5-8eff-82689cfa8750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236901671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.236901671
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.797440478
Short name T564
Test name
Test status
Simulation time 329523721320 ps
CPU time 736.5 seconds
Started Jun 30 06:27:52 PM PDT 24
Finished Jun 30 06:40:09 PM PDT 24
Peak memory 201836 kb
Host smart-d8732640-9f81-4675-8666-771a62a13b83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=797440478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.797440478
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3670864008
Short name T449
Test name
Test status
Simulation time 496631557072 ps
CPU time 1063.75 seconds
Started Jun 30 06:27:28 PM PDT 24
Finished Jun 30 06:45:12 PM PDT 24
Peak memory 201880 kb
Host smart-0b6a1e58-d139-42c4-9419-b5a6d2243e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670864008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3670864008
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.477060458
Short name T529
Test name
Test status
Simulation time 167949727756 ps
CPU time 60.75 seconds
Started Jun 30 06:27:47 PM PDT 24
Finished Jun 30 06:28:48 PM PDT 24
Peak memory 201860 kb
Host smart-96e8fb84-58e7-498e-b050-a43570ae335d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=477060458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.477060458
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2886953855
Short name T480
Test name
Test status
Simulation time 567992009198 ps
CPU time 1262.57 seconds
Started Jun 30 06:27:29 PM PDT 24
Finished Jun 30 06:48:32 PM PDT 24
Peak memory 202104 kb
Host smart-0acb7806-28c5-4efa-8148-e3a7f5e676e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886953855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2886953855
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2483143940
Short name T512
Test name
Test status
Simulation time 193113735337 ps
CPU time 118.36 seconds
Started Jun 30 06:27:59 PM PDT 24
Finished Jun 30 06:29:58 PM PDT 24
Peak memory 201888 kb
Host smart-aec07ede-2ede-4abc-91c1-81914aee2394
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483143940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2483143940
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1398967114
Short name T209
Test name
Test status
Simulation time 120064631887 ps
CPU time 367.2 seconds
Started Jun 30 06:27:41 PM PDT 24
Finished Jun 30 06:33:49 PM PDT 24
Peak memory 202260 kb
Host smart-3accb0a3-53a6-49d6-832c-660dce0e9e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398967114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1398967114
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.491970912
Short name T765
Test name
Test status
Simulation time 46257238854 ps
CPU time 47.84 seconds
Started Jun 30 06:27:46 PM PDT 24
Finished Jun 30 06:28:34 PM PDT 24
Peak memory 201688 kb
Host smart-6d84b33a-636e-4beb-a170-3c82ba725441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491970912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.491970912
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2196330521
Short name T525
Test name
Test status
Simulation time 4524110258 ps
CPU time 3.34 seconds
Started Jun 30 06:27:41 PM PDT 24
Finished Jun 30 06:27:45 PM PDT 24
Peak memory 201612 kb
Host smart-6b0207e8-d2d6-44d1-a1a1-178282f4179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196330521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2196330521
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.4219175466
Short name T769
Test name
Test status
Simulation time 5971379029 ps
CPU time 4.79 seconds
Started Jun 30 06:27:48 PM PDT 24
Finished Jun 30 06:27:54 PM PDT 24
Peak memory 201680 kb
Host smart-ea218d09-4a5f-4938-abae-68b421dcba04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219175466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4219175466
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1480001564
Short name T244
Test name
Test status
Simulation time 527224460322 ps
CPU time 1239.51 seconds
Started Jun 30 06:28:01 PM PDT 24
Finished Jun 30 06:48:41 PM PDT 24
Peak memory 201924 kb
Host smart-fc2c549a-0e06-4b4c-89ba-9835c13af9da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480001564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1480001564
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2570919740
Short name T226
Test name
Test status
Simulation time 365563544676 ps
CPU time 340.42 seconds
Started Jun 30 06:27:31 PM PDT 24
Finished Jun 30 06:33:12 PM PDT 24
Peak memory 211404 kb
Host smart-32713ce0-17bb-4d19-bf53-f496e6d4d52f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570919740 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2570919740
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4111261134
Short name T753
Test name
Test status
Simulation time 378573459 ps
CPU time 1.51 seconds
Started Jun 30 06:27:55 PM PDT 24
Finished Jun 30 06:27:57 PM PDT 24
Peak memory 201604 kb
Host smart-83d295d9-769a-4c4d-8a8d-df78329ecaf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111261134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4111261134
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3214118471
Short name T650
Test name
Test status
Simulation time 554419613670 ps
CPU time 605.9 seconds
Started Jun 30 06:27:46 PM PDT 24
Finished Jun 30 06:37:52 PM PDT 24
Peak memory 201944 kb
Host smart-c00934ac-f629-4645-8f8a-5b57bf463b62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214118471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3214118471
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1822476256
Short name T247
Test name
Test status
Simulation time 188592641185 ps
CPU time 228.73 seconds
Started Jun 30 06:27:41 PM PDT 24
Finished Jun 30 06:31:31 PM PDT 24
Peak memory 201960 kb
Host smart-7aadaa70-9561-4f7f-bb7f-923f4a2b5824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822476256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1822476256
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2201179326
Short name T269
Test name
Test status
Simulation time 158328737848 ps
CPU time 102.95 seconds
Started Jun 30 06:27:49 PM PDT 24
Finished Jun 30 06:29:33 PM PDT 24
Peak memory 201780 kb
Host smart-f59e3d45-be27-4eac-a0bd-d781c1c9440b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201179326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2201179326
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3320873915
Short name T489
Test name
Test status
Simulation time 333034056093 ps
CPU time 211.95 seconds
Started Jun 30 06:27:48 PM PDT 24
Finished Jun 30 06:31:21 PM PDT 24
Peak memory 201848 kb
Host smart-729f6edd-3418-4ecd-8d74-a4af83d95c4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320873915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3320873915
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2232301350
Short name T615
Test name
Test status
Simulation time 491315110152 ps
CPU time 323.56 seconds
Started Jun 30 06:27:42 PM PDT 24
Finished Jun 30 06:33:06 PM PDT 24
Peak memory 201956 kb
Host smart-a5cf2f77-9307-412e-a267-38e4edde95d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232301350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2232301350
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3215699041
Short name T727
Test name
Test status
Simulation time 330756608803 ps
CPU time 747.37 seconds
Started Jun 30 06:27:50 PM PDT 24
Finished Jun 30 06:40:18 PM PDT 24
Peak memory 201824 kb
Host smart-7eec4825-b95d-45c6-a667-fd00322a55cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215699041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3215699041
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2846627935
Short name T286
Test name
Test status
Simulation time 661139447623 ps
CPU time 1399.04 seconds
Started Jun 30 06:27:41 PM PDT 24
Finished Jun 30 06:51:06 PM PDT 24
Peak memory 201872 kb
Host smart-86188e11-abd8-4eb9-8a73-724aa42487bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846627935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2846627935
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3296545715
Short name T508
Test name
Test status
Simulation time 592065072824 ps
CPU time 1295.39 seconds
Started Jun 30 06:27:30 PM PDT 24
Finished Jun 30 06:49:06 PM PDT 24
Peak memory 201836 kb
Host smart-14e4f797-e77d-4662-b31a-8d24bc58fac1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296545715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3296545715
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3375470071
Short name T767
Test name
Test status
Simulation time 106762821413 ps
CPU time 568.11 seconds
Started Jun 30 06:27:28 PM PDT 24
Finished Jun 30 06:36:57 PM PDT 24
Peak memory 202244 kb
Host smart-64a5b10e-0399-4f37-b260-bb10395c90f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375470071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3375470071
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2141442933
Short name T707
Test name
Test status
Simulation time 23682177133 ps
CPU time 4.31 seconds
Started Jun 30 06:27:41 PM PDT 24
Finished Jun 30 06:27:46 PM PDT 24
Peak memory 201680 kb
Host smart-44ec64c3-0fce-4453-8aac-c8e3dd532d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141442933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2141442933
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2516136253
Short name T563
Test name
Test status
Simulation time 3214975813 ps
CPU time 1.18 seconds
Started Jun 30 06:27:35 PM PDT 24
Finished Jun 30 06:27:36 PM PDT 24
Peak memory 201624 kb
Host smart-b98c61b2-f296-4360-b40b-e498d0fe366d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516136253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2516136253
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2145876954
Short name T148
Test name
Test status
Simulation time 5788215780 ps
CPU time 2.64 seconds
Started Jun 30 06:27:50 PM PDT 24
Finished Jun 30 06:27:53 PM PDT 24
Peak memory 201656 kb
Host smart-571a70d4-697a-412d-a0a3-3daff1d79f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145876954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2145876954
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1009101534
Short name T407
Test name
Test status
Simulation time 732403261420 ps
CPU time 456.79 seconds
Started Jun 30 06:27:57 PM PDT 24
Finished Jun 30 06:35:35 PM PDT 24
Peak memory 210516 kb
Host smart-2903fbba-607a-45ab-8f1f-f147a5ad9c1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009101534 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1009101534
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.276154760
Short name T553
Test name
Test status
Simulation time 473960041 ps
CPU time 0.86 seconds
Started Jun 30 06:27:55 PM PDT 24
Finished Jun 30 06:27:56 PM PDT 24
Peak memory 201624 kb
Host smart-233834bf-e940-476c-bb68-ec8419357193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276154760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.276154760
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1098228860
Short name T235
Test name
Test status
Simulation time 201009282414 ps
CPU time 454.85 seconds
Started Jun 30 06:27:54 PM PDT 24
Finished Jun 30 06:35:30 PM PDT 24
Peak memory 201936 kb
Host smart-af7fa786-759c-40cc-af32-192e7a0a89e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098228860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1098228860
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.355242475
Short name T674
Test name
Test status
Simulation time 194936514486 ps
CPU time 480.21 seconds
Started Jun 30 06:27:48 PM PDT 24
Finished Jun 30 06:35:49 PM PDT 24
Peak memory 201832 kb
Host smart-ab766f92-572d-4356-808a-e978bc3f5263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355242475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.355242475
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2002318592
Short name T335
Test name
Test status
Simulation time 485219131272 ps
CPU time 300.27 seconds
Started Jun 30 06:27:56 PM PDT 24
Finished Jun 30 06:32:57 PM PDT 24
Peak memory 201900 kb
Host smart-c7cd49ef-aba9-44cb-92e3-9a10ce6de31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002318592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2002318592
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2757521634
Short name T758
Test name
Test status
Simulation time 168875551627 ps
CPU time 377.03 seconds
Started Jun 30 06:27:56 PM PDT 24
Finished Jun 30 06:34:14 PM PDT 24
Peak memory 201820 kb
Host smart-ce6b48fa-c578-4735-965f-1972217d470c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757521634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2757521634
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.613594146
Short name T725
Test name
Test status
Simulation time 491072114901 ps
CPU time 1070.15 seconds
Started Jun 30 06:27:44 PM PDT 24
Finished Jun 30 06:45:35 PM PDT 24
Peak memory 201724 kb
Host smart-71f6491c-fa4f-46d2-83ed-a1e5d3256f7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=613594146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.613594146
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.719860566
Short name T648
Test name
Test status
Simulation time 553511176582 ps
CPU time 97.25 seconds
Started Jun 30 06:27:50 PM PDT 24
Finished Jun 30 06:29:28 PM PDT 24
Peak memory 201908 kb
Host smart-4b9975d7-d3f6-4a0c-a833-4dbf4e48ebbc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719860566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.719860566
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.524530404
Short name T171
Test name
Test status
Simulation time 204176897907 ps
CPU time 123.98 seconds
Started Jun 30 06:27:56 PM PDT 24
Finished Jun 30 06:30:01 PM PDT 24
Peak memory 201836 kb
Host smart-2be48ced-d90a-4590-bff8-de9522948138
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524530404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.524530404
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.754550969
Short name T483
Test name
Test status
Simulation time 73572158773 ps
CPU time 301.43 seconds
Started Jun 30 06:28:06 PM PDT 24
Finished Jun 30 06:33:11 PM PDT 24
Peak memory 202104 kb
Host smart-978b2ce1-0267-4573-b7fc-ebf68b439447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754550969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.754550969
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3474690423
Short name T605
Test name
Test status
Simulation time 26210415306 ps
CPU time 13.29 seconds
Started Jun 30 06:27:57 PM PDT 24
Finished Jun 30 06:28:11 PM PDT 24
Peak memory 201680 kb
Host smart-ec3b3670-620b-45a1-932a-e42e1b569e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474690423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3474690423
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.484296034
Short name T360
Test name
Test status
Simulation time 4315801805 ps
CPU time 2.99 seconds
Started Jun 30 06:27:51 PM PDT 24
Finished Jun 30 06:27:55 PM PDT 24
Peak memory 201628 kb
Host smart-fdbfb446-f1c4-443c-bc92-6e166fe0182f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484296034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.484296034
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.245877861
Short name T149
Test name
Test status
Simulation time 6135142463 ps
CPU time 7.66 seconds
Started Jun 30 06:27:55 PM PDT 24
Finished Jun 30 06:28:04 PM PDT 24
Peak memory 201688 kb
Host smart-bfb23a37-44d2-416b-9e15-c1e576613c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245877861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.245877861
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3210357761
Short name T730
Test name
Test status
Simulation time 493452589405 ps
CPU time 512.87 seconds
Started Jun 30 06:27:50 PM PDT 24
Finished Jun 30 06:36:23 PM PDT 24
Peak memory 201884 kb
Host smart-9bb02817-df8b-49b2-b119-47d41d4e0e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210357761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3210357761
Directory /workspace/9.adc_ctrl_stress_all/latest
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