Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7336	1			T1	11		T7	55		T10	29
testmodes[AdcCtrlTestmodeNormal]	5879	1			T1	9		T2	1		T4	1
testmodes[AdcCtrlTestmodeLowpower]	6073	1			T3	16		T6	19		T7	79
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3935	1			T1	7		T7	16		T10	23
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1850	1			T1	4		T7	17		T10	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1443	1			T7	22		T10	4		T36	11
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1869	1			T1	3		T7	21		T10	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2154	1			T1	5		T6	2		T7	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1509	1			T6	1		T7	19		T10	5
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1421	1			T7	18		T10	2		T36	10
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1526	1			T7	23		T10	8		T36	9
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2882	1			T3	15		T6	18		T7	38