Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23973

1

T1

20

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3536

1

T6

2

T9

1

T10

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20966

1

T1

20

T2

1

T3

16

auto[1]

6543

1

T4

9

T5

1

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	465	1			T7	2		T10	2		T36	1
values[0]	43	1			T7	21		T213	9		T214	1
values[1]	682	1			T6	1		T24	15		T16	2
values[2]	3079	1			T5	1		T8	25		T9	2
values[3]	700	1			T4	9		T7	8		T11	1
values[4]	773	1			T12	14		T37	3		T128	17
values[5]	635	1			T28	15		T127	15		T151	11
values[6]	623	1			T2	1		T9	1		T54	16
values[7]	557	1			T10	7		T24	19		T128	27
values[8]	643	1			T6	1		T14	7		T37	4
values[9]	1451	1			T6	1		T24	7		T15	9
minimum	17858	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	840	1			T6	1		T7	21		T24	15
values[1]	3120	1			T5	1		T8	25		T9	2
values[2]	777	1			T4	9		T7	8		T11	1
values[3]	657	1			T37	3		T129	7		T215	5
values[4]	699	1			T28	15		T127	15		T132	10
values[5]	543	1			T2	1		T24	19		T54	16
values[6]	684	1			T6	1		T9	1		T10	7
values[7]	583	1			T14	7		T126	19		T139	1
values[8]	1010	1			T24	7		T15	9		T138	8
values[9]	269	1			T6	1		T127	15		T16	4
minimum	18327	1			T1	20		T3	16		T6	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	11		T24	12		T151	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	1		T194	1		T216	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1784	1			T5	1		T8	25		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	1		T127	1		T16	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	1		T7	3		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	1		T12	1		T128	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T134	1		T165	1		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T37	1		T129	1		T215	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T28	11		T127	1		T132	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T186	1		T136	11		T217	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	1		T54	11		T130	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T24	9		T151	1		T152	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	1		T9	1		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T10	5		T128	12		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	5		T218	3		T140	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T126	10		T139	1		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T24	2		T15	7		T138	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T15	1		T54	15		T219	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T127	1		T16	2		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T6	1		T172	9		T82	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18182	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T214	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T7	10		T24	3		T151	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	3		T43	2		T220	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T26	22		T149	14		T54	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T16	1		T221	3		T222	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	8		T7	5		T128	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	13		T128	8		T219	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T165	9		T43	1		T223	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T37	2		T129	6		T136	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T28	4		T127	14		T153	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T136	9		T147	4		T224	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T54	5		T201	21		T44	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T24	10		T151	10		T152	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T37	3		T153	1		T33	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	2		T128	15		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T14	2		T218	2		T78	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T126	9		T165	11		T225	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T24	5		T15	1		T38	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T54	13		T219	10		T48	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T127	14		T16	2		T135	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T82	10		T226	12		T227	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	3		T15	6		T16	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	465	1			T7	2		T10	2		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T7	11		T213	9		T228	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T214	1		T23	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T24	12		T151	1		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T16	1		T186	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1778	1			T5	1		T8	25		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	1		T127	1		T216	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T4	1		T7	3		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	1		T16	1		T143	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T134	1		T165	1		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	1		T37	1		T128	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T28	11		T127	1		T132	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T151	1		T215	5		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T9	1		T54	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T152	17		T229	1		T147	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T201	23		T140	15		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	5		T24	9		T128	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	1		T14	5		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T126	10		T194	1		T136	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T24	2		T15	7		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	436	1			T6	1		T15	1		T54	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17716	1			T1	20		T3	16		T6	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T7	10		T228	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T23	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T24	3		T129	12		T17	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T16	1		T40	3		T43	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T26	22		T149	14		T54	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T221	3		T230	15		T231	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	8		T7	5		T128	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T82	14		T222	13		T232	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T165	9		T223	2		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	13		T37	2		T128	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T28	4		T127	14		T153	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T151	10		T136	9		T224	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T54	5		T44	1		T33	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T152	16		T147	4		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T201	21		T153	1		T234	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T10	2		T24	10		T128	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T14	2		T37	3		T218	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T126	9		T136	9		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T24	5		T15	1		T127	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T54	13		T219	10		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T7	11		T24	4		T151	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	1		T194	1		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T5	1		T8	2		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	1		T127	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	9		T7	6		T128	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	1		T12	14		T128	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T134	1		T165	10		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T37	3		T129	7		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T28	5		T127	15		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T186	1		T136	10		T217	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T2	1		T54	6		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T24	11		T151	11		T152	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	1		T9	1		T37	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	7		T128	16		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	7		T218	3		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T126	10		T139	1		T165	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T24	6		T15	7		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T15	1		T54	14		T219	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T127	15		T16	4		T135	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T6	1		T172	1		T82	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18326	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T214	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	10		T24	11		T130	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T216	6		T40	4		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T8	23		T29	24		T45	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T221	3		T20	1		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	2		T215	13		T147	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T128	8		T219	9		T223	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T43	1		T223	2		T155	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T215	4		T136	12		T155	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T28	10		T132	9		T166	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T136	10		T217	16		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T54	10		T130	3		T132	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T24	8		T152	16		T213	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T140	14		T33	9		T155	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T128	11		T133	9		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T218	2		T140	12		T236	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T126	9		T19	3		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T24	1		T15	1		T138	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T54	14		T219	12		T48	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T135	12		T238	13		T239	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T172	8		T82	11		T240	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	465	1			T7	2		T10	2		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T7	11		T213	1		T228	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T214	1		T23	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T24	4		T151	1		T129	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	1		T16	2		T186	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T5	1		T8	2		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	1		T127	1		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	9		T7	6		T128	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	1		T16	1		T143	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T134	1		T165	10		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T12	14		T37	3		T128	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T28	5		T127	15		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T151	11		T215	1		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T2	1		T9	1		T54	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T152	17		T229	1		T147	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T201	23		T140	1		T153	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	7		T24	11		T128	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T6	1		T14	7		T37	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T126	10		T194	1		T136	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	425	1			T24	6		T15	7		T127	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	422	1			T6	1		T15	1		T54	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17858	1			T1	20		T3	16		T6	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T7	10		T213	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T23	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T24	11		T130	7		T17	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T40	4		T43	1		T217	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T8	23		T29	24		T45	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T216	6		T221	3		T20	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	2		T215	13		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T82	16		T222	9		T241	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T223	2		T155	10		T242	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T128	8		T219	9		T136	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T28	10		T132	9		T153	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T215	4		T136	10		T217	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T54	10		T130	3		T132	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T152	16		T147	9		T233	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T201	21		T140	14		T243	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T24	8		T128	11		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T218	2		T236	8		T156	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T126	9		T136	2		T235	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T24	1		T15	1		T138	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T54	14		T219	12		T172	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23927

1

T1

20

T3

16

T4

9

auto[ADC_CTRL_FILTER_COND_OUT]

3582

1

T2

1

T6

2

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21565

1

T1

20

T2

1

T3

16

auto[1]

5944

1

T5

1

T7

29

T8

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T244	1		-	-		-	-
values[0]	122	1			T14	7		T145	1		T135	26
values[1]	713	1			T37	4		T128	27		T151	11
values[2]	702	1			T2	1		T6	1		T28	15
values[3]	641	1			T7	21		T127	15		T16	1
values[4]	2894	1			T5	1		T8	25		T35	1
values[5]	634	1			T9	1		T24	15		T128	2
values[6]	662	1			T9	1		T15	1		T219	23
values[7]	952	1			T6	1		T24	7		T15	7
values[8]	665	1			T7	8		T12	1		T15	1
values[9]	1200	1			T4	9		T6	1		T9	1
minimum	18323	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1003	1			T14	7		T37	4		T128	27
values[1]	654	1			T2	1		T6	1		T7	21
values[2]	649	1			T127	30		T16	1		T54	23
values[3]	2805	1			T5	1		T8	25		T35	1
values[4]	763	1			T9	2		T130	4		T216	7
values[5]	665	1			T6	1		T15	1		T16	2
values[6]	1027	1			T12	1		T24	7		T15	1
values[7]	587	1			T12	14		T15	7		T128	17
values[8]	795	1			T4	9		T6	1		T7	8
values[9]	219	1			T9	1		T10	7		T141	13
minimum	18342	1			T1	20		T3	16		T6	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T151	1		T129	1		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T14	5		T37	1		T128	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T6	1		T7	11		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	1		T28	11		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T127	1		T132	17		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T127	1		T16	1		T54	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1613	1			T5	1		T8	25		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T24	9		T131	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	2		T130	4		T147	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T216	7		T143	1		T245	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	1		T194	1		T140	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	1		T16	1		T219	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T24	2		T15	1		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	1		T172	9		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	6		T128	9		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T219	10		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	1		T7	3		T16	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	1		T11	1		T138	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T10	5		T141	13		T220	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T9	1		T142	1		T82	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18182	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T246	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T151	10		T129	12		T38	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	2		T37	3		T128	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	10		T151	10		T218	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T28	4		T37	2		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T127	14		T220	5		T230	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T127	14		T54	9		T17	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T24	3		T26	22		T149	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T24	10		T238	12		T165	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T147	4		T84	7		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T245	3		T78	14		T82	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T226	10		T22	3		T98	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	1		T219	10		T126	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T24	5		T129	6		T136	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T135	13		T136	22		T165	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T15	1		T128	8		T80	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	13		T219	10		T201	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T4	8		T7	5		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T218	7		T40	3		T155	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T10	2		T220	9		T247	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T82	14		T248	10		T249	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T246	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T244	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T145	1		T250	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T14	5		T135	13		T246	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T151	1		T129	1		T215	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T37	1		T128	12		T156	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	1		T151	1		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T2	1		T28	11		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	11		T130	8		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T127	1		T16	1		T54	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T5	1		T8	25		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T24	9		T131	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	1		T24	12		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T165	1		T143	1		T245	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	1		T15	1		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T219	13		T126	10		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T24	2		T15	6		T128	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T6	1		T16	1		T135	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	3		T15	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	1		T172	9		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T4	1		T10	5		T16	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T6	1		T9	1		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18181	1			T1	20		T3	16		T6	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T14	2		T135	13		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T151	10		T129	12		T153	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T37	3		T128	15		T251	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T151	10		T38	14		T201	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T28	4		T48	2		T152	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	10		T218	2		T220	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T127	14		T54	9		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T26	22		T127	14		T149	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T24	10		T238	12		T17	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T24	3		T128	1		T147	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T165	9		T245	3		T82	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T84	7		T222	10		T226	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T219	10		T126	9		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	5		T15	1		T128	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T16	1		T135	13		T136	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	5		T80	2		T221	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T136	13		T201	10		T44	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T4	8		T10	2		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T12	13		T219	10		T218	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3