Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23774

1

T1

20

T2

1

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3735

1

T7

29

T12

1

T24

41

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21564

1

T1

20

T2

1

T3

16

auto[1]

5945

1

T4

9

T5

1

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	368	1			T9	1		T54	28		T219	43
values[0]	23	1			T83	1		T299	21		T278	1
values[1]	1012	1			T2	1		T6	1		T10	7
values[2]	2980	1			T5	1		T8	25		T35	1
values[3]	706	1			T9	2		T130	4		T132	23
values[4]	731	1			T7	8		T15	8		T37	3
values[5]	631	1			T6	1		T24	15		T15	1
values[6]	658	1			T4	9		T6	1		T7	21
values[7]	691	1			T11	1		T127	1		T16	4
values[8]	426	1			T128	27		T178	2		T39	2
values[9]	960	1			T12	1		T28	15		T127	30
minimum	18323	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	826	1			T2	1		T12	14		T24	19
values[1]	2987	1			T5	1		T8	25		T35	1
values[2]	772	1			T7	8		T9	2		T132	23
values[3]	676	1			T6	1		T15	8		T37	3
values[4]	698	1			T6	1		T24	15		T15	1
values[5]	606	1			T4	9		T7	21		T14	7
values[6]	634	1			T11	1		T16	4		T145	1
values[7]	489	1			T128	27		T151	11		T178	2
values[8]	1030	1			T9	1		T12	1		T28	15
values[9]	125	1			T54	28		T38	19		T173	1
minimum	18666	1			T1	20		T3	16		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	1		T12	1		T54	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	9		T151	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1692	1			T5	1		T8	25		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T16	1		T141	11		T17	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	2		T132	23		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	3		T136	13		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	1		T37	1		T172	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	7		T151	1		T132	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T15	1		T166	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T24	12		T129	1		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	1		T14	5		T128	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	11		T24	2		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	1		T16	2		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T152	17		T165	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T128	12		T39	2		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T151	1		T178	1		T140	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T9	1		T219	10		T215	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T12	1		T28	11		T127	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T225	1		T220	10		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T54	15		T38	5		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18233	1			T1	20		T3	16		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T258	11		T201	11		T141	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	13		T54	9		T126	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T24	10		T151	10		T238	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T26	22		T149	14		T37	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T17	22		T40	3		T153	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T196	3		T233	10		T226	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	5		T136	13		T223	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T37	2		T48	2		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	1		T135	13		T165	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T220	13		T296	9		T297	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T24	3		T129	12		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	8		T14	2		T128	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	10		T24	5		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	2		T147	4		T33	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T152	16		T165	9		T154	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T128	15		T147	10		T296	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T151	10		T178	1		T43	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T219	10		T44	1		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T28	4		T127	28		T219	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T225	12		T220	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T54	13		T38	14		T22	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T10	2		T14	3		T15	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T201	12		T82	10		T243	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T9	1		T219	10		T44	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T54	15		T219	13		T218	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T83	1		T299	11		T278	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T2	1		T6	1		T10	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T24	9		T151	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1675	1			T5	1		T8	25		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	1		T141	11		T216	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	2		T130	4		T132	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T136	13		T17	16		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T37	1		T172	9		T48	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	3		T15	7		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	1		T15	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T24	12		T129	1		T132	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	1		T6	1		T14	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	11		T24	2		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T11	1		T16	2		T128	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T127	1		T139	1		T257	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T128	12		T39	2		T147	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T178	1		T43	6		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T215	5		T139	1		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T12	1		T28	11		T127	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18181	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T219	10		T44	1		T18	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T54	13		T219	10		T218	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T299	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T10	2		T12	13		T54	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T24	10		T151	10		T238	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T26	22		T149	14		T37	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T40	3		T153	14		T234	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T233	10		T226	10		T227	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T136	13		T17	22		T78	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T37	2		T48	2		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	5		T15	1		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T220	13		T296	9		T300	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T24	3		T129	12		T147	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	8		T14	2		T218	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	10		T24	5		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T16	2		T128	8		T129	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T152	16		T165	9		T154	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T128	15		T147	4		T232	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T178	1		T43	2		T190	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T147	10		T225	12		T170	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T28	4		T127	28		T151	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T2	1		T12	14		T54	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T24	11		T151	11		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T5	1		T8	2		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	1		T141	1		T17	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	2		T132	1		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T7	6		T136	14		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	1		T37	3		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T15	7		T151	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	1		T15	1		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T24	4		T129	13		T135	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	9		T14	7		T128	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	11		T24	6		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T11	1		T16	4		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	17		T165	10		T154	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T128	16		T39	2		T147	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T151	11		T178	2		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	1		T219	11		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T12	1		T28	5		T127	30
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T225	13		T220	10		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T54	14		T38	18		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18394	1			T1	20		T3	16		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T258	1		T201	13		T141	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T54	12		T126	9		T215	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T24	8		T238	13		T201	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T8	23		T29	24		T45	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T141	10		T17	9		T40	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T132	22		T196	3		T233	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	2		T136	12		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T172	8		T48	17		T155	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	1		T132	9		T135	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T166	13		T156	13		T269	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T24	11		T135	12		T253	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T128	8		T130	7		T218	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	10		T24	1		T257	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T147	9		T33	9		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T152	16		T233	7		T221	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T128	11		T156	15		T213	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T140	2		T43	1		T241	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T219	9		T215	4		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T28	10		T138	7		T219	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T220	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T54	14		T38	1		T22	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T133	9		T243	7		T315	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T258	10		T201	10		T141	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T9	1		T219	11		T44	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T54	14		T219	11		T218	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T83	1		T299	11		T278	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T2	1		T6	1		T10	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T24	11		T151	11		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T5	1		T8	2		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T16	1		T141	1		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T130	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T136	14		T17	29		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T37	3		T172	1		T48	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T7	6		T15	7		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T6	1		T15	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T24	4		T129	13		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	9		T6	1		T14	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	11		T24	6		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T11	1		T16	4		T128	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T127	1		T139	1		T257	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T128	16		T39	2		T147	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T178	2		T43	7		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T215	1		T139	1		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T12	1		T28	5		T127	30
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T219	9		T44	2		T221	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T54	14		T219	12		T218	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T299	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T54	12		T126	9		T215	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T24	8		T258	10		T238	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T8	23		T29	24		T45	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T141	10		T216	17		T40	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T130	3		T132	22		T233	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T136	12		T17	9		T288	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T172	8		T48	17		T155	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	2		T15	1		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T156	13		T269	14		T220	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	11		T132	9		T253	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T130	7		T218	2		T166	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	10		T24	1		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T128	8		T33	9		T235	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T257	2		T152	16		T233	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T128	11		T147	9		T304	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T43	1		T241	9		T174	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T215	4		T252	13		T156	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T28	10		T138	7		T38	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20