Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23834

1

T1

20

T3

16

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

3675

1

T2

1

T4

9

T6

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21209

1

T1

20

T2

1

T3

16

auto[1]

6300

1

T5

1

T6

1

T8

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T241	10		T182	11		-	-
values[0]	23	1			T286	1		T197	1		T282	4
values[1]	623	1			T9	1		T16	4		T138	8
values[2]	582	1			T127	15		T54	16		T219	23
values[3]	759	1			T127	1		T16	3		T128	2
values[4]	709	1			T2	1		T6	3		T15	7
values[5]	3127	1			T4	9		T5	1		T8	25
values[6]	791	1			T10	7		T11	1		T28	15
values[7]	763	1			T9	1		T15	1		T151	1
values[8]	572	1			T24	7		T54	35		T129	7
values[9]	1216	1			T7	29		T9	1		T12	14
minimum	18323	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	782	1			T9	1		T127	15		T138	8
values[1]	606	1			T16	6		T54	16		T128	2
values[2]	723	1			T6	1		T15	7		T127	1
values[3]	3130	1			T2	1		T4	9		T5	1
values[4]	791	1			T12	1		T28	15		T127	15
values[5]	787	1			T11	1		T151	1		T129	13
values[6]	564	1			T10	7		T24	7		T15	1
values[7]	711	1			T9	1		T54	7		T129	7
values[8]	934	1			T7	29		T9	1		T14	7
values[9]	110	1			T12	14		T139	1		T223	3
minimum	18371	1			T1	20		T3	16		T6	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T151	1		T38	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T127	1		T138	8		T201	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T16	2		T54	11		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	1		T219	13		T133	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	6		T16	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	1		T127	1		T215	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1661	1			T5	1		T6	1		T8	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	1		T4	1		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T28	11		T37	2		T48	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	1		T127	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T11	1		T131	1		T132	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T151	1		T129	1		T215	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	1		T134	1		T43	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	5		T24	2		T54	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	1		T54	3		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T218	8		T201	11		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T7	14		T9	1		T24	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	5		T186	2		T140	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T12	1		T139	1		T322	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T223	2		T147	9		T268	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18191	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T279	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T151	10		T38	14		T178	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T127	14		T201	19		T165	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T16	2		T54	5		T128	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T16	1		T219	10		T133	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	1		T136	9		T165	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T136	13		T223	1		T234	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T26	22		T149	14		T159	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	8		T24	10		T128	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T28	4		T37	5		T48	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T127	14		T151	10		T17	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T135	13		T40	3		T223	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T129	12		T82	14		T196	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T43	2		T155	13		T220	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	2		T24	5		T54	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T54	4		T129	6		T126	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T218	7		T201	12		T235	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	15		T24	3		T128	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	2		T19	1		T236	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T12	13		T322	5		T198	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T223	1		T147	9		T268	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	3		T15	6		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T279	15		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T182	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T241	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T286	1		T197	1		T323	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T282	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T16	2		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T138	8		T201	13		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T54	11		T139	1		T140	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T127	1		T219	13		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T16	1		T128	1		T130	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T127	1		T16	1		T215	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	1		T15	6		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	1		T6	2		T128	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1641	1			T5	1		T8	25		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T4	1		T12	1		T24	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T11	1		T28	11		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	5		T127	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T9	1		T15	1		T43	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T151	1		T219	10		T275	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T54	3		T129	1		T126	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T24	2		T54	15		T218	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T7	14		T9	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T14	5		T186	2		T140	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18181	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T182	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T279	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	2		T151	10		T38	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T201	19		T165	9		T80	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T54	5		T251	1		T23	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T127	14		T219	10		T155	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T128	1		T165	11		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T16	1		T133	9		T223	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	1		T136	9		T243	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T128	8		T136	22		T147	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T26	22		T149	14		T37	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	8		T24	10		T17	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T28	4		T48	2		T135	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	2		T127	14		T151	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T43	2		T155	13		T78	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T219	10		T82	14		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T54	4		T129	6		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T24	5		T54	13		T218	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T7	15		T12	13		T24	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T14	2		T223	1		T147	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	1		T151	11		T38	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T127	15		T138	1		T201	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T16	4		T54	6		T128	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T16	2		T219	11		T133	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	6		T16	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	1		T127	1		T215	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T5	1		T6	1		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	1		T4	9		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T28	5		T37	7		T48	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	1		T127	15		T151	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	1		T131	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T151	1		T129	13		T215	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T15	1		T134	1		T43	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	7		T24	6		T54	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	1		T54	5		T129	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T218	8		T201	13		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T7	17		T9	1		T24	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	7		T186	2		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T12	14		T139	1		T322	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T223	2		T147	10		T268	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18332	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T279	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T38	1		T132	9		T218	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T138	7		T201	11		T216	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T54	10		T130	3		T140	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T219	12		T133	9		T141	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T136	10		T270	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T215	13		T136	12		T252	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T8	23		T29	24		T45	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T24	8		T128	8		T136	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T28	10		T48	17		T238	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T172	8		T253	10		T141	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T132	16		T135	12		T40	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T215	4		T82	16		T196	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T43	1		T217	9		T155	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T24	1		T54	14		T219	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T54	2		T126	9		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T218	7		T201	10		T235	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T7	12		T24	11		T128	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T140	2		T19	1		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T262	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T223	1		T147	8		T268	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T324	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T279	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T182	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T241	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T286	1		T197	1		T323	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T282	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T16	4		T151	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T138	1		T201	21		T165	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T54	6		T139	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T127	15		T219	11		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	1		T128	2		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T127	1		T16	2		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T15	6		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	1		T6	2		T128	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T5	1		T8	2		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T4	9		T12	1		T24	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	1		T28	5		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T10	7		T127	15		T151	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	1		T15	1		T43	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T151	1		T219	11		T275	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T54	5		T129	7		T126	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T24	6		T54	14		T218	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T7	17		T9	1		T12	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T14	7		T186	2		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T241	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T279	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T282	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T38	1		T132	9		T218	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T138	7		T201	11		T80	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T54	10		T140	12		T251	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T219	12		T141	12		T216	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T130	3		T140	14		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T215	13		T133	9		T216	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T15	1		T136	10		T156	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T128	8		T136	14		T235	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T8	23		T29	24		T45	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T24	8		T17	9		T153	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T28	10		T48	17		T132	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T172	8		T215	4		T132	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T43	1		T217	9		T155	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T219	9		T82	16		T196	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T54	2		T126	9		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T24	1		T54	14		T218	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T7	12		T24	11		T128	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T140	2		T223	1		T147	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20