Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27509

1

T1

20

T2

1

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23966

1

T1

20

T3

16

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

3543

1

T2

1

T4

9

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21103

1

T1

20

T2

1

T3

16

auto[1]

6406

1

T5

1

T8

25

T9

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23503

1

T1

20

T2

1

T3

16

auto[1]

4006

1

T4

8

T7

15

T10

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	271	1			T7	29		T12	14		T128	27
values[0]	18	1			T286	1		T325	1		T279	16
values[1]	631	1			T9	1		T138	8		T151	11
values[2]	599	1			T127	15		T16	4		T54	16
values[3]	695	1			T15	7		T127	1		T16	3
values[4]	776	1			T2	1		T6	3		T24	19
values[5]	3120	1			T4	9		T5	1		T8	25
values[6]	739	1			T10	7		T11	1		T127	15
values[7]	776	1			T9	1		T15	1		T151	1
values[8]	574	1			T24	7		T54	35		T129	7
values[9]	987	1			T9	1		T14	7		T24	15
minimum	18323	1			T1	20		T3	16		T6	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	658	1			T127	15		T138	8		T151	11
values[1]	590	1			T16	6		T54	16		T128	2
values[2]	785	1			T6	1		T15	7		T127	1
values[3]	3117	1			T2	1		T4	9		T5	1
values[4]	779	1			T12	1		T28	15		T127	15
values[5]	769	1			T10	7		T11	1		T151	1
values[6]	643	1			T24	7		T15	1		T54	28
values[7]	678	1			T9	1		T54	7		T129	7
values[8]	939	1			T7	29		T9	1		T14	7
values[9]	94	1			T12	14		T223	3		T322	6
minimum	18457	1			T1	20		T3	16		T6	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

4215

1

T7

12

T8

23

T24

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T138	8		T151	1		T132	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T127	1		T201	1		T216	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T16	2		T54	11		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T16	1		T219	13		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	6		T16	1		T130	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T6	1		T127	1		T215	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1658	1			T5	1		T6	2		T8	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	1		T4	1		T24	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T48	18		T17	16		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	1		T28	11		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T11	1		T131	1		T132	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	5		T151	1		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	1		T54	15		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T24	2		T219	10		T132	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	1		T54	3		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T218	8		T201	11		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T7	14		T9	1		T128	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	5		T24	12		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T12	1		T322	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T223	2		T256	14		T326	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18207	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T9	1		T201	12		T165	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T151	10		T178	1		T147	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T127	14		T201	10		T80	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T16	2		T54	5		T128	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T16	1		T219	10		T155	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	1		T136	9		T165	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T133	9		T136	13		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T26	22		T149	14		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	8		T24	10		T128	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	2		T17	22		T245	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T28	4		T127	14		T37	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T135	13		T40	3		T223	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	2		T129	12		T82	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T54	13		T43	2		T155	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T24	5		T219	10		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T54	4		T129	6		T126	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T218	7		T201	12		T235	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	15		T128	15		T152	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	2		T24	3		T147	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T12	13		T322	5		T198	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T223	1		T327	7		T290	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	3		T15	6		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T201	9		T165	9		T174	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T7	14		T12	1		T128	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T140	3		T147	9		T305	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T286	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T325	1		T279	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T138	8		T151	1		T38	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	1		T201	13		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T16	2		T54	11		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T127	1		T219	13		T141	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	6		T16	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T127	1		T16	1		T215	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	2		T166	1		T136	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T2	1		T6	1		T24	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1672	1			T5	1		T8	25		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T4	1		T12	1		T28	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T11	1		T131	1		T48	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	5		T127	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T9	1		T15	1		T132	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T151	1		T219	10		T132	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T54	18		T129	1		T126	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T24	2		T218	8		T201	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T9	1		T145	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	5		T24	12		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18181	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T7	15		T12	13		T128	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T147	9		T328	12		T98	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T279	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T151	10		T38	14		T178	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T201	19		T165	9		T80	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T16	2		T54	5		T153	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T127	14		T219	10		T155	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T15	1		T128	1		T165	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	1		T133	9		T43	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T136	9		T243	10		T226	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T24	10		T128	8		T136	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T26	22		T149	14		T37	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T4	8		T28	4		T37	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T48	2		T135	13		T40	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	2		T127	14		T151	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T43	2		T155	13		T296	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T219	10		T82	14		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T54	17		T129	6		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T24	5		T218	7		T201	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T152	16		T33	4		T78	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	2		T24	3		T223	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T15	6		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T138	1		T151	11		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T127	15		T201	11		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T16	4		T54	6		T128	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T16	2		T219	11		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	6		T16	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	1		T127	1		T215	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T5	1		T6	2		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	1		T4	9		T24	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T48	3		T17	29		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	1		T28	5		T127	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	1		T131	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	7		T151	1		T129	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	1		T54	14		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T24	6		T219	11		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	1		T54	5		T129	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T218	8		T201	13		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T7	17		T9	1		T128	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	7		T24	4		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T12	14		T322	6		T198	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T223	2		T256	1		T326	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18368	1			T1	20		T3	16		T6	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T9	1		T201	10		T165	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T138	7		T132	9		T140	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T216	17		T254	10		T252	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T54	10		T218	2		T140	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T219	12		T141	12		T216	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T15	1		T130	3		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T215	13		T133	9		T136	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T8	23		T29	24		T45	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T24	8		T128	8		T136	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T48	17		T17	9		T217	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T28	10		T172	8		T238	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T132	16		T135	12		T141	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T215	4		T253	10		T82	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T54	14		T43	1		T217	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T24	1		T219	9		T132	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T54	2		T126	9		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T218	7		T201	10		T235	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T7	12		T128	11		T130	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T24	11		T140	2		T147	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T262	2		T310	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T223	1		T256	13		T326	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T38	1		T155	10		T303	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T201	11		T174	11		T282	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T7	17		T12	14		T128	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T140	1		T147	10		T305	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T286	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T325	1		T279	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T138	1		T151	11		T38	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	1		T201	21		T165	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	4		T54	6		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T127	15		T219	11		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	6		T16	1		T128	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T127	1		T16	2		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	2		T166	1		T136	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T2	1		T6	1		T24	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T5	1		T8	2		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	9		T12	1		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	1		T131	1		T48	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	7		T127	15		T151	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	1		T15	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T151	1		T219	11		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T54	19		T129	7		T126	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T24	6		T218	8		T201	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T9	1		T145	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	7		T24	4		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T1	20		T3	16		T6	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T7	12		T128	11		T130	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T140	2		T147	8		T241	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T279	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T138	7		T38	1		T132	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T201	11		T80	1		T233	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T54	10		T140	12		T153	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T219	12		T141	12		T216	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T15	1		T130	3		T140	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T215	13		T133	9		T43	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T136	10		T156	15		T243	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T24	8		T128	8		T136	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T8	23		T29	24		T45	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T28	10		T153	14		T252	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T48	17		T135	12		T141	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T172	8		T215	4		T238	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T132	16		T43	1		T217	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T219	9		T132	22		T82	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T54	16		T126	9		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T24	1		T218	7		T201	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T166	13		T152	16		T33	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T24	11		T223	1		T235	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23294

1

T1

20

T2

1

T3

16

auto[1]

auto[0]

4215

1

T7

12

T8

23

T24

20